kunlun/inc/hw/reg/riscv2/15/pwm_new_reg.h

//-----------------------------------
#define CFG_TBCTL_ADDR 0x0000
#define CLK_DIV0_OFFSET 24
#define CLK_DIV0_MASK 0xFF000000
#define CLK_DIV1_OFFSET 16
#define CLK_DIV1_MASK 0x00FF0000
#define SINGL_PULS_EN_OFFSET 15
#define SINGL_PULS_EN_MASK 0x00008000
#define PHSDIR_OFFSET 14
#define PHSDIR_MASK 0x00004000
#define SWFSYNC_OFFSET 6
#define SWFSYNC_MASK 0x00000040
#define SYNCOSEL_OFFSET 4
#define SYNCOSEL_MASK 0x00000030
#define PRDLD_OFFSET 3
#define PRDLD_MASK 0x00000008
#define PHSEN_OFFSET 2
#define PHSEN_MASK 0x00000004
#define CNT_MODE_OFFSET 0
#define CNT_MODE_MASK 0x00000003

//-----------------------------------
#define CFG_TBSTS_ADDR 0x0004
#define CNT_VAL_LAT_OFFSET 8
#define CNT_VAL_LAT_MASK 0xFFFFFF00
#define CNT_MAX_ST_OFFSET 2
#define CNT_MAX_ST_MASK 0x00000004
#define PWM_SYNC_ST_OFFSET 1
#define PWM_SYNC_ST_MASK 0x00000002
#define CNT_DIR_OFFSET 0
#define CNT_DIR_MASK 0x00000001

//-----------------------------------
#define CFG_TBST_CLR_ADDR 0x0008
#define CNT_MAX_CLR_OFFSET 1
#define CNT_MAX_CLR_MASK 0x00000002
#define SYNC_ST_CLR_OFFSET 0
#define SYNC_ST_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_TBPHS_ADDR 0x000C
#define TBPHS_OFFSET 0
#define TBPHS_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_TBCNT_ADDR 0x0010
#define TB_CNT_OFFSET 0
#define TB_CNT_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_TBPRD_ADDR 0x0014
#define TBPRD_OFFSET 0
#define TBPRD_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_CMPCTL_ADDR 0x001c
#define SHDB_FUL_OFFSET 9
#define SHDB_FUL_MASK 0x00000200
#define SHDA_FUL_OFFSET 8
#define SHDA_FUL_MASK 0x00000100
#define SHDB_MOD_OFFSET 6
#define SHDB_MOD_MASK 0x00000040
#define SHDA_MOD_OFFSET 4
#define SHDA_MOD_MASK 0x00000010
#define LDB_MOD_OFFSET 2
#define LDB_MOD_MASK 0x0000000C
#define LDA_MOD_OFFSET 0
#define LDA_MOD_MASK 0x00000003

//-----------------------------------
#define CFG_CMPA_ADDR 0x0024
#define CMPA_OFFSET 0
#define CMPA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_CMPB_ADDR 0x0028
#define CMPB_OFFSET 0
#define CMPB_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_AQCTLA_ADDR 0x002C
#define ACTA_CNTB_DWN_OFFSET 10
#define ACTA_CNTB_DWN_MASK 0x00000C00
#define ACTA_CNTB_UP_OFFSET 8
#define ACTA_CNTB_UP_MASK 0x00000300
#define ACTA_CNTA_DWN_OFFSET 6
#define ACTA_CNTA_DWN_MASK 0x000000C0
#define ACTA_CNTA_UP_OFFSET 4
#define ACTA_CNTA_UP_MASK 0x00000030
#define ACTA_CNT_PRD_OFFSET 2
#define ACTA_CNT_PRD_MASK 0x0000000C
#define ACTA_CNT_ZERO_OFFSET 0
#define ACTA_CNT_ZERO_MASK 0x00000003

//-----------------------------------
#define CFG_AQCTLB_ADDR 0x0030
#define ACTB_CNTB_DWN_OFFSET 10
#define ACTB_CNTB_DWN_MASK 0x00000C00
#define ACTB_CNTB_UP_OFFSET 8
#define ACTB_CNTB_UP_MASK 0x00000300
#define ACTB_CNTA_DWN_OFFSET 6
#define ACTB_CNTA_DWN_MASK 0x000000C0
#define ACTB_CNTA_UP_OFFSET 4
#define ACTB_CNTA_UP_MASK 0x00000030
#define ACTB_CNT_PRD_OFFSET 2
#define ACTB_CNT_PRD_MASK 0x0000000C
#define ACTB_CNT_ZERO_OFFSET 0
#define ACTB_CNT_ZERO_MASK 0x00000003

//-----------------------------------
#define CFG_AQSFRC_ADDR 0x0034
#define RLDCSF_OFFSET 6
#define RLDCSF_MASK 0x000000C0
#define OTSFB_OFFSET 5
#define OTSFB_MASK 0x00000020
#define ACTSFB_OFFSET 3
#define ACTSFB_MASK 0x00000018
#define OTSFA_OFFSET 2
#define OTSFA_MASK 0x00000004
#define ACTSFA_OFFSET 0
#define ACTSFA_MASK 0x00000003

//-----------------------------------
#define CFG_AQCSFRC_ADDR 0x0038
#define CSFB_OFFSET 2
#define CSFB_MASK 0x0000000C
#define CSFA_OFFSET 0
#define CSFA_MASK 0x00000003

//-----------------------------------
#define CFG_DBCTL_ADDR 0x003C
#define IN_MODE_OFFSET 4
#define IN_MODE_MASK 0x00000030
#define POLSEL_OFFSET 2
#define POLSEL_MASK 0x0000000C
#define OUT_MODE_OFFSET 0
#define OUT_MODE_MASK 0x00000003

//-----------------------------------
#define CFG_DBRED_ADDR 0x0040
#define R_DLY_VAL_OFFSET 0
#define R_DLY_VAL_MASK 0x000003FF

//-----------------------------------
#define CFG_DBFED_ADDR 0x0044
#define F_DLY_VAL_OFFSET 0
#define F_DLY_VAL_MASK 0x000003FF

//-----------------------------------
#define CFG_TZSEL_ADDR 0x0048
#define DCBEVT1_OSHT_OFFSET 15
#define DCBEVT1_OSHT_MASK 0x00008000
#define DCAEVT1_OSHT_OFFSET 14
#define DCAEVT1_OSHT_MASK 0x00004000
#define TZ6_OSHT_OFFSET 13
#define TZ6_OSHT_MASK 0x00002000
#define TZ5_OSHT_OFFSET 12
#define TZ5_OSHT_MASK 0x00001000
#define TZ4_OSHT_OFFSET 11
#define TZ4_OSHT_MASK 0x00000800
#define TZ3_OSHT_OFFSET 10
#define TZ3_OSHT_MASK 0x00000400
#define TZ2_OSHT_OFFSET 9
#define TZ2_OSHT_MASK 0x00000200
#define TZ1_OSHT_OFFSET 8
#define TZ1_OSHT_MASK 0x00000100
#define DCBEVT2_CBC_OFFSET 7
#define DCBEVT2_CBC_MASK 0x00000080
#define DCAEVT2_CBC_OFFSET 6
#define DCAEVT2_CBC_MASK 0x00000040
#define TZ6_CBC_OFFSET 5
#define TZ6_CBC_MASK 0x00000020
#define TZ5_CBC_OFFSET 4
#define TZ5_CBC_MASK 0x00000010
#define TZ4_CBC_OFFSET 3
#define TZ4_CBC_MASK 0x00000008
#define TZ3_CBC_OFFSET 2
#define TZ3_CBC_MASK 0x00000004
#define TZ2_CBC_OFFSET 1
#define TZ2_CBC_MASK 0x00000002
#define TZ1_CBC_OFFSET 0
#define TZ1_CBC_MASK 0x00000001

//-----------------------------------
#define CFG_TZDCSEL_ADDR 0x004C
#define DCBEVT2_SEL_OFFSET 9
#define DCBEVT2_SEL_MASK 0x00000E00
#define DCBEVT1_SEL_OFFSET 6
#define DCBEVT1_SEL_MASK 0x000001C0
#define DCAEVT2_SEL_OFFSET 3
#define DCAEVT2_SEL_MASK 0x00000038
#define DCAEVT1_SEL_OFFSET 0
#define DCAEVT1_SEL_MASK 0x00000007

//-----------------------------------
#define CFG_TZCTL_ADDR 0x0050
#define DCBEVT2_ACTB_OFFSET 10
#define DCBEVT2_ACTB_MASK 0x00000C00
#define DCBEVT1_ACTB_OFFSET 8
#define DCBEVT1_ACTB_MASK 0x00000300
#define DCAEVT2_ACTA_OFFSET 6
#define DCAEVT2_ACTA_MASK 0x000000C0
#define DCAEVT1_ACTA_OFFSET 4
#define DCAEVT1_ACTA_MASK 0x00000030
#define TZ_ACTB_OFFSET 2
#define TZ_ACTB_MASK 0x0000000C
#define TZ_ACTA_OFFSET 0
#define TZ_ACTA_MASK 0x00000003

//-----------------------------------
#define CFG_ETSEL_ADDR 0x0054
#define SOCB_EN_OFFSET 15
#define SOCB_EN_MASK 0x00008000
#define SOCB_SEL_OFFSET 12
#define SOCB_SEL_MASK 0x00007000
#define SOCA_EN_OFFSET 11
#define SOCA_EN_MASK 0x00000800
#define SOCA_SEL_OFFSET 8
#define SOCA_SEL_MASK 0x00000700
#define INNER_INT_SEL_OFFSET 0
#define INNER_INT_SEL_MASK 0x00000007

//-----------------------------------
#define CFG_ETPS_ADDR 0x0058
#define SOCB_CNT_OFFSET 28
#define SOCB_CNT_MASK 0xF0000000
#define SOCB_PRD_OFFSET 24
#define SOCB_PRD_MASK 0x0F000000
#define SOCA_CNT_OFFSET 20
#define SOCA_CNT_MASK 0x00F00000
#define SOCA_PRD_OFFSET 16
#define SOCA_PRD_MASK 0x000F0000
#define INT_CNT_OFFSET 8
#define INT_CNT_MASK 0x0000FF00
#define INT_PRD_OFFSET 0
#define INT_PRD_MASK 0x000000FF

//-----------------------------------
#define CFG_PWMINT_RAW_ADDR 0x005C
#define DCBEVT2_INT_RAW_OFFSET 14
#define DCBEVT2_INT_RAW_MASK 0x00004000
#define DCBEVT1_INT_RAW_OFFSET 13
#define DCBEVT1_INT_RAW_MASK 0x00002000
#define DCAEVT2_INT_RAW_OFFSET 12
#define DCAEVT2_INT_RAW_MASK 0x00001000
#define DCAEVT1_INT_RAW_OFFSET 11
#define DCAEVT1_INT_RAW_MASK 0x00000800
#define OSHT_INT_RAW_OFFSET 10
#define OSHT_INT_RAW_MASK 0x00000400
#define CBC_INT_RAW_OFFSET 9
#define CBC_INT_RAW_MASK 0x00000200
#define SOCB_INT_RAW_OFFSET 2
#define SOCB_INT_RAW_MASK 0x00000004
#define SOCA_INT_RAW_OFFSET 1
#define SOCA_INT_RAW_MASK 0x00000002
#define INNER_INT_RAW_OFFSET 0
#define INNER_INT_RAW_MASK 0x00000001

//-----------------------------------
#define CFG_PWMINT_ST_ADDR 0x0060
#define DCBEVT2_INT_ST_OFFSET 14
#define DCBEVT2_INT_ST_MASK 0x00004000
#define DCBEVT1_INT_ST_OFFSET 13
#define DCBEVT1_INT_ST_MASK 0x00002000
#define DCAEVT2_INT_ST_OFFSET 12
#define DCAEVT2_INT_ST_MASK 0x00001000
#define DCAEVT1_INT_ST_OFFSET 11
#define DCAEVT1_INT_ST_MASK 0x00000800
#define OSHT_INT_ST_OFFSET 10
#define OSHT_INT_ST_MASK 0x00000400
#define CBC_INT_ST_OFFSET 9
#define CBC_INT_ST_MASK 0x00000200
#define SOCB_INT_ST_OFFSET 2
#define SOCB_INT_ST_MASK 0x00000004
#define SOCA_INT_ST_OFFSET 1
#define SOCA_INT_ST_MASK 0x00000002
#define INNER_INT_ST_OFFSET 0
#define INNER_INT_ST_MASK 0x00000001

//-----------------------------------
#define CFG_PWMINT_ENA_ADDR 0x0064
#define DCBEVT2_INT_ENA_OFFSET 14
#define DCBEVT2_INT_ENA_MASK 0x00004000
#define DCBEVT1_INT_ENA_OFFSET 13
#define DCBEVT1_INT_ENA_MASK 0x00002000
#define DCAEVT2_INT_ENA_OFFSET 12
#define DCAEVT2_INT_ENA_MASK 0x00001000
#define DCAEVT1_INT_ENA_OFFSET 11
#define DCAEVT1_INT_ENA_MASK 0x00000800
#define OSHT_INT_ENA_OFFSET 10
#define OSHT_INT_ENA_MASK 0x00000400
#define CBC_INT_ENA_OFFSET 9
#define CBC_INT_ENA_MASK 0x00000200
#define SOCB_INT_ENA_OFFSET 2
#define SOCB_INT_ENA_MASK 0x00000004
#define SOCA_INT_ENA_OFFSET 1
#define SOCA_INT_ENA_MASK 0x00000002
#define INNER_INT_ENA_OFFSET 0
#define INNER_INT_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_PWMINT_CLR_ADDR 0x0068
#define DCBEVT2_INT_CLR_OFFSET 14
#define DCBEVT2_INT_CLR_MASK 0x00004000
#define DCBEVT1_INT_CLR_OFFSET 13
#define DCBEVT1_INT_CLR_MASK 0x00002000
#define DCAEVT2_INT_CLR_OFFSET 12
#define DCAEVT2_INT_CLR_MASK 0x00001000
#define DCAEVT1_INT_CLR_OFFSET 11
#define DCAEVT1_INT_CLR_MASK 0x00000800
#define OSHT_INT_CLR_OFFSET 10
#define OSHT_INT_CLR_MASK 0x00000400
#define CBC_INT_CLR_OFFSET 9
#define CBC_INT_CLR_MASK 0x00000200
#define SOCB_INT_CLR_OFFSET 2
#define SOCB_INT_CLR_MASK 0x00000004
#define SOCA_INT_CLR_OFFSET 1
#define SOCA_INT_CLR_MASK 0x00000002
#define INNER_INT_CLR_OFFSET 0
#define INNER_INT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_EVTFRC_ADDR 0x006C
#define DCBEVT2_TZFRC_OFFSET 14
#define DCBEVT2_TZFRC_MASK 0x00004000
#define DCBEVT1_TZFRC_OFFSET 13
#define DCBEVT1_TZFRC_MASK 0x00002000
#define DCAEVT2_TZFRC_OFFSET 12
#define DCAEVT2_TZFRC_MASK 0x00001000
#define DCAEVT1_TZFRC_OFFSET 11
#define DCAEVT1_TZFRC_MASK 0x00000800
#define OSHT_FRC_OFFSET 10
#define OSHT_FRC_MASK 0x00000400
#define CBC_FRC_OFFSET 9
#define CBC_FRC_MASK 0x00000200
#define SOCB_FRC_OFFSET 2
#define SOCB_FRC_MASK 0x00000004
#define SOCA_FRC_OFFSET 1
#define SOCA_FRC_MASK 0x00000002
#define INNER_INT_FRC_OFFSET 0
#define INNER_INT_FRC_MASK 0x00000001

//-----------------------------------
#define CFG_PCCTL_ADDR 0x0078
#define CHP_DUTY_OFFSET 8
#define CHP_DUTY_MASK 0x00000700
#define CHP_FREQ_OFFSET 5
#define CHP_FREQ_MASK 0x000000E0
#define OSHT_WTH_OFFSET 1
#define OSHT_WTH_MASK 0x0000001E
#define CHP_EN_OFFSET 0
#define CHP_EN_MASK 0x00000001

//-----------------------------------
#define CFG_DCTRIPSEL_ADDR 0x009C
#define DCBL_CMP_SEL_OFFSET 12
#define DCBL_CMP_SEL_MASK 0x0000F000
#define DCBH_CMP_SEL_OFFSET 8
#define DCBH_CMP_SEL_MASK 0x00000F00
#define DCAL_CMP_SEL_OFFSET 4
#define DCAL_CMP_SEL_MASK 0x000000F0
#define DCAH_CMP_SEL_OFFSET 0
#define DCAH_CMP_SEL_MASK 0x0000000F

//-----------------------------------
#define CFG_DCACTL_ADDR 0x0100
#define EVT2_FRCSYNC_SEL_A_OFFSET 9
#define EVT2_FRCSYNC_SEL_A_MASK 0x00000200
#define EVT2_SRC_SEL_A_OFFSET 8
#define EVT2_SRC_SEL_A_MASK 0x00000100
#define EVT1_SYNC_EN_A_OFFSET 3
#define EVT1_SYNC_EN_A_MASK 0x00000008
#define EVT1_SOC_EN_A_OFFSET 2
#define EVT1_SOC_EN_A_MASK 0x00000004
#define EVT1_FRCSYNC_SEL_A_OFFSET 1
#define EVT1_FRCSYNC_SEL_A_MASK 0x00000002
#define EVT1_SRC_SEL_A_OFFSET 0
#define EVT1_SRC_SEL_A_MASK 0x00000001

//-----------------------------------
#define CFG_DCBCTL_ADDR 0x0104
#define EVT2_FRCSYNC_SEL_B_OFFSET 9
#define EVT2_FRCSYNC_SEL_B_MASK 0x00000200
#define EVT2_SRC_SEL_B_OFFSET 8
#define EVT2_SRC_SEL_B_MASK 0x00000100
#define EVT1_SYNC_EN_B_OFFSET 3
#define EVT1_SYNC_EN_B_MASK 0x00000008
#define EVT1_SOC_EN_B_OFFSET 2
#define EVT1_SOC_EN_B_MASK 0x00000004
#define EVT1_FRCSYNC_SEL_B_OFFSET 1
#define EVT1_FRCSYNC_SEL_B_MASK 0x00000002
#define EVT1_SRC_SEL_B_OFFSET 0
#define EVT1_SRC_SEL_B_MASK 0x00000001

//-----------------------------------
#define CFG_DCFCTL_ADDR 0x0108
#define PULS_SEL_OFFSET 4
#define PULS_SEL_MASK 0x00000030
#define BLANK_INV_OFFSET 3
#define BLANK_INV_MASK 0x00000008
#define BLANK_EN_OFFSET 2
#define BLANK_EN_MASK 0x00000004
#define FIR_SRC_SEL_OFFSET 0
#define FIR_SRC_SEL_MASK 0x00000003

//-----------------------------------
#define CFG_DCCAPCTL_ADDR 0x010C
#define CAP_SHDW_MOD_OFFSET 1
#define CAP_SHDW_MOD_MASK 0x00000002
#define CAP_EN_OFFSET 0
#define CAP_EN_MASK 0x00000001

//-----------------------------------
#define CFG_DCFOFFSET_ADDR 0x0110
#define BLANK_OFFSET_OFFSET 0
#define BLANK_OFFSET_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DCFOFFSETCNT_ADDR 0x0114
#define OFFSET_CNT_OFFSET 0
#define OFFSET_CNT_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DCFWINDOW_ADDR 0x0118
#define BLANK_WINDOW_WIDTH_OFFSET 0
#define BLANK_WINDOW_WIDTH_MASK 0x000000FF

//-----------------------------------
#define CFG_DCFWINDOWCNT_ADDR 0x011C
#define WINDOW_CNT_OFFSET 0
#define WINDOW_CNT_MASK 0x000000FF

//-----------------------------------
#define CFG_DCCAP_ADDR 0x0120
#define CAP_TBCNT_OFFSET 0
#define CAP_TBCNT_MASK 0x00FFFFFF

//HW module read/write macro
#define PWM_NEW0_READ_REG(addr) SOC_READ_REG(PWM_NEW0_BASEADDR + addr)
#define PWM_NEW0_WRITE_REG(addr,value) SOC_WRITE_REG(PWM_NEW0_BASEADDR + addr,value)
#define PWM_NEW1_READ_REG(addr) SOC_READ_REG(PWM_NEW1_BASEADDR + addr)
#define PWM_NEW1_WRITE_REG(addr,value) SOC_WRITE_REG(PWM_NEW1_BASEADDR + addr,value)
#define PWM_NEW2_READ_REG(addr) SOC_READ_REG(PWM_NEW2_BASEADDR + addr)
#define PWM_NEW2_WRITE_REG(addr,value) SOC_WRITE_REG(PWM_NEW2_BASEADDR + addr,value)
#define PWM_NEW3_READ_REG(addr) SOC_READ_REG(PWM_NEW3_BASEADDR + addr)
#define PWM_NEW3_WRITE_REG(addr,value) SOC_WRITE_REG(PWM_NEW3_BASEADDR + addr,value)
#define PWM_NEW4_READ_REG(addr) SOC_READ_REG(PWM_NEW4_BASEADDR + addr)
#define PWM_NEW4_WRITE_REG(addr,value) SOC_WRITE_REG(PWM_NEW4_BASEADDR + addr,value)
#define PWM_NEW5_READ_REG(addr) SOC_READ_REG(PWM_NEW5_BASEADDR + addr)
#define PWM_NEW5_WRITE_REG(addr,value) SOC_WRITE_REG(PWM_NEW5_BASEADDR + addr,value)