kunlun/inc/hw/reg/riscv3/2/soc/macro/afft_reg.h

//-----------------------------------
#define CFG_AUDIO_FFT_VER_ADDR 0x0000
#define SW_AFFT_VERSION_OFFSET 0
#define SW_AFFT_VERSION_MASK 0x0000FFFF

//-----------------------------------
#define CFG_AFFT_CMD_ADDR 0x0004
#define SW_FFT_EN_OFFSET 4
#define SW_FFT_EN_MASK 0x00000010
#define SW_FFT_INIT_DONE_OFFSET 3
#define SW_FFT_INIT_DONE_MASK 0x00000008
#define SW_FFT_SRST_OFFSET 2
#define SW_FFT_SRST_MASK 0x00000004
#define SW_FFT_DONE_OFFSET 1
#define SW_FFT_DONE_MASK 0x00000002
#define SW_TRIG_IN_OFFSET 0
#define SW_TRIG_IN_MASK 0x00000001

//-----------------------------------
#define CFG_AFFT_CFG_ADDR 0x0008
#define SW_FFT_CORE_ST_OFFSET 29
#define SW_FFT_CORE_ST_MASK 0xE0000000
#define SW_FFT_CTRL_ST_OFFSET 26
#define SW_FFT_CTRL_ST_MASK 0x1C000000
#define SW_FFT_WIN_SEL_OFFSET 24
#define SW_FFT_WIN_SEL_MASK 0x03000000
#define SW_INVERT_IFFT_DATA_N_OFFSET 18
#define SW_INVERT_IFFT_DATA_N_MASK 0x00040000
#define SW_DISABLE_SQRT_OFFSET 17
#define SW_DISABLE_SQRT_MASK 0x00020000
#define SW_INIT_ALL_MEM_OFFSET 16
#define SW_INIT_ALL_MEM_MASK 0x00010000
#define SW_AHB_BYTES_OFFSET 13
#define SW_AHB_BYTES_MASK 0x0000E000
#define SW_IS_SIGNED_EXT_OFFSET 12
#define SW_IS_SIGNED_EXT_MASK 0x00001000
#define SW_CLK_FORCE_ON_OFFSET 8
#define SW_CLK_FORCE_ON_MASK 0x00000100
#define SW_DATA_MODE_OFFSET 5
#define SW_DATA_MODE_MASK 0x000000E0
#define SW_IS_COMPLEX_OFFSET 4
#define SW_IS_COMPLEX_MASK 0x00000010
#define SW_IS_FFT_OFFSET 3
#define SW_IS_FFT_MASK 0x00000008
#define SW_FFT_SIZE_OFFSET 0
#define SW_FFT_SIZE_MASK 0x00000007

//-----------------------------------
#define CFG_AFFT_SHIFT_ADDR 0x000C
#define SW_IN_LSH_BIT_SEL_OFFSET 13
#define SW_IN_LSH_BIT_SEL_MASK 0x00006000
#define SW_OUT_RSH_BIT_SEL_OFFSET 10
#define SW_OUT_RSH_BIT_SEL_MASK 0x00001C00
#define SW_FFT_STAGE4_SHIFT_OFFSET 8
#define SW_FFT_STAGE4_SHIFT_MASK 0x00000300
#define SW_FFT_STAGE3_SHIFT_OFFSET 6
#define SW_FFT_STAGE3_SHIFT_MASK 0x000000C0
#define SW_FFT_STAGE2_SHIFT_OFFSET 4
#define SW_FFT_STAGE2_SHIFT_MASK 0x00000030
#define SW_FFT_STAGE1_SHIFT_OFFSET 2
#define SW_FFT_STAGE1_SHIFT_MASK 0x0000000C
#define SW_FFT_STAGE0_SHIFT_OFFSET 0
#define SW_FFT_STAGE0_SHIFT_MASK 0x00000003

//-----------------------------------
#define CFG_AFFT_FLT_ADDR 0x0010
#define SW_I2FLT_ST_OFFSET 24
#define SW_I2FLT_ST_MASK 0xFF000000
#define SW_FLT2I_ST_OFFSET 16
#define SW_FLT2I_ST_MASK 0x00FF0000
#define SW_IGNORE_FLT2I_ST_OFFSET 8
#define SW_IGNORE_FLT2I_ST_MASK 0x00000100
#define SW_FLT_ST_CLR_OFFSET 4
#define SW_FLT_ST_CLR_MASK 0x00000010
#define SW_FLT_RND_SEL_OFFSET 0
#define SW_FLT_RND_SEL_MASK 0x00000007

//-----------------------------------
#define CFG_AFFT_FLT_EXP_ADDR 0x0014
#define SW_FLTOUT_EXP_BIAS_OFFSET 18
#define SW_FLTOUT_EXP_BIAS_MASK 0x03FC0000
#define SW_FLT_EXP_BIAS_OVR_EN_OFFSET 17
#define SW_FLT_EXP_BIAS_OVR_EN_MASK 0x00020000
#define FLT_EXP_BIAS_OFFSET 8
#define FLT_EXP_BIAS_MASK 0x0001FF00
#define SW_FLT_EXP_THRE_OFFSET 0
#define SW_FLT_EXP_THRE_MASK 0x000000FF

//-----------------------------------
#define CFG_AFFT_FLT2I_REG0_ADDR 0x0020
#define SW_FLT2I_REG0_OFFSET 0
#define SW_FLT2I_REG0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_AFFT_FLT2I_REG1_ADDR 0x0024
#define SW_FLT2I_REG1_OFFSET 0
#define SW_FLT2I_REG1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_AFFT_FLT2I_REG2_ADDR 0x0028
#define SW_FLT2I_REG2_OFFSET 0
#define SW_FLT2I_REG2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_AFFT_FLT2I_REG3_ADDR 0x002C
#define SW_FLT2I_REG3_OFFSET 0
#define SW_FLT2I_REG3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_AFFT_AHB_RD_ADDR_ADDR 0x0030
#define SW_AHB_RD_ADDR_OFFSET 0
#define SW_AHB_RD_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_AFFT_AHB_WR_ADDR_ADDR 0x0034
#define SW_AHB_WR_ADDR_OFFSET 0
#define SW_AHB_WR_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_AFFT_INT_RAW_ADDR 0x0040
#define FFT_DONE_INT_RAW_OFFSET 0
#define FFT_DONE_INT_RAW_MASK 0x00000001

//-----------------------------------
#define CFG_AFFT_INT_ST_ADDR 0x0044
#define FFT_DONE_INT_ST_OFFSET 0
#define FFT_DONE_INT_ST_MASK 0x00000001

//-----------------------------------
#define CFG_AFFT_INT_ENA_ADDR 0x0048
#define FFT_DONE_INT_ENA_OFFSET 0
#define FFT_DONE_INT_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_AFFT_INT_CLR_ADDR 0x004C
#define FFT_DONE_INT_CLR_OFFSET 0
#define FFT_DONE_INT_CLR_MASK 0x00000001

//HW module read/write macro
#define AFFT_READ_REG(addr) SOC_READ_REG(AFFT_REG_BASEADDR + addr)
#define AFFT_WRITE_REG(addr,value) SOC_WRITE_REG(AFFT_REG_BASEADDR + addr,value)