kunlun/inc/hw/reg/riscv3/2/soc/macro/dma_reg.h

//-----------------------------------
#define CFG_DMA_REG_VERSION_ADDR 0x0000
#define DMA_REG_VERSION_OFFSET 0
#define DMA_REG_VERSION_MASK 0x000000FF

//-----------------------------------
#define CFG_DMA_SOFT_RESET_CFG_ADDR 0x0004
#define DMA_FIFO_SOFT_RST_OFFSET 2
#define DMA_FIFO_SOFT_RST_MASK 0x00000004
#define DMA_RX_SOFT_RST_OFFSET 1
#define DMA_RX_SOFT_RST_MASK 0x00000002
#define DMA_TX_SOFT_RST_OFFSET 0
#define DMA_TX_SOFT_RST_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_CRC0_CFG0_ADDR 0x0008
#define CRC0_CHN_ID_OFFSET 12
#define CRC0_CHN_ID_MASK 0x000FF000
#define CRC0_MODE_OFFSET 4
#define CRC0_MODE_MASK 0x00000FF0
#define CRC0_OUT_DONE_OFFSET 2
#define CRC0_OUT_DONE_MASK 0x00000004
#define CRC0_INIT_OFFSET 1
#define CRC0_INIT_MASK 0x00000002
#define CRC0_EB_OFFSET 0
#define CRC0_EB_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_CRC0_CFG1_ADDR 0x000C
#define CRC0_OUT_OFFSET 0
#define CRC0_OUT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_CRC0_CFG2_ADDR 0x0010
#define CRC0_POLYNOMIAL_OFFSET 0
#define CRC0_POLYNOMIAL_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_CRC1_CFG0_ADDR 0x0014
#define CRC1_CHN_ID_OFFSET 12
#define CRC1_CHN_ID_MASK 0x000FF000
#define CRC1_MODE_OFFSET 4
#define CRC1_MODE_MASK 0x00000FF0
#define CRC1_OUT_DONE_OFFSET 2
#define CRC1_OUT_DONE_MASK 0x00000004
#define CRC1_INIT_OFFSET 1
#define CRC1_INIT_MASK 0x00000002
#define CRC1_EB_OFFSET 0
#define CRC1_EB_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_CRC1_CFG1_ADDR 0x0018
#define CRC1_OUT_OFFSET 0
#define CRC1_OUT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_CRC1_CFG2_ADDR 0x001C
#define CRC1_POLYNOMIAL_OFFSET 0
#define CRC1_POLYNOMIAL_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_CKSUM0_ADDR 0x0020
#define CKSUM0_OUT_OFFSET 16
#define CKSUM0_OUT_MASK 0xFFFF0000
#define CKSUM0_ID_OFFSET 8
#define CKSUM0_ID_MASK 0x0000FF00
#define CKSUM0_INIT_OFFSET 1
#define CKSUM0_INIT_MASK 0x00000002
#define CKSUM0_EB_OFFSET 0
#define CKSUM0_EB_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_CKSUM1_ADDR 0x0024
#define CKSUM1_OUT_OFFSET 16
#define CKSUM1_OUT_MASK 0xFFFF0000
#define CKSUM1_ID_OFFSET 8
#define CKSUM1_ID_MASK 0x0000FF00
#define CKSUM1_INIT_OFFSET 1
#define CKSUM1_INIT_MASK 0x00000002
#define CKSUM1_EB_OFFSET 0
#define CKSUM1_EB_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_FP_CFG0_ADDR 0x0028
#define DMA_FP_RESET_OFFSET 26
#define DMA_FP_RESET_MASK 0x04000000
#define DMA_FP_SHIFT_OFFSET 20
#define DMA_FP_SHIFT_MASK 0x03F00000
#define DMA_FP_ID_OFFSET 12
#define DMA_FP_ID_MASK 0x000FF000
#define DMA_FP_OP_TYPE_OFFSET 8
#define DMA_FP_OP_TYPE_MASK 0x00000F00
#define DMA_FP_INIT_OFFSET 7
#define DMA_FP_INIT_MASK 0x00000080
#define DMA_FP_RND_OFFSET 4
#define DMA_FP_RND_MASK 0x00000070
#define DMA_FP_EB_OFFSET 3
#define DMA_FP_EB_MASK 0x00000008
#define DMA_FP_MAX_MIN_CTRL_OFFSET 2
#define DMA_FP_MAX_MIN_CTRL_MASK 0x00000004
#define DMA_FP_FAC_CTRL_OFFSET 0
#define DMA_FP_FAC_CTRL_MASK 0x00000003

//-----------------------------------
#define CFG_DMA_FP_CFG1_ADDR 0x002C
#define DMA_FP_FAC_OFFSET 0
#define DMA_FP_FAC_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_FP_ST0_ADDR 0x0030
#define DMA_FP_SUM_OFFSET 0
#define DMA_FP_SUM_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_FP_ST1_ADDR 0x0034
#define DMA_FP_MAX_MIN_OFFSET 0
#define DMA_FP_MAX_MIN_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_FP_CHN_INDEX_ADDR 0x0038
#define DMA_FP_INDEX_OFFSET 0
#define DMA_FP_INDEX_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DMA_DBG_STATUS0_ADDR 0x003C
#define DMA_DBG_STATUS0_OFFSET 0
#define DMA_DBG_STATUS0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_DBG_STATUS1_ADDR 0x0040
#define DMA_DBG_STATUS1_OFFSET 0
#define DMA_DBG_STATUS1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_DBG_STATUS2_ADDR 0x0044
#define DMA_DBG_STATUS2_OFFSET 0
#define DMA_DBG_STATUS2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_DBG_STATUS3_ADDR 0x0048
#define DMA_DBG_STATUS3_OFFSET 0
#define DMA_DBG_STATUS3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_ALL_CHN_INT_SUMMARY0_ADDR 0x004C
#define DMA_ALL_CHN_INT_SUMMARY0_OFFSET 0
#define DMA_ALL_CHN_INT_SUMMARY0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_ALL_CHN_INT_SUMMARY1_ADDR 0x0050
#define DMA_ALL_CHN_INT_SUMMARY1_OFFSET 0
#define DMA_ALL_CHN_INT_SUMMARY1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_ALL_CHN_INT_SUMMARY2_ADDR 0x0054
#define DMA_ALL_CHN_INT_SUMMARY2_OFFSET 0
#define DMA_ALL_CHN_INT_SUMMARY2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_ALL_CHN_INT_SUMMARY3_ADDR 0x0058
#define DMA_ALL_CHN_INT_SUMMARY3_OFFSET 0
#define DMA_ALL_CHN_INT_SUMMARY3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_LINK_NULL_ADDR_ADDR 0x005C
#define DMA_LINK_NULL_ADDR_OFFSET 0
#define DMA_LINK_NULL_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_BUFF_NULL_ADDR_ADDR 0x0060
#define DMA_BUFF_NULL_ADDR_OFFSET 0
#define DMA_BUFF_NULL_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_PROT_REG_CFG_ADDR 0x0064
#define DMA_PROT_REG_PATTERN_OFFSET 0
#define DMA_PROT_REG_PATTERN_MASK 0x0000FFFF

//-----------------------------------
#define CFG_DMA_TKIP_MIC_CTRL_ADDR 0x0068
#define SW_TKIP_MIC_WORD_NUM_OFFSET 16
#define SW_TKIP_MIC_WORD_NUM_MASK 0x3FFF0000
#define SW_TKIP_MIC_CRYPT_SRST_OFFSET 12
#define SW_TKIP_MIC_CRYPT_SRST_MASK 0x00001000
#define SW_TKIP_MIC_ID_OFFSET 4
#define SW_TKIP_MIC_ID_MASK 0x00000FF0
#define SW_RO_TKIP_MIC_DONE_LVL_OFFSET 3
#define SW_RO_TKIP_MIC_DONE_LVL_MASK 0x00000008
#define SW_TKIP_MIC_START_OFFSET 2
#define SW_TKIP_MIC_START_MASK 0x00000004
#define SW_TKIP_MIC_ABORT_OFFSET 1
#define SW_TKIP_MIC_ABORT_MASK 0x00000002
#define SW_TKIP_MIC_ENA_OFFSET 0
#define SW_TKIP_MIC_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_TKIP_MIC_KEY_HIGH_ADDR 0x006C
#define SW_TKIP_MIC_KEY_HIGH_OFFSET 0
#define SW_TKIP_MIC_KEY_HIGH_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_TKIP_MIC_KEY_LOW_ADDR 0x0070
#define SW_TKIP_MIC_KEY_LOW_OFFSET 0
#define SW_TKIP_MIC_KEY_LOW_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_RO_TKIP_MIC_HIGH_ADDR 0x0074
#define SW_RO_TKIP_MIC_HIGH_OFFSET 0
#define SW_RO_TKIP_MIC_HIGH_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_RO_TKIP_MIC_LOW_ADDR 0x0078
#define SW_RO_TKIP_MIC_LOW_OFFSET 0
#define SW_RO_TKIP_MIC_LOW_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_CHN0_CFG0_ADDR 0x1000
#define CH0_DESC_LINK_ADDR_OFFSET 0
#define CH0_DESC_LINK_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_CHN0_CFG1_ADDR 0x1004

//-----------------------------------
#define CFG_DMA_CHN0_CFG2_ADDR 0x1008
#define CH0_DESC_OWNER_EB_IGNORE_OFFSET 30
#define CH0_DESC_OWNER_EB_IGNORE_MASK 0x40000000
#define CH0_DMA_INT_EB_OFFSET 26
#define CH0_DMA_INT_EB_MASK 0x3C000000
#define CH0_TX_ADDR_INC_MODE_OFFSET 25
#define CH0_TX_ADDR_INC_MODE_MASK 0x02000000
#define CH0_RX_ADDR_INC_MODE_OFFSET 24
#define CH0_RX_ADDR_INC_MODE_MASK 0x01000000
#define CH0_TX_DATA_WIDTH_OFFSET 22
#define CH0_TX_DATA_WIDTH_MASK 0x00C00000
#define CH0_RX_DATA_WIDTH_OFFSET 20
#define CH0_RX_DATA_WIDTH_MASK 0x00300000
#define CH0_TX_BIT_ORDER_SEL_OFFSET 19
#define CH0_TX_BIT_ORDER_SEL_MASK 0x00080000
#define CH0_RX_BIT_ORDER_SEL_OFFSET 18
#define CH0_RX_BIT_ORDER_SEL_MASK 0x00040000
#define CH0_TX_WORD_ORDER_SEL_OFFSET 17
#define CH0_TX_WORD_ORDER_SEL_MASK 0x00020000
#define CH0_RX_WORD_ORDER_SEL_OFFSET 16
#define CH0_RX_WORD_ORDER_SEL_MASK 0x00010000
#define CH0_TX_BURST_LEN_OFFSET 12
#define CH0_TX_BURST_LEN_MASK 0x0000F000
#define CH0_RX_BURST_LEN_OFFSET 8
#define CH0_RX_BURST_LEN_MASK 0x00000F00
#define CH0_SOFT_RESET_OFFSET 6
#define CH0_SOFT_RESET_MASK 0x00000040
#define CH0_TRANS_TYPE_OFFSET 4
#define CH0_TRANS_TYPE_MASK 0x00000030
#define CH0_START_SEL_OFFSET 3
#define CH0_START_SEL_MASK 0x00000008
#define CH0_START_OFFSET 2
#define CH0_START_MASK 0x00000004
#define CH0_SUSPEND_OFFSET 0
#define CH0_SUSPEND_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_CHN0_CFG3_ADDR 0x100C
#define CH0_DBG_BUS_SEL_OFFSET 16
#define CH0_DBG_BUS_SEL_MASK 0x000F0000
#define CH0_PRIORITY_OFFSET 14
#define CH0_PRIORITY_MASK 0x0000C000
#define CH0_TX_TRANS_STEP_OFFSET 11
#define CH0_TX_TRANS_STEP_MASK 0x00003800
#define CH0_RX_TRANS_STEP_OFFSET 8
#define CH0_RX_TRANS_STEP_MASK 0x00000700
#define CH0_HW_REQ_SYNC_SEL_OFFSET 7
#define CH0_HW_REQ_SYNC_SEL_MASK 0x00000080
#define CH0_HW_REQ_INDEX_OFFSET 0
#define CH0_HW_REQ_INDEX_MASK 0x0000007F

//-----------------------------------
#define CFG_DMA_CHN0_CFG4_ADDR 0x1010
#define CH0_STOP_OFFSET 16
#define CH0_STOP_MASK 0x00010000
#define CH0_SUSPEND_STATUS_OFFSET 15
#define CH0_SUSPEND_STATUS_MASK 0x00008000
#define CH0_TX_BURST_ALIGN_EN_OFFSET 13
#define CH0_TX_BURST_ALIGN_EN_MASK 0x00002000
#define CH0_RX_BURST_ALIGN_EN_OFFSET 12
#define CH0_RX_BURST_ALIGN_EN_MASK 0x00001000
#define CH0_TX_WRAP_BURST_TYPE_OFFSET 4
#define CH0_TX_WRAP_BURST_TYPE_MASK 0x000000F0
#define CH0_RX_WRAP_BURST_TYPE_OFFSET 0
#define CH0_RX_WRAP_BURST_TYPE_MASK 0x0000000F

//-----------------------------------
#define CFG_DMA_CHN0_CFG5_ADDR 0x1014
#define CH0_DESC_RELOAD_LINK_ADDR_OFFSET 0
#define CH0_DESC_RELOAD_LINK_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_CHN0_CFG6_ADDR 0x1018

//-----------------------------------
#define CFG_DMA_CHN0_CFG7_ADDR 0x101C
#define CH0_DBG_BUS_OFFSET 0
#define CH0_DBG_BUS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DMA_CHN0_INT_RAW_ADDR 0x2000
#define CH0_CURR_DECR_DME_INT_RAW_OFFSET 7
#define CH0_CURR_DECR_DME_INT_RAW_MASK 0x00000080
#define CH0_STOP_INT_RAW_OFFSET 6
#define CH0_STOP_INT_RAW_MASK 0x00000040
#define CH0_SUSPEND_INT_RAW_OFFSET 5
#define CH0_SUSPEND_INT_RAW_MASK 0x00000020
#define CH0_BUFF_ADDR_NULL_INT_RAW_OFFSET 4
#define CH0_BUFF_ADDR_NULL_INT_RAW_MASK 0x00000010
#define CH0_HW_ACK_INT_RAW_OFFSET 3
#define CH0_HW_ACK_INT_RAW_MASK 0x00000008
#define CH0_CURR_DECR_INT_RAW_OFFSET 2
#define CH0_CURR_DECR_INT_RAW_MASK 0x00000004
#define CH0_ALL_DECR_INT_RAW_OFFSET 1
#define CH0_ALL_DECR_INT_RAW_MASK 0x00000002
#define CH0_DECR_IS_NOT_HW_INT_RAW_OFFSET 0
#define CH0_DECR_IS_NOT_HW_INT_RAW_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_CHN0_INT_ST_ADDR 0x2004
#define CH0_CURR_DECR_DME_INT_ST_OFFSET 7
#define CH0_CURR_DECR_DME_INT_ST_MASK 0x00000080
#define CH0_STOP_INT_ST_OFFSET 6
#define CH0_STOP_INT_ST_MASK 0x00000040
#define CH0_SUSPEND_INT_ST_OFFSET 5
#define CH0_SUSPEND_INT_ST_MASK 0x00000020
#define CH0_BUFF_ADDR_NULL_INT_ST_OFFSET 4
#define CH0_BUFF_ADDR_NULL_INT_ST_MASK 0x00000010
#define CH0_HW_ACK_INT_ST_OFFSET 3
#define CH0_HW_ACK_INT_ST_MASK 0x00000008
#define CH0_CURR_DECR_INT_ST_OFFSET 2
#define CH0_CURR_DECR_INT_ST_MASK 0x00000004
#define CH0_ALL_DECR_INT_ST_OFFSET 1
#define CH0_ALL_DECR_INT_ST_MASK 0x00000002
#define CH0_DECR_IS_NOT_HW_INT_ST_OFFSET 0
#define CH0_DECR_IS_NOT_HW_INT_ST_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_CHN0_INT_ENA_ADDR 0x2008
#define CH0_CURR_DECR_DME_INT_ENA_OFFSET 7
#define CH0_CURR_DECR_DME_INT_ENA_MASK 0x00000080
#define CH0_STOP_INT_ENA_OFFSET 6
#define CH0_STOP_INT_ENA_MASK 0x00000040
#define CH0_SUSPEND_INT_ENA_OFFSET 5
#define CH0_SUSPEND_INT_ENA_MASK 0x00000020
#define CH0_BUFF_ADDR_NULL_INT_ENA_OFFSET 4
#define CH0_BUFF_ADDR_NULL_INT_ENA_MASK 0x00000010
#define CH0_HW_ACK_INT_ENA_OFFSET 3
#define CH0_HW_ACK_INT_ENA_MASK 0x00000008
#define CH0_CURR_DECR_INT_ENA_OFFSET 2
#define CH0_CURR_DECR_INT_ENA_MASK 0x00000004
#define CH0_ALL_DECR_INT_ENA_OFFSET 1
#define CH0_ALL_DECR_INT_ENA_MASK 0x00000002
#define CH0_DECR_IS_NOT_HW_INT_ENA_OFFSET 0
#define CH0_DECR_IS_NOT_HW_INT_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_DMA_CHN0_INT_CLR_ADDR 0x200C
#define CH0_CURR_DECR_DME_INT_CLR_OFFSET 7
#define CH0_CURR_DECR_DME_INT_CLR_MASK 0x00000080
#define CH0_STOP_INT_CLR_OFFSET 6
#define CH0_STOP_INT_CLR_MASK 0x00000040
#define CH0_SUSPEND_INT_CLR_OFFSET 5
#define CH0_SUSPEND_INT_CLR_MASK 0x00000020
#define CH0_BUFF_ADDR_NULL_INT_CLR_OFFSET 4
#define CH0_BUFF_ADDR_NULL_INT_CLR_MASK 0x00000010
#define CH0_HW_ACK_INT_CLR_OFFSET 3
#define CH0_HW_ACK_INT_CLR_MASK 0x00000008
#define CH0_CURR_DECR_INT_CLR_OFFSET 2
#define CH0_CURR_DECR_INT_CLR_MASK 0x00000004
#define CH0_ALL_DECR_INT_CLR_OFFSET 1
#define CH0_ALL_DECR_INT_CLR_MASK 0x00000002
#define CH0_DECR_IS_NOT_HW_INT_CLR_OFFSET 0
#define CH0_DECR_IS_NOT_HW_INT_CLR_MASK 0x00000001

//HW module read/write macro
#define DMA0_READ_REG(addr) SOC_READ_REG(DMA0_BASEADDR + addr)
#define DMA0_WRITE_REG(addr,value) SOC_WRITE_REG(DMA0_BASEADDR + addr,value)

#define DMA1_READ_REG(addr) SOC_READ_REG(DMA1_BASEADDR + addr)
#define DMA1_WRITE_REG(addr,value) SOC_WRITE_REG(DMA1_BASEADDR + addr,value)

#define DMA2_READ_REG(addr) SOC_READ_REG(DMA2_BASEADDR + addr)
#define DMA2_WRITE_REG(addr,value) SOC_WRITE_REG(DMA2_BASEADDR + addr,value)