kunlun/inc/hw/reg/riscv3/2/soc/macro/eq_reg.h

//-----------------------------------
#define CFG_ACC_EQ_VER_ADDR 0x0000
#define SW_EQ_VERSION_OFFSET 0
#define SW_EQ_VERSION_MASK 0x0000FFFF

//-----------------------------------
#define CFG_EQ_CMD_ADDR 0x0004
#define SW_EQ_COEF_DONE_OFFSET 12
#define SW_EQ_COEF_DONE_MASK 0x00001000
#define SW_EQ_COEF_START_OFFSET 8
#define SW_EQ_COEF_START_MASK 0x00000100
#define SW_EQ_DONE_OFFSET 4
#define SW_EQ_DONE_MASK 0x00000010
#define SW_EQ_START_OFFSET 0
#define SW_EQ_START_MASK 0x00000001

//-----------------------------------
#define CFG_EQ_ENA_ADDR 0x0008
#define SW_EQ_CLK_FORCE_ON_OFFSET 16
#define SW_EQ_CLK_FORCE_ON_MASK 0x00010000
#define RO_EQ_STATUS_OFFSET 12
#define RO_EQ_STATUS_MASK 0x00007000
#define SW_EQ_COEF_EN_OFFSET 8
#define SW_EQ_COEF_EN_MASK 0x00000100
#define SW_EQ_SRST_OFFSET 4
#define SW_EQ_SRST_MASK 0x00000010
#define SW_EQ_EN_OFFSET 0
#define SW_EQ_EN_MASK 0x00000001

//-----------------------------------
#define CFG_EQ_SET_ADDR 0x000C
#define SW_EQ_NOISE_MODE_OFFSET 30
#define SW_EQ_NOISE_MODE_MASK 0x40000000
#define SW_EQ_DATA_LEN_OFFSET 20
#define SW_EQ_DATA_LEN_MASK 0x3FF00000
#define SW_EQ_BIG_ENDIAN_OFFSET 19
#define SW_EQ_BIG_ENDIAN_MASK 0x00080000
#define SW_EQ_DATA_MODE_OFFSET 18
#define SW_EQ_DATA_MODE_MASK 0x00040000
#define SW_EQ_START_BAND_OFFSET 12
#define SW_EQ_START_BAND_MASK 0x0003F000
#define SW_EQ_DATA_LOAD_MEM_OFFSET 11
#define SW_EQ_DATA_LOAD_MEM_MASK 0x00000800
#define SW_EQ_FLT_MODE_OFFSET 10
#define SW_EQ_FLT_MODE_MASK 0x00000400
#define SW_EQ_NUM_OFFSET 4
#define SW_EQ_NUM_MASK 0x000003F0
#define SW_EQ_AHB_RW_OFFSET 3
#define SW_EQ_AHB_RW_MASK 0x00000008
#define SW_EQ_AHB_BYTES_OFFSET 0
#define SW_EQ_AHB_BYTES_MASK 0x00000007

//-----------------------------------
#define CFG_EQ_DATA_RD_ADDR_ADDR 0x00010
#define SW_EQ_DATA_RD_ADDR_OFFSET 0
#define SW_EQ_DATA_RD_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EQ_DATA_WR_ADDR_ADDR 0x0014
#define SW_EQ_DATA_WR_ADDR_OFFSET 0
#define SW_EQ_DATA_WR_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EQ_SHIFT_ADDR 0x0018
#define SW_EQ_OUT_RSH_BIT_SEL_OFFSET 4
#define SW_EQ_OUT_RSH_BIT_SEL_MASK 0x000000F0
#define SW_EQ_IN_LSH_BIT_SEL_OFFSET 0
#define SW_EQ_IN_LSH_BIT_SEL_MASK 0x0000000F

//-----------------------------------
#define CFG_EQ_FLT_SET_ADDR 0x001C
#define SW_EQ_I2FLT_ST_OFFSET 24
#define SW_EQ_I2FLT_ST_MASK 0xFF000000
#define SW_EQ_FLT2I_ST_OFFSET 16
#define SW_EQ_FLT2I_ST_MASK 0x00FF0000
#define SW_EQ_FLT_ST_CLR_OFFSET 5
#define SW_EQ_FLT_ST_CLR_MASK 0x00000020
#define SW_EQ_IGNORE_FLT2I_ST_OFFSET 4
#define SW_EQ_IGNORE_FLT2I_ST_MASK 0x00000010
#define SW_EQ_FLT_RND_SEL_OFFSET 0
#define SW_EQ_FLT_RND_SEL_MASK 0x00000007

//-----------------------------------
#define CFG_EQ_FLT_EXP_SET_ADDR 0x0020
#define SW_EQ_FLTOUT_EXP_BIAS_OFFSET 18
#define SW_EQ_FLTOUT_EXP_BIAS_MASK 0x03FC0000
#define SW_EQ_EXP_BIAS_OVR_EN_OFFSET 17
#define SW_EQ_EXP_BIAS_OVR_EN_MASK 0x00020000
#define EQ_FLT_EXP_BIAS_OFFSET 8
#define EQ_FLT_EXP_BIAS_MASK 0x0001FF00
#define SW_EQ_EXP_THRE_OFFSET 0
#define SW_EQ_EXP_THRE_MASK 0x000000FF

//-----------------------------------
#define CFG_EQ_FLT2I_REG0_ADDR 0x0024
#define SW_EQ_FLT2I_REG0_OFFSET 0
#define SW_EQ_FLT2I_REG0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EQ_FLT2I_REG1_ADDR 0x0028
#define SW_EQ_FLT2I_REG1_OFFSET 0
#define SW_EQ_FLT2I_REG1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EQ_FLT2I_REG2_ADDR 0x002C
#define SW_EQ_FLT2I_REG2_OFFSET 0
#define SW_EQ_FLT2I_REG2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EQ_FLT2I_REG3_ADDR 0x0030
#define SW_EQ_FLT2I_REG3_OFFSET 0
#define SW_EQ_FLT2I_REG3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EQ_INT_RAW_ADDR 0x0034
#define EQ_COEF_DONE_INT_RAW_OFFSET 4
#define EQ_COEF_DONE_INT_RAW_MASK 0x00000010
#define EQ_DONE_INT_RAW_OFFSET 0
#define EQ_DONE_INT_RAW_MASK 0x00000001

//-----------------------------------
#define CFG_EQ_INT_ST_ADDR 0x0038
#define EQ_COEF_DONE_INT_ST_OFFSET 4
#define EQ_COEF_DONE_INT_ST_MASK 0x00000010
#define EQ_DONE_INT_ST_OFFSET 0
#define EQ_DONE_INT_ST_MASK 0x00000001

//-----------------------------------
#define CFG_EQ_INT_ENA_ADDR 0x003C
#define EQ_COEF_DONE_INT_ENA_OFFSET 4
#define EQ_COEF_DONE_INT_ENA_MASK 0x00000010
#define EQ_DONE_INT_ENA_OFFSET 0
#define EQ_DONE_INT_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_EQ_INT_CLR_ADDR 0x0040
#define EQ_COEF_DONE_INT_CLR_OFFSET 4
#define EQ_COEF_DONE_INT_CLR_MASK 0x00000010
#define EQ_DONE_INT_CLR_OFFSET 0
#define EQ_DONE_INT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_EQ_COEF_RW_ADDR 0x0044
#define SW_EQ_COEF_RW_OFFSET 0
#define SW_EQ_COEF_RW_MASK 0x00000001

//-----------------------------------
#define CFG_EQ_COEF_RD_ADDR_ADDR 0x0048
#define SW_EQ_COEF_RD_ADDR_OFFSET 0
#define SW_EQ_COEF_RD_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EQ_COEF_WR_ADDR_ADDR 0x004C
#define SW_EQ_COEF_WR_ADDR_OFFSET 0
#define SW_EQ_COEF_WR_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EQ_DATA_CLIP_RATE_ADDR 0x0050
#define SW_EQ_OUT_CLIP_RATE_OFFSET 0
#define SW_EQ_OUT_CLIP_RATE_MASK 0x0000000F

//-----------------------------------
#define CFG_EQ_OUT_CLIP_THRE_ADDR 0x0054
#define SW_EQ_OUT_CLIP_THRES_OFFSET 0
#define SW_EQ_OUT_CLIP_THRES_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EQ_COEF_SWITCH_ADDR 0x0060
#define SW_EQ_SWITCH_DONE_OFFSET 17
#define SW_EQ_SWITCH_DONE_MASK 0x00020000
#define RO_EQ_SWITCH_STATUS_OFFSET 16
#define RO_EQ_SWITCH_STATUS_MASK 0x00010000
#define SW_EQ_DST_NUM_OFFSET 10
#define SW_EQ_DST_NUM_MASK 0x0000FC00
#define SW_EQ_DST_START_BAND_OFFSET 4
#define SW_EQ_DST_START_BAND_MASK 0x000003F0
#define SW_EQ_DST_COEF_LOAD_EN_OFFSET 2
#define SW_EQ_DST_COEF_LOAD_EN_MASK 0x00000004
#define SW_EQ_SRC_COEF_OUT_EN_OFFSET 1
#define SW_EQ_SRC_COEF_OUT_EN_MASK 0x00000002
#define SW_EQ_COEF_SWITCH_EN_OFFSET 0
#define SW_EQ_COEF_SWITCH_EN_MASK 0x00000001

//-----------------------------------
#define CFG_EQ_COEF_SWITCH_CFG_ADDR 0x0064
#define SW_EQ_SWITCH_LEN_SEL_OFFSET 16
#define SW_EQ_SWITCH_LEN_SEL_MASK 0x000F0000
#define SW_EQ_SWITCH_DELAY_OFFSET 0
#define SW_EQ_SWITCH_DELAY_MASK 0x00003FFF

//-----------------------------------
#define CFG_RO_EQ_COEF_SWITCH_ST_ADDR 0x0068
#define RO_EQ_SWITCH_LEN_OFFSET 14
#define RO_EQ_SWITCH_LEN_MASK 0xFFFFC000
#define RO_EQ_SWITCH_DELAY_OFFSET 0
#define RO_EQ_SWITCH_DELAY_MASK 0x00003FFF

//-----------------------------------
#define CFG_EQ_DST_COEF_RD_ADDR_ADDR 0x006C
#define SW_EQ_DST_COEF_RD_ADDR_OFFSET 0
#define SW_EQ_DST_COEF_RD_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EQ_DST_COEF_WR_ADDR_ADDR 0x0070
#define SW_EQ_DST_COEF_WR_ADDR_OFFSET 0
#define SW_EQ_DST_COEF_WR_ADDR_MASK 0xFFFFFFFF

//HW module read/write macro
#define EQ_READ_REG(addr) SOC_READ_REG(EQ_REG_BASEADDR + addr)
#define EQ_WRITE_REG(addr,value) SOC_WRITE_REG(EQ_REG_BASEADDR + addr,value)