78 lines
2.1 KiB
C
78 lines
2.1 KiB
C
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/****************************************************************************
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*
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* Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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*
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* This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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* be copied by any method or incorporated into another program without
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* the express written consent of Aerospace C.Power. This Information or any portion
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* thereof remains the property of Aerospace C.Power. The Information contained herein
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* is believed to be accurate and Aerospace C.Power assumes no responsibility or
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* liability for its use in any way and conveys no license or title under
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* any patent or copyright and makes no representation or warranty that this
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* Information is free from patent or copyright infringement.
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*
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* ****************************************************************************/
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/* os shim includes */
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#include "os_types.h"
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#include "iot_irq.h"
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#include "iot_wdg.h"
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#include "efuse.h"
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#include "iot_system.h"
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#include "sec_glb.h"
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#include "platform.h"
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#include "encoding.h"
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extern void def_trap_entry_1();
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extern void intc_handler(uint32_t cpu);
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extern void trigger_zero_addr_access_detect();
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extern void ahb_core0_enable();
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uintptr_t handle_trap_1(uintptr_t mcause, uintptr_t epc, saved_registers *reg)
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{
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if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT) {
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intc_handler(HAL_INTR_CPU_1);
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}else {
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}
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return epc;
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}
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void _init_1()
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{
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//disable cpu1 branch prediction
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sec_glb_core1_branch_pred_enable(0);
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//disable cpu0, cpu2 instruction master access to dmc cache slave
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sec_glb_mtx_mst_acc(19, 14, 0);
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sec_glb_mtx_mst_acc(19, 16, 0);
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sec_glb_mtx_mst_acc(20, 14, 0);
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sec_glb_mtx_mst_acc(20, 16, 0);
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write_csr(mtvec, &def_trap_entry_1);
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clear_csr(mie, MIP_MEIP);
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clear_csr(mie, MIP_MTIP);
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iot_interrupt_init(HAL_INTR_CPU_1);
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set_csr(mie, MIP_MEIP);
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// Enable interrupts in general.
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set_csr(mstatus, MSTATUS_MIE);
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wdg_deinit(HAL_WDG_CPU_0);
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//wdg_deinit(HAL_WDG_CPU_1);
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wdg_deinit(HAL_WDG_CPU_2);
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wdg_deinit(HAL_WDG_CPU_3);
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wdg_deinit(HAL_WDG_CPU_4);
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}
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void _fini()
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{
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}
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