248 lines
8.4 KiB
C
248 lines
8.4 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#ifndef HW_REG_API_H
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#define HW_REG_API_H
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#include "os_types.h"
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#include "chip_reg_base.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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//#define MSVC_CHECK_REG
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#ifdef __GNUC__
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#define SOC_READ_REG(addr) ((volatile uint32_t)*((volatile uint32_t*)(addr)))
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#define SOC_WRITE_REG(addr, value) (*((volatile uint32_t*)(addr)) = (value))
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#else
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#ifdef MSVC_CHECK_REG
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#define SOC_READ_REG(addr) \
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printf("r 0x%x\n", (addr))?0:0
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#define SOC_WRITE_REG(addr, value) \
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printf("w 0x%x = 0x%x\n", (addr), (value))
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#else
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#define SOC_READ_REG(addr) (0)
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#define SOC_WRITE_REG(addr, value) (void)(0)
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#endif
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#endif
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#define REG_FIELD_GET(name, dword) ((dword & name##_MASK) >> name##_OFFSET)
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#define REG_FIELD_SET(name, dword, value) \
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do { \
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(dword) &= ~name##_MASK; \
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(dword) |= (((value) << name##_OFFSET) & name##_MASK); \
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} while(0)
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#define __REG_N_FIELD__(...) __REG_N_FIELD_(__VA_ARGS__, __FIELD_RSEQ_N())
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#define __REG_N_FIELD_(...) __REG_FIELD_N(__VA_ARGS__)
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#define __REG_FIELD_N(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, \
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_13, _14, _15, _16, _17, _18, _19, _20, _21, _22, _23, \
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_24, _25, _26, _27, _28, _29, _30, _31, _32, _33, _34, \
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_35, _36, _37, _38, _39, _40, _41, _42, _43, _44, _45, \
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_46, _47, _48, _49, _50, _51, _52, _53, _54, _55, _56, \
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_57, _58, _59, _60, _61, _62, _63, _64, N, ...) \
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N
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#define __FIELD_RSEQ_N() \
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32, 32, 31, 31, 30, 30, 29, 29, 28, 28, 27, 27, 26, 26, 25, 25, 24, 24, \
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23, 23, 22, 22, 21, 21, 20, 20, 19, 19, 18, 18, 17, 17, 16, 16, 15, \
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15, 14, 14, 13, 13, 12, 12, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 6, 5, \
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5, 4, 4, 3, 3, 2, 2, 1, 1, 0, 0,
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#define CONCATENATE(arg1, arg2) arg1##arg2
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#define WR_FIELD_1(bitfield, val) __x._b.bitfield = val;
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#define WR_FIELD_2(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_1(__VA_ARGS__); \
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}
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#define WR_FIELD_3(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_2(__VA_ARGS__); \
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}
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#define WR_FIELD_4(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_3(__VA_ARGS__); \
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}
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#define WR_FIELD_5(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_4(__VA_ARGS__); \
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}
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#define WR_FIELD_6(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_5(__VA_ARGS__); \
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}
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#define WR_FIELD_7(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_6(__VA_ARGS__); \
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}
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#define WR_FIELD_8(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_7(__VA_ARGS__); \
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}
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#define WR_FIELD_9(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_8(__VA_ARGS__); \
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}
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#define WR_FIELD_10(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_9(__VA_ARGS__); \
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}
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#define WR_FIELD_11(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_10(__VA_ARGS__); \
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}
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#define WR_FIELD_12(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_11(__VA_ARGS__); \
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}
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#define WR_FIELD_13(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_12(__VA_ARGS__); \
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}
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#define WR_FIELD_14(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_13(__VA_ARGS__); \
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}
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#define WR_FIELD_15(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_14(__VA_ARGS__); \
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}
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#define WR_FIELD_16(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_15(__VA_ARGS__); \
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}
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#define WR_FIELD_17(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_16(__VA_ARGS__); \
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}
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#define WR_FIELD_18(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_17(__VA_ARGS__); \
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}
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#define WR_FIELD_19(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_18(__VA_ARGS__); \
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}
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#define WR_FIELD_20(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_19(__VA_ARGS__); \
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}
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#define WR_FIELD_21(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_20(__VA_ARGS__); \
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}
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#define WR_FIELD_22(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_21(__VA_ARGS__); \
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}
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#define WR_FIELD_23(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_22(__VA_ARGS__); \
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}
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#define WR_FIELD_24(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_23(__VA_ARGS__); \
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}
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#define WR_FIELD_25(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_24(__VA_ARGS__); \
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}
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#define WR_FIELD_26(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_25(__VA_ARGS__); \
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}
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#define WR_FIELD_27(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_26(__VA_ARGS__); \
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}
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#define WR_FIELD_28(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_27(__VA_ARGS__); \
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}
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#define WR_FIELD_29(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_28(__VA_ARGS__); \
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}
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#define WR_FIELD_30(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_29(__VA_ARGS__); \
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}
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#define WR_FIELD_31(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_30(__VA_ARGS__); \
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}
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#define WR_FIELD_32(f, val, ...) \
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{ \
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WR_FIELD_1(f, val); \
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WR_FIELD_31(__VA_ARGS__); \
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}
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#define WR_REG_FIELD_(N, reg, ...) \
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({ \
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typeof(reg) __x = reg; \
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CONCATENATE(WR_FIELD_, N)(__VA_ARGS__); \
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reg = __x; \
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})
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/**
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* WR_REG_FIELD(reg, field1, val1, field2, val2, field3, val3, ...)
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*/
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#define WR_REG_FIELD(reg, ...) \
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WR_REG_FIELD_(__REG_N_FIELD__(reg, __VA_ARGS__), reg, __VA_ARGS__)
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#define RE_REG_FIELD(reg, bitfield) \
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({ \
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typeof(reg) __x = reg; \
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__x._b.bitfield; \
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})
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#ifdef __cplusplus
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}
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#endif
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#endif // !HW_REG_API_H
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