559 lines
17 KiB
C
559 lines
17 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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/* os shim includes */
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#include "iot_config.h"
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#include "os_types.h"
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/* plc public api includes */
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#include "plc_fr.h"
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#include "plc_const.h"
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#include "iot_bitops.h"
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/* mac module internal includes */
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#include "mac.h"
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#include "mac_dsr.h"
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#include "mac_isr.h"
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#include "hw_reg_api.h"
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#include "mac_sys_reg.h"
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/* driver includes */
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#include "iot_irq.h"
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#include "mac_ppm_scan.h"
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/* WAR */
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#include "mac_rx_buf_ring.h"
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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#include "mac_raw_reg.h"
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#include "mac_rawdata_hw.h"
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#include "plc_protocol.h"
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#include "phy_bb.h"
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#include "phy_phase.h"
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#endif
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#include "mac_pdev.h"
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#include "mac_tx_power.h"
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#if WAR_TIMEOUT_TX_ABORT
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#include "mac_tx_hw.h"
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#endif
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#include "mac_int.h"
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#include "mac_cmn_hw.h"
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#include "mac_rf_isr.h"
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#if HW_PLATFORM == HW_PLATFORM_SIMU
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void mac_isr_enable(uint8_t id)
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{
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(void)id;
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}
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void mac_isr_disable(uint8_t id)
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{
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(void)id;
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}
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void mac_isr_start()
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{
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}
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void mac_isr_clear(uint32_t isr_evt)
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{
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(void)isr_evt;
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}
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void mac_isr_stop()
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{
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}
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void mac_isr_init(dsr_notification_func_t callback)
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{
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(void)callback;
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}
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#else /* HW_PLATFORM == HW_PLATFORM_SIMU */
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/* global mac isr context */
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mac_isr_ctx_t g_mac_isr_ctx;
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mac_isr_ctx_t *p_mac_isr_ctx = &g_mac_isr_ctx;
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uint8_t IRAM_ATTR mac_isr_get_dsr_id(uint32_t isr_id)
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{
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uint32_t dsr_id = MAC_DSR_MAX_ID;
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#if 1
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if (isr_id == MAC_ISR_BC_ALERT_ID) {
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dsr_id = MAC_DSR_BC_ALERT_ID;
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} else if (isr_id == MAC_ISR_BC_MISS_ID) {
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dsr_id = MAC_DSR_BC_MISS_ID;
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} else if (isr_id == MAC_ISR_BC_RX_ID) {
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dsr_id = MAC_DSR_BC_RX_ID;
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} else if (isr_id == MAC_ISR_SCH_STOP_ID) {
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dsr_id = MAC_DSR_SCH_STOP_ID;
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} else if (isr_id == MAC_ISR_HWQ_STOP_ID) {
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dsr_id = MAC_DSR_HWQ_STOP_ID;
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} else if (isr_id == MAC_ISR_MPDU_TX_COMP_ID) {
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dsr_id = MAC_DSR_MPDU_TX_COMP_ID;
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} else if (isr_id == MAC_ISR_MPDU_LIST_TX_COMP_ID) {
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dsr_id = MAC_DSR_MPDU_LIST_TX_COMP_ID;
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} else if (isr_id == MAC_ISR_START_DESC_ERR_ID) {
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dsr_id = MAC_DSR_START_DESC_ERR_ID;
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} else if (isr_id == MAC_ISR_END_DESC_ERR_ID) {
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dsr_id = MAC_DSR_END_DESC_ERR_ID;
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} else if (isr_id == MAC_ISR_TX_UNDERRUN_ID) {
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dsr_id = MAC_DSR_TX_UNDERRUN_ID;
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} else if (isr_id == MAC_ISR_MPDU_RX_ID) {
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dsr_id = MAC_DSR_MPDU_RX_ID;
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} else if (isr_id == MAC_ISR_PB_RX_ID) {
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dsr_id = MAC_DSR_PB_RX_ID;
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} else if (isr_id == MAC_ISR_FC_RX_ID) {
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dsr_id = MAC_DSR_FC_RX_ID;
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} else if (isr_id == MAC_ISR_RX_DESC_OVERFLOW_ID) {
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dsr_id = MAC_DSR_RX_DESC_OVERFLOW_ID;
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} else if (isr_id == MAC_ISR_RX_LOAD_OVERFLOW_ID) {
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dsr_id = MAC_DSR_RX_LOAD_OVERFLOW_ID;
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} else if (isr_id == MAC_ISR_RX_LOW_WATERMARK_ID) {
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dsr_id = MAC_DSR_RX_LOW_WATERMARK_ID;
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}
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#else
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switch (isr_id) {
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case MAC_ISR_BC_ALERT_ID:
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dsr_id = MAC_DSR_BC_ALERT_ID;
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break;
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case MAC_ISR_BC_MISS_ID:
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dsr_id = MAC_DSR_BC_MISS_ID;
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break;
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case MAC_ISR_BC_RX_ID:
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dsr_id = MAC_DSR_BC_RX_ID;
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break;
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case MAC_ISR_SCH_STOP_ID:
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dsr_id = MAC_DSR_SCH_STOP_ID;
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break;
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case MAC_ISR_HWQ_STOP_ID:
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dsr_id = MAC_DSR_HWQ_STOP_ID;
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break;
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case MAC_ISR_MPDU_TX_COMP_ID:
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dsr_id = MAC_DSR_MPDU_TX_COMP_ID;
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break;
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case MAC_ISR_MPDU_LIST_TX_COMP_ID:
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dsr_id = MAC_DSR_MPDU_LIST_TX_COMP_ID;
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break;
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case MAC_ISR_START_DESC_ERR_ID:
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dsr_id = MAC_DSR_START_DESC_ERR_ID;
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break;
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case MAC_ISR_END_DESC_ERR_ID:
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dsr_id = MAC_DSR_END_DESC_ERR_ID;
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break;
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case MAC_ISR_TX_UNDERRUN_ID:
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dsr_id = MAC_DSR_TX_UNDERRUN_ID;
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break;
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case MAC_ISR_MPDU_RX_ID:
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dsr_id = MAC_DSR_MPDU_RX_ID;
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break;
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case MAC_ISR_PB_RX_ID:
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dsr_id = MAC_DSR_PB_RX_ID;
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break;
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case MAC_ISR_FC_RX_ID:
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dsr_id = MAC_DSR_FC_RX_ID;
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break;
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case MAC_ISR_RX_DESC_OVERFLOW_ID:
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dsr_id = MAC_DSR_RX_DESC_OVERFLOW_ID;
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break;
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case MAC_ISR_RX_LOAD_OVERFLOW_ID:
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dsr_id = MAC_DSR_RX_LOAD_OVERFLOW_ID;
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break;
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case MAC_ISR_RX_LOW_WATERMARK_ID:
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dsr_id = MAC_DSR_RX_LOW_WATERMARK_ID;
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break;
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default:
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break;
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}
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#endif
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return dsr_id;
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}
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static uint32_t IRAM_ATTR mac_isr_ext1_handler(uint32_t vector,
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iot_addrword_t data)
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{
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uint32_t int_status;
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uint8_t dsr[32], cnt;
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(void)vector;
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(void)data;
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/* read pending interrupt status */
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int_status = RGF_MAC_READ_REG(CFG_MAC_INT_EXT_3_STS_ADDR);
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/* clear pending interrupt status */
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RGF_MAC_WRITE_REG(CFG_MAC_INT_EXT_3_CLR_ADDR, int_status);
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cnt = 0;
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if (int_status & ((1 << MAC_INT_ZC0_CAP_OFFSET)
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| (1 << MAC_INT_ZC1_CAP_OFFSET)
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| (1 << MAC_INT_ZC2_CAP_OFFSET)
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| (1 << MAC_INT_ZC3_CAP_OFFSET)
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| (1 << MAC_INT_ZC4_CAP_OFFSET)
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| (1 << MAC_INT_ZC5_CAP_OFFSET))) {
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dsr[cnt++] = MAC_DSR_ZERO_CROSS_ID;
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}
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//TODO: add code
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#if ENA_TX_RAW_INT
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uint32_t raw_sts = RGF_RAW_READ_REG(CFG_RAW_INT_STATUS_ADDR);
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if (MAC_TX_START_INT_STATUS & raw_sts) {
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uint32_t fc[4];
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/* tx fc need update */
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iot_raw_write_reg(RAW_REG_TYPE_MAC, CFG_TX_FC_NEED_UPD_ADDR, 0x1);
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/* get original tx fc */
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fc[0] = iot_raw_read_reg(RAW_REG_TYPE_MAC, CFG_TX_RAW_FC_0_ADDR);
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fc[1] = iot_raw_read_reg(RAW_REG_TYPE_MAC, CFG_TX_RAW_FC_1_ADDR);
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fc[2] = iot_raw_read_reg(RAW_REG_TYPE_MAC, CFG_TX_RAW_FC_2_ADDR);
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fc[3] = iot_raw_read_reg(RAW_REG_TYPE_MAC, CFG_TX_RAW_FC_3_ADDR);
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iot_raw_write_reg(RAW_REG_TYPE_MAC, CFG_TX_SW_FC_0_ADDR, fc[0]);
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iot_raw_write_reg(RAW_REG_TYPE_MAC, CFG_TX_SW_FC_1_ADDR, fc[1]);
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iot_raw_write_reg(RAW_REG_TYPE_MAC, CFG_TX_SW_FC_2_ADDR, fc[2]);
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iot_raw_write_reg(RAW_REG_TYPE_MAC, CFG_TX_SW_FC_3_ADDR, fc[3]);
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iot_raw_write_reg(RAW_REG_TYPE_MAC, CFG_TX_FC_DATA0_ADDR, fc[0]);
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iot_raw_write_reg(RAW_REG_TYPE_MAC, CFG_TX_FC_DATA1_ADDR, fc[1]);
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iot_raw_write_reg(RAW_REG_TYPE_MAC, CFG_TX_FC_DATA2_ADDR, fc[2]);
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iot_raw_write_reg(RAW_REG_TYPE_MAC, CFG_TX_FC_DATA3_ADDR, fc[3]);
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/* set sw fc valid */
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iot_raw_write_reg(RAW_REG_TYPE_MAC, CFG_SW_FC_VALID_ADDR, 0x1);
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/* clear interrupt status */
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mac_rawdata_tx_start_isr_clr();
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}
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#endif
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#if ENABLE_CCA_ISR == 1
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/* TODO: for kl3, need move to proi 0/1 */
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mac_set_cca_pcs_busy_timeout_ms(0, 0);
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mac_set_cca_pcs_idle_timeout_ms(0, 0);
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mac_pdev_t *pdev = get_pdev_ptr(PLC_PDEV_ID);
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uint32_t int_status;
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int_status = mac_cca_get_int_sts(pdev->cca_isr_pri);
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mac_cca_int_clear(pdev->cca_isr_pri, int_status);
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if(int_status & (1<<MAC_INT_PCS_BUSY_TIMEOUT_OFFSET))
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{
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/*TODO: handle pcs busy interrupte*/
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}
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if(int_status & (1<<MAC_INT_PCS_IDLE_TIMEOUT_OFFSET))
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{
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/*TODO: handle pcs idle interrupte*/
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}
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mac_set_cca_pcs_busy_timeout_ms(1, MAC_PCS_BUSY_TIMEOUT);
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mac_set_cca_pcs_idle_timeout_ms(1, MAC_PCS_IDLE_TIMEOUT);
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#endif
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if (cnt) {
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dsr[cnt++] = MAC_DSR_ISR_SYNC_ID;
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p_mac_isr_ctx->dsr_callback(dsr, cnt);
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mac_isr_stop();
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}
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/* if entry cert mode,
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* use os_task_switch_context sw can immediately entry dsr
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* to save time
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*/
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mac_pdev_t *pdev_t = g_mac_pdev[PLC_PDEV_ID];
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if (1 == pdev_t->switch_ctxt_in_mac_isr) {
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os_task_switch_context();
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}
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return 0;
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}
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static uint32_t IRAM_ATTR mac_isr_handler(uint32_t vector, iot_addrword_t data)
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{
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uint8_t i, j, tmp;
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uint32_t int_status;
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uint8_t dsr[32], cnt;
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(void)vector;
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(void)data;
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/* read pending interrupt status */
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int_status = RGF_MAC_READ_REG(CFG_MAC_INT_STS_ADDR);
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int_status >>= MAC_INT_STATUS_OFFSET;
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/* clear pending interrupt status */
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RGF_MAC_WRITE_REG(CFG_MAC_INT_CLR_ADDR,
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(int_status << MAC_INT_CLR_0_OFFSET));
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i = 0;
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cnt = 0;
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while (int_status) {
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tmp = int_status & 0xFF;
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while (tmp) {
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#if WAR_TIMEOUT_TX_ABORT
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/*check phy tx abort*/
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mac_check_timeout_tx_abort();
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#endif
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j = iot_bitops_fls(tmp) - 1;
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tmp &= ~(0x1 << j);
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dsr[cnt] = mac_isr_get_dsr_id(i + j);
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cnt++;
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#if MAC_SCHED_HW_DEBUG
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if (MAC_ISR_BC_ALERT_ID == (i + j)) {
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//reorder beacon alert time
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g_mac_pdev[PLC_PDEV_ID]->mac_isr_rx_fc_ts_ntb = \
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RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
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}
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#endif
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/*count mac underrun_cnt */
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if (MAC_ISR_TX_UNDERRUN_ID == (i + j)) {
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g_mac_pdev[PLC_PDEV_ID]->mac_underrun_cnt++;
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}
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/* isr callback */
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if (MAC_ISR_MPDU_RX_ID == (i + j)) {
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#if ENA_HW_SYNC_PPM_WAR
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mac_hw_sync_ppm_clr(PLC_PDEV_ID);
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#endif
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#if DEBUG_INVAILD_ADDR
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mac_judge_ring_buf_validation();
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#endif
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/* WAR for bug id 244, save sof fc info
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* TODO:remember a cnt, and check at
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* the top of SACK handler
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*/
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#if MAC_TIMESTAMPING
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mac_pdev_t *pdev_t = g_mac_pdev[PLC_PDEV_ID];
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pdev_t->mac_isr_ntb = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
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#endif
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}
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if (MAC_ISR_MPDU_TX_COMP_ID == (i + j)) {
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/* tx comp isr */
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mac_pdev_t *pdev = g_mac_pdev[PLC_PDEV_ID];
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pdev->fc_hw[0] = iot_raw_read_reg(RAW_REG_TYPE_MAC, CFG_TX_FC_DATA0_ADDR);
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pdev->fc_hw[1] = iot_raw_read_reg(RAW_REG_TYPE_MAC, CFG_TX_FC_DATA1_ADDR);
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pdev->fc_hw[2] = iot_raw_read_reg(RAW_REG_TYPE_MAC, CFG_TX_FC_DATA2_ADDR);
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pdev->fc_hw[3] = iot_raw_read_reg(RAW_REG_TYPE_MAC, CFG_TX_FC_DATA3_ADDR);
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}
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}
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int_status >>= 8;
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i += 8;
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}
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if (cnt) {
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dsr[cnt] = MAC_DSR_ISR_SYNC_ID;
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cnt++;
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p_mac_isr_ctx->dsr_callback(dsr, cnt);
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mac_isr_stop();
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}
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/* if entry cert mode,
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* use os_task_switch_context sw can immediately entry dsr
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* to save time
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*/
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mac_pdev_t *pdev_t = g_mac_pdev[PLC_PDEV_ID];
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if(1 == pdev_t->switch_ctxt_in_mac_isr)
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{
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os_task_switch_context();
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}
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return 0;
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}
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|
|
||
|
static void mac_isr_reset()
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||
|
{
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||
|
uint32_t prio_mask;
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||
|
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||
|
/* disable all mac interrupt and clean up any pending interrupt */
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||
|
p_mac_isr_ctx->isr_mask = 0;
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||
|
RGF_MAC_WRITE_REG(CFG_INT_ENA_MASK_ADDR, p_mac_isr_ctx->isr_mask);
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||
|
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||
|
/* clean up all pending interrupt */
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||
|
RGF_MAC_WRITE_REG(CFG_MAC_INT_CLR_ADDR, CFG_INT_ENABLE_MASK_MASK);
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||
|
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||
|
/* assign priority 0 interrupts, CPU0 & CPU1 use the interrupt */
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|
prio_mask = 1 << (MAC_ISR_MPDU_RX_ID + CFG_INT_PRI0_MASK_OFFSET);
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|
RGF_MAC_WRITE_REG(CFG_INT_PRI0_MASK_ADDR, prio_mask);
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|
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||
|
/* assign priority 1 interrupts */
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prio_mask = 1 << (MAC_ISR_BC_MISS_ID + CFG_INT_PRI1_MASK_OFFSET);
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prio_mask |= 1 << (MAC_ISR_SCH_STOP_ID + CFG_INT_PRI1_MASK_OFFSET);
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|
prio_mask |= 1 << (MAC_ISR_HWQ_STOP_ID + CFG_INT_PRI1_MASK_OFFSET);
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|
/* move from priority 0 */
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|
prio_mask |= 1 << (MAC_ISR_RX_LOW_WATERMARK_ID + CFG_INT_PRI0_MASK_OFFSET);
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|
prio_mask |= 1 << (MAC_ISR_MPDU_TX_COMP_ID + CFG_INT_PRI0_MASK_OFFSET);
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|
prio_mask |= 1 << (MAC_ISR_MPDU_LIST_TX_COMP_ID + CFG_INT_PRI0_MASK_OFFSET);
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|
prio_mask |= 1 << (MAC_ISR_PB_RX_ID + CFG_INT_PRI0_MASK_OFFSET);
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|
RGF_MAC_WRITE_REG(CFG_INT_PRI1_MASK_ADDR, prio_mask);
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||
|
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||
|
/* assign priority 2 interrupts */
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||
|
prio_mask = 1 << (MAC_ISR_BC_ALERT_ID + CFG_INT_PRI2_MASK_OFFSET);
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|
prio_mask |= 1 << (MAC_ISR_BC_RX_ID + CFG_INT_PRI2_MASK_OFFSET);
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|
prio_mask |= 1 << (MAC_ISR_START_DESC_ERR_ID + CFG_INT_PRI2_MASK_OFFSET);
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|
prio_mask |= 1 << (MAC_ISR_END_DESC_ERR_ID + CFG_INT_PRI2_MASK_OFFSET);
|
||
|
prio_mask |= 1 << (MAC_ISR_TX_UNDERRUN_ID + CFG_INT_PRI2_MASK_OFFSET);
|
||
|
prio_mask |= 1 << (MAC_ISR_FC_RX_ID + CFG_INT_PRI2_MASK_OFFSET);
|
||
|
prio_mask |= 1 << (MAC_ISR_RX_DESC_OVERFLOW_ID + CFG_INT_PRI2_MASK_OFFSET);
|
||
|
prio_mask |= 1 << (MAC_ISR_RX_LOAD_OVERFLOW_ID + CFG_INT_PRI2_MASK_OFFSET);
|
||
|
RGF_MAC_WRITE_REG(CFG_INT_PRI2_MASK_ADDR, prio_mask);
|
||
|
|
||
|
/* assign priority 3 interrupts, only cpu1 use the interrupt*/
|
||
|
prio_mask = 0;
|
||
|
RGF_MAC_WRITE_REG(CFG_INT_PRI3_MASK_ADDR, prio_mask);
|
||
|
}
|
||
|
|
||
|
void mac_isr_enable(uint8_t id)
|
||
|
{
|
||
|
uint32_t int_mask;
|
||
|
|
||
|
if (id <= MAC_ISR_MAX_ID) {
|
||
|
int_mask = 1 << (CFG_INT_ENABLE_MASK_OFFSET + id);
|
||
|
if (!(p_mac_isr_ctx->isr_mask & int_mask)) {
|
||
|
p_mac_isr_ctx->isr_mask |= int_mask;
|
||
|
RGF_MAC_WRITE_REG(CFG_INT_ENA_MASK_ADDR, p_mac_isr_ctx->isr_mask);
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void mac_isr_disable(uint8_t id)
|
||
|
{
|
||
|
uint32_t int_mask;
|
||
|
|
||
|
if (id <= MAC_ISR_MAX_ID) {
|
||
|
int_mask = 1 << (CFG_INT_ENABLE_MASK_OFFSET + id);
|
||
|
if (p_mac_isr_ctx->isr_mask & int_mask) {
|
||
|
p_mac_isr_ctx->isr_mask &= ~int_mask;
|
||
|
RGF_MAC_WRITE_REG(CFG_INT_ENA_MASK_ADDR, p_mac_isr_ctx->isr_mask);
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void mac_isr_ext1_enable(uint8_t id)
|
||
|
{
|
||
|
uint32_t int_mask;
|
||
|
|
||
|
if (id <= MAC_ISR_EXT1_MAX_ID) {
|
||
|
int_mask = RGF_MAC_READ_REG(CFG_MAC_INT_EXT_3_ENA_ADDR);
|
||
|
int_mask |= 1 << id;
|
||
|
RGF_MAC_WRITE_REG(CFG_MAC_INT_EXT_3_ENA_ADDR, int_mask);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void mac_isr_ext1_disable(uint8_t id)
|
||
|
{
|
||
|
uint32_t int_mask;
|
||
|
|
||
|
if (id <= MAC_ISR_EXT1_MAX_ID) {
|
||
|
int_mask = RGF_MAC_READ_REG(CFG_MAC_INT_EXT_3_ENA_ADDR);
|
||
|
int_mask &= ~(1 << id);
|
||
|
RGF_MAC_WRITE_REG(CFG_MAC_INT_EXT_3_ENA_ADDR, int_mask);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void mac_isr_start()
|
||
|
{
|
||
|
/* enable soc irq */
|
||
|
iot_interrupt_unmask(p_mac_isr_ctx->isr_3_h);
|
||
|
iot_interrupt_unmask(p_mac_isr_ctx->isr_2_h);
|
||
|
iot_interrupt_unmask(p_mac_isr_ctx->isr_1_h);
|
||
|
iot_interrupt_unmask(p_mac_isr_ctx->isr_0_h);
|
||
|
}
|
||
|
|
||
|
void IRAM_ATTR mac_isr_stop()
|
||
|
{
|
||
|
/* disable soc irq */
|
||
|
iot_interrupt_mask(p_mac_isr_ctx->isr_0_h);
|
||
|
iot_interrupt_mask(p_mac_isr_ctx->isr_1_h);
|
||
|
iot_interrupt_mask(p_mac_isr_ctx->isr_2_h);
|
||
|
iot_interrupt_mask(p_mac_isr_ctx->isr_3_h);
|
||
|
}
|
||
|
|
||
|
void mac_isr_init(dsr_notification_func_t callback)
|
||
|
{
|
||
|
os_mem_set(p_mac_isr_ctx, 0, sizeof(*p_mac_isr_ctx));
|
||
|
|
||
|
p_mac_isr_ctx->dsr_callback = callback;
|
||
|
|
||
|
mac_isr_reset();
|
||
|
|
||
|
/* allocate soc irq resource */
|
||
|
p_mac_isr_ctx->isr_0_h = iot_interrupt_create(HAL_VECTOR_MAC_0,
|
||
|
HAL_INTR_PRI_7, (iot_addrword_t)NULL, mac_isr_handler);
|
||
|
p_mac_isr_ctx->isr_1_h = iot_interrupt_create(HAL_VECTOR_MAC_1,
|
||
|
HAL_INTR_PRI_7, (iot_addrword_t)NULL, mac_isr_handler);
|
||
|
p_mac_isr_ctx->isr_2_h = iot_interrupt_create(HAL_VECTOR_MAC_2,
|
||
|
HAL_INTR_PRI_7, (iot_addrword_t)NULL, mac_isr_handler);
|
||
|
p_mac_isr_ctx->isr_3_h = iot_interrupt_create(HAL_VECTOR_MAC_3,
|
||
|
HAL_INTR_PRI_7, (iot_addrword_t)NULL, mac_isr_ext1_handler);
|
||
|
|
||
|
/* attach soc irq resource */
|
||
|
iot_interrupt_attach(p_mac_isr_ctx->isr_0_h);
|
||
|
iot_interrupt_attach(p_mac_isr_ctx->isr_1_h);
|
||
|
iot_interrupt_attach(p_mac_isr_ctx->isr_2_h);
|
||
|
iot_interrupt_attach(p_mac_isr_ctx->isr_3_h);
|
||
|
|
||
|
/* systic mac cb register */
|
||
|
#if HW_PLATFORM >= HW_PLATFORM_FPGA
|
||
|
os_task_set_systick_cb(mac_timer_ctxt);
|
||
|
#endif
|
||
|
|
||
|
/* init rf isr */
|
||
|
mac_rf_isr_init(callback);
|
||
|
}
|
||
|
|
||
|
void mac_isr_clear(uint32_t isr_evt)
|
||
|
{
|
||
|
if (isr_evt > MAC_ISR_MAX_ID) {
|
||
|
IOT_ASSERT(0);
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
/* clear isr */
|
||
|
RGF_MAC_WRITE_REG(CFG_MAC_INT_CLR_ADDR, 1 << isr_evt);
|
||
|
}
|
||
|
|
||
|
void IRAM_ATTR mac_check_nncco_fc()
|
||
|
{
|
||
|
uint32_t bb_fc[4] = {0};
|
||
|
/* if nncco , need fill back desc */
|
||
|
bb_fc[0] = RGF_RAW_READ_REG(CFG_TX_FC_DATA0_ADDR);
|
||
|
bb_fc[1] = RGF_RAW_READ_REG(CFG_TX_FC_DATA1_ADDR);
|
||
|
bb_fc[2] = RGF_RAW_READ_REG(CFG_TX_FC_DATA2_ADDR);
|
||
|
bb_fc[3] = RGF_RAW_READ_REG(CFG_TX_FC_DATA3_ADDR);
|
||
|
/* judge delimeter type */
|
||
|
if (FC_DELIM_NNCCO == (bb_fc[0] & 0x3)) {
|
||
|
g_phy_ctxt.indep.nn_cco_fc[0] = bb_fc[0];
|
||
|
g_phy_ctxt.indep.nn_cco_fc[1] = bb_fc[1];
|
||
|
g_phy_ctxt.indep.nn_cco_fc[2] = bb_fc[2];
|
||
|
g_phy_ctxt.indep.nn_cco_fc[3] = bb_fc[3];
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void IRAM_ATTR mac_timer_ctxt()
|
||
|
{
|
||
|
#if PPM_NTB_CAL
|
||
|
mac_ntb_sync_ppm_from_isr();
|
||
|
#endif
|
||
|
mac_zc_systic_trig();
|
||
|
/* check fc */
|
||
|
mac_check_nncco_fc();
|
||
|
}
|
||
|
#endif /* HW_PLATFORM == HW_PLATFORM_SIMU */
|