kunlun/plc/halmac/hw3/plc_inc/mac_reset.h

/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/
#ifndef RESET_H
#define RESET_H

#ifdef __cplusplus
extern "C" {
#endif

typedef enum {
    MAC_RST_REASON_COLD,
    MAC_RST_REASON_WARM,
} MAC_RST_REASON_ID;

typedef enum {
    CONT_RX_ABORT4,
    PHY_TX_HANG,
} MAC_PHY_RESET_REASON;

/* 40 ticks for 1ms if 0.040us units for each tick */
#define TICKS_MS 25000 // 1000us / 0.04us

#define MAC_PHY_IDLE_STS           0
#define MAC_PHY_RX_STS             1
#define MAC_PHY_TX_STS             2
#define MAC_PHY_UNKNOW_STS         3

#define MAC_RX_LISTEN_STS          (0 << 15)
#define MAC_RX_FC_STS              (1 << 15)
#define MAC_RX_PLD_STS             (2 << 15)
#define MAC_TX_CCA_WAIT_STS        (4 << 15)
#define MAC_DO_NOT_BBAI_STS        (5 << 15)

/* 0x320 : cfg_mac_dbg_bus_sel[11:8]=3
 *         cfg_mac_dbg_bus_sel[7:5]=1
 */
#define MAC_DEBUG_VALUE_320        0x320

/* 0x2   : cfg_mac_dbg_bus_sel[11:8]=0
 *         cfg_mac_dbg_bus_sel[6:4]=0
 *         cfg_mac_dbg_bus_sel[1]=1
 */
#define MAC_DEBUG_VALUE_2          0x2

/* 0x12  : cfg_mac_dbg_bus_sel[11:8]=0
 *         cfg_mac_dbg_bus_sel[6:4]=1
 *         cfg_mac_dbg_bus_sel[1]=1
 */
#define MAC_DEBUG_VALUE_12         0x12

/* 0x22  : cfg_mac_dbg_bus_sel[11:8]=0
 *         cfg_mac_dbg_bus_sel[6:4]=2
 *         cfg_mac_dbg_bus_sel[1]=1
 */
#define MAC_DEBUG_VALUE_22         0x22

/* 0x32  : cfg_mac_dbg_bus_sel[11:8]=0
 *         cfg_mac_dbg_bus_sel[6:4]=3
 *         cfg_mac_dbg_bus_sel[1]=1
 */
#define MAC_DEBUG_VALUE_32         0x32

/* mac_dbg_bus[17:15] */
#define MAC_DEBUG_VALUE_MASK_BIT_15_17   0x38000
/* mac_dbg_bus[18:13] */
#define MAC_DEBUG_VALUE_MASK_BIT_13_18   0x7E000

/* mac wait tx idle time ms */
#define MAC_WAIT_TX_IDLE_TIEM_MS         40    //40ms

/* stop vdev trigger stop schedule */
#define MAC_TX_HANG_STATUS_1             1
/* switch band trigger stop schedule */
#define MAC_TX_HANG_STATUS_2             2
/* poweroff trigger stop schedule */
#define MAC_TX_HANG_STATUS_3             3
/* updata beacon trigger stop schedule */
#define MAC_TX_HANG_STATUS_4             4
/* power recover trigger stop schedule */
#define MAC_TX_HANG_STATUS_5             5

#define MACC_TX_HANG_STATUS_MAX          0xff

/* reset mac API */
void mac_reset(MAC_RST_REASON_ID rst_reason);

/* warm reset hold */
void warm_rst_mac_hold();

/* warm reset release */
void warm_rst_mac_release();

/* reset mac or bb for WAR HW issue */
void mac_warm_reset_war(uint32_t flag);

void mac_set_sw_idle_mode(uint32_t ena, uint32_t is_idle);

uint32_t mac_wait_phy_txrx_idle();

void mac_force_phy_tx_ready(uint32_t ena, uint32_t is_force_ready);

void mac_tx_wait_all_queue_idle(uint32_t iscco, uint32_t time_ms);

void mac_cfg_reg_reset();

void mac_sw_trig_need_en(bool_t ena);

void mac_sw_trig_start(bool_t ena);

void mac_dma_ckl_sel(bool_t ena);

/**
 * @brief mac_get_phy_txrx_sts - get phy txrx status.
 * @param  null
 */
uint32_t mac_get_phy_txrx_sts();

/**
 * @brief mac_set_sts_idle     - mac set status to idle.
 * @param  null
 */
uint32_t mac_set_sts_idle();

/**
 * @brief mac_free_sts_idle     - mac free status to idle.
 * @param  null
 */
uint32_t mac_free_sts_idle();

/**
 * @brief mac_dbg_bus_get_mac_sts   - mac_dbg_bus_get_mac_sts.
 * @param  value                    - value
 * @param  mask                     - mask
 * @return  0
 */
uint32_t mac_dbg_bus_get_mac_sts(uint32_t value, uint32_t mask);

/**
 * @brief mac_set_pcs_busy   - mac set pcs busy.
 * @param  enable :            enable
 * @param  value :             value
 * @return  0
 */
uint32_t mac_set_pcs_busy(uint32_t enable, uint32_t value);

/**
 * @brief mac_set_pcs_busy_from_isr   - mac set pcs busy.
 * @param  enable :                   - enable
 * @param  value :                    - value
 * @return  0
 */
uint32_t mac_set_pcs_busy_from_isr(uint32_t enable, uint32_t value);

/**
 * @brief mac_set_fc_crc_done  - mac set fc crc done.
 * @param  enable :            enable
 * @param  value :             value
 * @return  0
 */
uint32_t mac_set_fc_crc_done(uint32_t enable, uint32_t value);

/**
 * @brief mac_set_reg_tx_abort_debug_value  - mac set reg tx abort debug value.
                                              not rx abort and keep the scene.
 * @return  0
 */
uint32_t mac_set_reg_tx_abort_debug_value();

/**
 * @brief mac_force_mac_phy_interface    - mac force mac phy interface
 *                                         entry tx ready status.
 * @param  value :                         0/1
 * @return  0
 */
uint32_t mac_force_mac_phy_interface(uint32_t value);

#ifdef __cplusplus
}
#endif

#endif // !RESET_H