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kunlun/mfgtool/ram/inc/hw3/ram_hw.h

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2024-09-28 14:24:04 +08:00
/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
****************************************************************************/
#ifndef RAM_HW_H
#define RAM_HW_H
#define RAM_SYSCLK_SET_AS_150M() \
do {\
clk_core_freq_set(CPU_FREQ_150M);\
} while(0)
#define RAM_CACHE_INIT() \
do {\
ahb_cache_disable(); \
ahb_set_cache_buffer_mode(); \
ahb_cache_enable(); \
ahb_cache_fill_valid_space(); \
} while (0)
#define RAM_EFUSE_DUMP() ramEfuseDump(0, 128)
#define RAM_IMG_OEM_TYPE imgV1OEM
#define RAM_DEVICE_TYPE devV1Kunlun3
#define RAM_CHIP_TYPE 3 /* KL3 */
#define HASH_IV_BASE (0x140+EFUSE_BASEADDR)
#define FLASH_RUN_ADDR_CHECK(addr) ((((addr & 0xff000000) == (ICACHE0_SFC_RAM_BASEADDR & 0xff000000)) || \
((addr & 0xff000000) == (ICACHE1_SFC_RAM_BASEADDR & 0xff000000))) ? 1 : 0)
#define REG_SFC_CFG0 (SFC_REG_BASEADDR + CFG_SFC_CFG0_ADDR)
#define SFC_CRYPT_OFFSET SFC_CRYPT_MODE_MASK
#endif //RAM_HW_H