kunlun/plc/halphy/hw2/phy_mix.c

/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/
#include "mac_sys_reg.h"
#include "phy_reg.h"
#include "hw_reg_api.h"
#include "phy_tx_reg.h"
#include "phy_bb.h"
#include "phy_rx_fd_reg.h"
#include "phy_rxtd_reg.h"
#include "phy_mix.h"
#include "phy_tmap.h"

void phy_tx_dly_gp_set(uint16_t dly)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_TX_READ_REG(CFG_BB_TX_DLY_ADDR);
    REG_FIELD_SET(SW_TX_DLY_GP, tmp, dly);
    PHY_TX_WRITE_REG(CFG_BB_TX_DLY_ADDR, tmp);
#else
    (void)dly;
#endif
}

void phy_tx_long_pream_enable()
{
    uint32_t tmp = 0;

    /* enable phy tx long preamble */
    tmp = RGF_MAC_READ_REG(CFG_PHY_CTRL_ADDR);
    REG_FIELD_SET(CFG_PHY_TX_LONG_PREAM_EN, tmp, 1);
    RGF_MAC_WRITE_REG(CFG_PHY_CTRL_ADDR,tmp);

    /* matching SG num of preambles to be sent */
    tmp = PHY_READ_REG(CFG_BB_PRE_CFG_ADDR);
    REG_FIELD_SET(SW_TX_PRE_NUM,tmp,13);
    PHY_WRITE_REG(CFG_BB_PRE_CFG_ADDR, tmp);

#if PLC_SUPPORT_CCO_ROLE
    tmp = PHY_TX_READ_REG(CFG_BB_TX_DLY_ADDR);
    REG_FIELD_SET(SW_TX_DLY_SG, tmp, 4095);
    REG_FIELD_SET(SW_TX_DLY_GP, tmp, 4095);
    PHY_TX_WRITE_REG(CFG_BB_TX_DLY_ADDR, tmp);
#else
    tmp = PHY_TX_READ_REG(CFG_BB_TX_DLY_ADDR);
    REG_FIELD_SET(SW_TX_DLY_SG, tmp, 4095);
    REG_FIELD_SET(SW_TX_DLY_GP, tmp, 4095);
    PHY_TX_WRITE_REG(CFG_BB_TX_DLY_ADDR, tmp);
#endif

}

void phy_pb_robo_set(bool_t nsg_en, bool_t mn_invert)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
    uint32_t tmp = 0;

    tmp = PHY_READ_REG(CFG_BB_PB_ROBO_ADDR);
    REG_FIELD_SET(SW_IS_NSG_PB_ROBO, tmp, nsg_en);
    REG_FIELD_SET(SW_MN_INVERT, tmp, mn_invert);
    PHY_WRITE_REG(CFG_BB_PB_ROBO_ADDR, tmp);
#else
    (void)nsg_en;
    (void)mn_invert;
#endif
}

void phy_td_robo_mode_set(bool_t en, uint8_t robo_mod)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
    uint32_t tmp = 0;

    tmp = PHY_READ_REG(CFG_BB_TD_ROBO_ADDR);
    REG_FIELD_SET(SW_TD_ROBO_MODE, tmp, robo_mod);
    REG_FIELD_SET(SW_TD_ROBO_EN, tmp, en);
    PHY_WRITE_REG(CFG_BB_TD_ROBO_ADDR, tmp);
#else
    (void)en;
    (void)robo_mod;
#endif
}

void phy_tx_pre_num_set(uint16_t pre_num)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
    uint32_t tmp = 0;

    tmp = PHY_READ_REG(CFG_BB_PRE_CFG_ADDR);
    REG_FIELD_SET(SW_TX_PRE_NUM, tmp, pre_num);
    PHY_WRITE_REG(CFG_BB_PRE_CFG_ADDR, tmp);
#else
    (void)pre_num;
#endif
}

void phy_2syncm_en(bool_t en)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
    uint32_t tmp = 0;

    tmp = PHY_RX_FD_READ_REG(CFG_BB_FRAME_SYNC_ADDR);
    REG_FIELD_SET(SW_2SYNCM_EN, tmp, en);
    PHY_RX_FD_WRITE_REG(CFG_BB_FRAME_SYNC_ADDR, tmp);
#else
    (void)en;
#endif
}

void phy_sync_symb_acc_en(bool_t en)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
    uint32_t tmp = 0;

    tmp = PHY_RX_FD_READ_REG(CFG_BB_FRAME_SYNC_ADDR);
    REG_FIELD_SET(SW_SYNC_SYMB_ACC_EN, tmp, en);
    PHY_RX_FD_WRITE_REG(CFG_BB_FRAME_SYNC_ADDR, tmp);
#else
    (void)en;
#endif
}

void phy_skip_for_td_robo_set(uint32_t skip)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_RXTD_READ_REG(CFG_BB_SKIP_FOR_TD_ROBO_ADDR);
    REG_FIELD_SET( \
        SW_EXT_SKIP_FOR_TD_TOBO, tmp, skip);
    PHY_RXTD_WRITE_REG(CFG_BB_SKIP_FOR_TD_ROBO_ADDR, tmp);
#else
    (void)skip;
#endif
}

void phy_neg_pream_ctrl_set(uint16_t symb_num)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_READ_REG(CFG_BB_NEG_PREAM_CTRL_ADDR);
    REG_FIELD_SET( \
        SW_NEG_PREAM_SYMB_NUM, tmp, symb_num);
    PHY_WRITE_REG(CFG_BB_NEG_PREAM_CTRL_ADDR, tmp);
#else
    (void)symb_num;
#endif
}

void phy_av_high_speed_gi_x_set(uint8_t gi_x)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_READ_REG(CFG_BB_PLD_CFG_ADDR);
    REG_FIELD_SET(SW_AV_HIGH_SPEED_GI_X, tmp, gi_x);
    PHY_WRITE_REG(CFG_BB_PLD_CFG_ADDR, tmp);
#else
    (void)gi_x;
#endif
}

void phy_av_high_speed_code_rate_set(uint8_t rate)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_READ_REG(CFG_BB_PLD_CFG_ADDR);
    REG_FIELD_SET(SW_AV_HIGH_SPEED_CODE_RATE, tmp, rate);
    PHY_WRITE_REG(CFG_BB_PLD_CFG_ADDR, tmp);
#else
    (void)rate;
#endif
}

void phy_rxfd_mc_en(bool_t en)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_RX_FD_READ_REG(CFG_BB_MC_PER_SUBC_ADDR);
    REG_FIELD_SET(SW_MC_PER_SUBC_EN, tmp, en);
    PHY_RX_FD_WRITE_REG(CFG_BB_MC_PER_SUBC_ADDR, tmp);
#else
    (void)en;
#endif
}

void phy_tx_prs_pre_num_cal(uint8_t robo_mod)
{
    uint16_t sw_tx_pream_num = 0;
    uint16_t neg_pream_num = 0;
    uint16_t pos_pream_num = 0;
    uint32_t proto_id = PHY_PROTO_TYPE_GET();

    if(proto_id == PLC_PROTO_TYPE_GP) {
        sw_tx_pream_num = PHY_SPEC_TX_PREAM_NUM_GP;
    } else if(proto_id == PLC_PROTO_TYPE_SPG) {
        sw_tx_pream_num = PHY_SPEC_TX_PREAM_NUM_SPG;
    } else if(proto_id == PLC_PROTO_TYPE_SG) {
        sw_tx_pream_num = PHY_SPEC_TX_PREAM_NUM_SG;
    }

    /* cal neg preamble number */
    neg_pream_num = \
        ((2 << (robo_mod - 1)) << 1) + \
        ((2 << (robo_mod - 1)) >> 1) + 1;

    /* config neg preamble number */
    phy_neg_pream_ctrl_set(neg_pream_num);

    /* cal pos preamble number */
    pos_pream_num  = \
        sw_tx_pream_num * (2 << (robo_mod - 1));

    /* cal total preamble number*/
    sw_tx_pream_num = neg_pream_num + pos_pream_num;

    /* config total preamble number */
    phy_tx_pre_num_set(sw_tx_pream_num);
    phy_sg_bmcs_pream_num_set( \
        sw_tx_pream_num, sw_tx_pream_num, sw_tx_pream_num);
    phy_sg_emcs_pream_num_set( \
        sw_tx_pream_num, sw_tx_pream_num, sw_tx_pream_num);
}

void phy_gp_fc101_set(bool_t always_en, uint8_t thr, bool_t en)
{
#if HW_PLATFORM != HW_PLATFORM_SIMU
    uint32_t tmp = 0;

    tmp = PHY_RX_FD_READ_REG(CFG_BB_FC101_ADDR);
    REG_FIELD_SET(SW_ALWAYS_FC101_EN, tmp, always_en);
    REG_FIELD_SET(SW_FC101_THR, tmp, thr);
    REG_FIELD_SET(SW_FC101_EN, tmp, en);
    PHY_RX_FD_WRITE_REG(CFG_BB_FC101_ADDR, tmp);
#else
    (void)always_en;
    (void)thr;
    (void)en;
#endif
}

void phy_gp_skip_for_fc101_set(uint16_t skip)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_RXTD_READ_REG(CFG_BB_RX_TD_CTRL_DLY_ADDR);
    REG_FIELD_SET( \
        SW_SKIP_FOR_FC101, tmp, skip);
    PHY_RXTD_WRITE_REG(CFG_BB_RX_TD_CTRL_DLY_ADDR, tmp);
#else
    (void)skip;
#endif
}

void phy_gp_tune_skip_for_fc101_set(uint16_t skip)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_RXTD_READ_REG(CFG_BB_OFFSET_FROM_CORR_ADDR);
    REG_FIELD_SET( \
        SW_TUNE_SKIP_FOR_FC, tmp, skip);
    PHY_RXTD_WRITE_REG(CFG_BB_OFFSET_FROM_CORR_ADDR, tmp);
#else
    (void)skip;
#endif
}

void phy_skip_for_burst_set(uint32_t skip)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_RXTD_READ_REG(CFG_BB_SKIP_FOR_BST_ADDR);
    REG_FIELD_SET(SW_SKIP_FOR_BST, tmp, skip);
    PHY_RXTD_WRITE_REG(CFG_BB_SKIP_FOR_BST_ADDR, tmp);
#else
    (void)skip;
#endif
}

void phy_rxfd_burst_stop_time_set(uint32_t time)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_RX_FD_READ_REG(CFG_BB_TURBO_STOP_BST_ADDR);
    REG_FIELD_SET(SW_TURBO_STOP_TIME_BST, tmp, time);
    PHY_RX_FD_WRITE_REG(CFG_BB_TURBO_STOP_BST_ADDR, tmp);
#else
    (void)time;
#endif
}

void phy_rxtd_bifs_time_set(uint32_t time)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_RXTD_READ_REG(CFG_BB_BIFS_TIME_ADDR);
    REG_FIELD_SET(SW_BIFS_TIME, tmp, time);
    PHY_RXTD_WRITE_REG(CFG_BB_BIFS_TIME_ADDR, tmp);
#else
    (void)time;
#endif
}

void phy_td_robo_ext_init(uint8_t robo_mod)
{
    /* check mod */
    if(!robo_mod) {
        /* not use td robo */
        return;
    }

    /* pb robo */
    phy_pb_robo_set(false, true);

    /* robo mode */
    phy_td_robo_mode_set(true, robo_mod);

    /* cal tx pre num */
    phy_tx_prs_pre_num_cal(robo_mod);

    /* update pkt det time out */
    phy_pkt_time_out_set(35000 * (2 << (robo_mod - 1)));
    phy_pkt_time_out_384_set(4000 * (2 << (robo_mod - 1)));
    phy_find_minus_time_out_384_set(4000 * (2 << (robo_mod - 1)));
    phy_find_minus_time_out_3k_set(50000 * (2 << (robo_mod - 1)));
    phy_skip_for_td_robo_set(3072 * ((2 << (robo_mod - 1)) - 1));

    /* rxfd */
    phy_2syncm_en(false);
    phy_sync_symb_acc_en(true);
}

void phy_spcl_feat_init()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA

    /* enable phy tx long preamble */
#if IOT_TX_LONG_PREAMBLE_ENABLE
    phy_tx_long_pream_enable();
#endif

    /* td robo for reduce power */
    phy_td_robo_ext_init(PHY_TD_ROBO_EXT_MODE_LVL);
#endif
}

void phy_gp_hybrid_mode_init()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    /* global config for all pkt */
    phy_gp_fc101_set(true, 63, true);

    /* neg preamble symb num */
    phy_neg_pream_ctrl_set(2);

    /* skip */
    phy_gp_skip_for_fc101_set(2508);
    phy_gp_tune_skip_for_fc101_set(186);
#endif
}

void phy_gp_burst_init()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    phy_mix_flag_set(false);
    phy_rxfd_rate_offset_set(0);
    phy_av_high_speed_gi_x_set(0);
    /* enable only for tmap */
    phy_rxfd_mc_en(false);
    phy_av_high_speed_code_rate_set(PHY_TURBO_RATE_16_21);
    phy_skip_for_burst_set(1374/2+384*3+192);
    phy_tx_dly_gp_set(487);
    phy_rxfd_burst_stop_time_set(4500);
    phy_rxtd_bifs_time_set(1820);
#endif
}