103 lines
3.6 KiB
C
103 lines
3.6 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#ifndef _BB_CPU_CONFIG_H_
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#define _BB_CPU_CONFIG_H_
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/* os shim includes */
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#include "os_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* define rf chip version */
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/* define the micro indicate version 1 available before 2022.8.15 */
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#define RF_VER1_2022_8_15 1
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/* define txrx use the way of DMA or not */
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#define BB_CPU_TXRX_USE_DMA 0
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/* define bbcpu debug print enable or not */
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#define BB_CPU_DEBUG_PRINT 1
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/* this define indecate hw ring enable for debug rx flow of bbcpu */
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#define BB_CPU_HW_RING_ENABLE 1
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/* rx exception notify plc cpu
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* eg: BB_CPU_RX_RING_SIG_ERR, BB_CPU_RX_RING_PHR_ERR...
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*/
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#define BB_CPU_RX_EXCEPTION_NOTIFY_PLC_CPU 0
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/* delay between txcfg step 1 and txcfg step 2, unit us */
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#define BB_CPU_TXCFG1_TXCFG2_DELAY_US 105
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/* option2 special mode delay between txcfg step 2 and aotx, unit us, 100us */
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#define BB_CPU_AOTX_TXCFG_SPC_OP2_DELAY_US 95
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/* option3 special mode delay between txcfg step 3 and aotx, unit us, 500us */
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#define BB_CPU_AOTX_TXCFG_SPC_OP3_DELAY_US 495
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/* option2 10db power delay between txcfg step 2 and aotx, unit us, 5us */
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#define BB_CPU_AOTX_TXCFG_OP2_DELAY_US 0
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/* option3 10db power delay between txcfg step 3 and aotx, unit us, 150us */
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#define BB_CPU_AOTX_TXCFG_OP3_DELAY_US 145
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/* time --------------------------------> **
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* start_ntb--->notx--->aotx--->sotx
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*/
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/* define the time of notx timer(sw define), uint ntb.
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* need immediately start.
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*/
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#define BB_CPU_NOTX_TIME 1
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/* define the time of aotx timer, uint ntb.
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* time reserved for sw config beacon timestamp. 4us*25.
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*/
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#define BB_CPU_AOTX_TIME 100
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/* define the time of sotx timer, uint ntb.
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* sotx time - aotx time > 50us.
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* 50us*25 + BB_CPU_AOTX_TIME = 1350.
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*/
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#define BB_CPU_SOTX_TIME 1350
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/* define the time of gap for sotx to singal start, uint ntb */
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#define BB_CPU_TX_GOLDEN_GAP_OPT1 375
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#define BB_CPU_TX_GOLDEN_GAP_OPT2 725
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#define BB_CPU_TX_GOLDEN_GAP_OPT3 1400
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/* define the time of gap for tx start */
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#define bb_cpu_get_tx_golden_gap(opt) (BB_CPU_SOTX_TIME \
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- BB_CPU_NOTX_TIME + (((opt) == 1) ? BB_CPU_TX_GOLDEN_GAP_OPT1 \
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: (((opt) == 2) ? BB_CPU_TX_GOLDEN_GAP_OPT2 : BB_CPU_TX_GOLDEN_GAP_OPT3)))
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/* define the time of gap for stf interrupt to signal start, uint ntb */
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#define BB_CPU_RX_GOLDEN_GAP_OPT1 15950
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#define BB_CPU_RX_GOLDEN_GAP_OPT2 16400
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#define BB_CPU_RX_GOLDEN_GAP_OPT3 17250
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/* define the time of gap for rx start, uint ntb */
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#define BB_CPU_RX_GOLDEN_GAP(opt) (((opt) == 1) ? \
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BB_CPU_RX_GOLDEN_GAP_OPT1 : (((opt) == 2) ? \
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BB_CPU_RX_GOLDEN_GAP_OPT2 : BB_CPU_RX_GOLDEN_GAP_OPT3))
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#ifdef __cplusplus
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}
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#endif
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#endif // _BB_CPU_CONFIG_H_
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