279 lines
8.2 KiB
C
279 lines
8.2 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "hw_reg_api.h"
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#include "chip_reg_base.h"
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#include "ada_reg.h"
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#include "iot_config.h"
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#include "phy_bb.h"
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#include "phy_reg.h"
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#include "phy_rx_fd_reg.h"
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#include "phy_ana.h"
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#include "ahb.h"
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#include "os_types.h"
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#include "iot_errno_api.h"
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#include "iot_io.h"
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#include "hw_phy_api.h"
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#include "phy_ada_dump.h"
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#include "phy_agc.h"
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#include "iot_clock.h"
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void phy_ada_dump_adc_init( \
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uint16_t tone_id, \
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uint32_t b_size, \
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uint32_t s_size)
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{
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DaRxPara_t rp = {0};
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/* ADA power on */
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phy_ada_enable(true);
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/* ada_clk_ratio --- 2:1 */
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phy_ada_clk_ratio_cfg(1);
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/* tx ada cfg */
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rp.buf_size = b_size;
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rp.sample_size = s_size;
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rp.mode = ADC_MODE_AUTO;
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rp.thrd = PHY_DUMP_THD_DFT;
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rp.clk_inv_en = true;
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rp.dmsb_inv_en = false;
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phy_ada_rx_cfg(&rp);
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ahb_bb_adc_scale_set(0);
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}
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void phy_ada_dump_dac_init(uint16_t tone_id)
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{
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uint32_t tmp;
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/* ADA power on */
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phy_ada_enable(true);
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/* dac clk inv */
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tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
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REG_FIELD_SET(DAC_CLK_INV,tmp,0x1);
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ADA_WRITE_REG(CFG_ADC_CFG2_ADDR,tmp);
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/* bb adc scale */
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ahb_bb_adc_scale_set(3);
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}
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uint32_t phy_dump_size_cal(uint32_t *b_size, uint32_t *s_size)
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{
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uint32_t ada_dump_trig_mode = ADC_DUMP_TRIG_SUPPORT;
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uint32_t ada_dump_dump_mode = ADC_DUMP_MODE_SUPPORT;
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/* check dump mode */
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IOT_ASSERT(ada_dump_dump_mode <= ADC_DUMP_MODE_PHY && \
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ada_dump_trig_mode <= ADC_DUMP_TRIG_RX_ABORT);
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/* check force mode and so on */
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if (ada_dump_dump_mode == ADC_DUMP_MODE_FORCE) {
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*b_size = 200*K - 1;
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*s_size = 200*K - 1;
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} else if (ada_dump_dump_mode == ADC_DUMP_MODE_AUTO) {
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*b_size = 32*K - 1;
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*s_size = 18*K;
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} else {
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/* TODO: cal dynamic */
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switch (ada_dump_trig_mode)
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{
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case ADC_DUMP_TRIG_CCA:
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case ADC_DUMP_TRIG_PKT_DECT:
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case ADC_DUMP_TRIG_SYNC_OK:
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case ADC_DUMP_TRIG_FC_DONE:
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case ADC_DUMP_TRIG_FC_CRC_OK:
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case ADC_DUMP_TRIG_FC_CRC_FAIL:
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case ADC_DUMP_TRIG_FC_OK_REV_PB:
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*b_size = 150*K - 1;
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*s_size = 120*K;
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break;
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case ADC_DUMP_TRIG_PB_DONE:
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case ADC_DUMP_TRIG_PB_CRC_OK:
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case ADC_DUMP_TRIG_PB_CRC_FAIL:
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case ADC_DUMP_TRIG_RX_ABORT:
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*b_size = 150*K - 1;
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*s_size = 1024;
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break;
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default:
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*b_size = 150*K - 1;
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*s_size = 150*K - 512;
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break;
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}
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}
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return ERR_OK;
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}
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uint32_t phy_ada_dump_addr_get(uint32_t *addr)
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{
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uint32_t size;
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if (addr == NULL) {
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size = 0;
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goto out;
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}
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/* the address reservation use defective, the length use the maximum,
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* and the address is the fixed value.
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*/
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size = 0xFFFFFFFF;
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#if ADC_DUMP_FROM_DDR_EN
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*addr = ADC_DUMP_DDR_ADDR;
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#else
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*addr = ADC_DUMP_RAM_ADDR;
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#endif
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out:
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return size;
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}
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/* ADA adc data dump */
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uint32_t phy_ada_dump_start(uint32_t b_size, \
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uint32_t s_size, \
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ADC_DUMP_MODE mode, \
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uint32_t dly_cnt, \
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uint32_t *trig_offset, \
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uint32_t trig_id, \
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uint32_t speed)
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{
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uint32_t ret = ERR_OK;
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uint32_t tmp = 0;
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uint32_t cnt = 0;
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/* lose data with agc reset */
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phy_gain_chg_rst_en_set(0x0);
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/* pb crc fail gen */
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#ifdef PHY_GEN_PB_CRC_FAIL_SUPPORT
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tmp = PHY_RX_FD_READ_REG(CFG_BB_TURBO_CTRL_ADDR);
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REG_FIELD_SET(SW_SCRAMBLE_MODE, tmp, 1);
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PHY_RX_FD_WRITE_REG(CFG_BB_TURBO_CTRL_ADDR, tmp);
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#endif
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/* reduce robo inter num to avoid reseting rx path */
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#if ADC_DUMP_TRIG_SUPPORT == ADC_DUMP_TRIG_PB_CRC_FAIL
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phy_turbo_dec_inter_set(2);
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#endif
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/* ada dump start address */
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ADA_WRITE_REG(CFG_PSRAM_BUF_PTR_ADDR, ADC_DUMP_DST_ADDR);
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/* 1 select DDR and 0 select AI ram for dump */
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tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
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REG_FIELD_SET(ADA_DUMP_DDR_MODE, tmp, ADC_DUMP_FROM_DDR_EN);
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ADA_WRITE_REG(CFG_ADC_CFG0_ADDR, tmp);
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/*
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* just for trig dump
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* bit[3:2] 0: original speed;
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* 1: 1/2 speed;
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* 2: 1/4 speed;
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* 3: 1/8 speed.
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*/
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tmp = ADA_READ_REG(CFG_ADC_DUMP_CTRL_ADDR);
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if (mode == ADC_DUMP_MODE_AUTO) {
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REG_FIELD_SET(SW_ADC_1BYTE_EN,tmp,true);
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/* bypass adc_sample_ena_sw and adc_trig_pos_en */
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tmp |= (1 << 6) | (1 << 5);
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} else if(mode == ADC_DUMP_MODE_PHY) {
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REG_FIELD_SET(SW_ADC_1BYTE_EN,tmp,false);
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#if ADC_DUMP_TRIG_WITH_THRD == 1
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REG_FIELD_SET(SW_ADC_TRIG_AUTO,tmp,true);
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#else
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REG_FIELD_SET(SW_ADC_TRIG_AUTO,tmp,false);
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#endif
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}
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REG_FIELD_SET(SW_ADC_DUMP_SPEED, tmp, speed);
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ADA_WRITE_REG(CFG_ADC_DUMP_CTRL_ADDR, tmp);
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/* random dump the fixed length data */
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if (b_size == s_size) {
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phy_adc_mode_cfg(ADC_MODE_FORCE);
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} else {
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tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
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if (mode == ADC_DUMP_MODE_AUTO) {
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REG_FIELD_SET(ADC_TRIG_FROM_PHY,tmp,false);
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REG_FIELD_SET(ADC_AUTO_MODE,tmp,false);
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} else if(mode == ADC_DUMP_MODE_PHY) {
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REG_FIELD_SET(ADC_TRIG_FROM_PHY,tmp,true);
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}
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REG_FIELD_SET(ADC_FORCE_MODE,tmp,false);
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ADA_WRITE_REG(CFG_ADC_CFG2_ADDR, tmp);
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}
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/* trig option */
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tmp = PHY_READ_REG(CFG_BB_ADA_DUMP_CFG_ADDR);
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if (mode == ADC_DUMP_MODE_AUTO) {
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REG_FIELD_SET(SW_BB_DUMP_DATA_SEL,tmp,ADC_DUMP_SEL_DATA_RAW);
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} else if(mode == ADC_DUMP_MODE_PHY) {
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REG_FIELD_SET(SW_BB_DUMP_DATA_SEL,tmp,ADC_DUMP_DATA_SEL);
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REG_FIELD_SET(SW_BB_DUMP_TRIG_SEL,tmp,trig_id);
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}
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PHY_WRITE_REG(CFG_BB_ADA_DUMP_CFG_ADDR,tmp);
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if (1) {
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/* clear sample done */
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while(phy_adc_is_sample_done()) {
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tmp = ADA_READ_REG(CFG_ADC_DUMP_CTRL_ADDR);
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tmp |= (1 << 7);
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ADA_WRITE_REG(CFG_ADC_DUMP_CTRL_ADDR, tmp);
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tmp = ADA_READ_REG(CFG_ADC_DUMP_CTRL_ADDR);
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tmp &= ~(1 << 7);
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ADA_WRITE_REG(CFG_ADC_DUMP_CTRL_ADDR, tmp);
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}
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if (mode == ADC_DUMP_MODE_AUTO) {
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tmp = ADA_READ_REG(CFG_ADC_CFG2_ADDR);
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REG_FIELD_SET(ADC_AUTO_MODE,tmp,true);
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ADA_WRITE_REG(CFG_ADC_CFG2_ADDR, tmp);
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} else if(mode == ADC_DUMP_MODE_FORCE || \
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mode == ADC_DUMP_MODE_PHY) {
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/* enable adc to trig dump */
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phy_adc_en_cfg(true);
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/* adc trigger en */
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phy_adc_trig_en_cfg(true);
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}
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while(1) {
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/* sample done */
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if (phy_adc_is_sample_done()) {
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/* get trig address */
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*trig_offset = phy_adc_trig_addr_get();
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/* delau 10 us for ai ram done */
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iot_delay_us(10);
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/* select DDR forever */
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if(ADC_DUMP_FROM_DDR_EN == 0) {
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tmp = ADA_READ_REG(CFG_ADC_CFG0_ADDR);
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REG_FIELD_SET(ADA_DUMP_DDR_MODE, tmp, 1);
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ADA_WRITE_REG(CFG_ADC_CFG0_ADDR, tmp);
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}
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/* dump adc buffer */
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iot_printf("trigger addr:%d\n", *trig_offset);
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break;
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} else {
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/* timeout */
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if (cnt++ > dly_cnt) {
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ret = ERR_FAIL;
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break;
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}
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}
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}
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}
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return ret;
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}
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