kunlun/plc/halphy/hw2/phy_ppm.c

/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

***************************************************************************/

#include "hw_reg_api.h"
#include "phy_reg.h"
#include "phy_dfe_reg.h"
#include "plc_const.h"
#include "phy_ppm.h"

void phy_set_sw_nn_tx_ppm_en(uint8_t enable)
{
    (void)enable;
    return;
}

uint32_t phy_get_sw_nn_tx_ppm_en(void)
{
    return 0;
}

void phy_set_sw_nn_rx_ppm_en(uint8_t enable)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp;
    tmp = PHY_DFE_READ_REG(CFG_BB_PPM_CFG2_ADDR);
    REG_FIELD_SET(SW_NN_PPM_EN, tmp, !!enable);
    PHY_DFE_WRITE_REG(CFG_BB_PPM_CFG2_ADDR, tmp);
#else
    (void)enable;
#endif
    return;
}

uint32_t phy_get_sw_nn_rx_ppm_en(void)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    return (uint32_t)REG_FIELD_GET(SW_NN_PPM_EN, \
        PHY_DFE_READ_REG(CFG_BB_PPM_CFG2_ADDR));
#else
    return 0;
#endif
}

uint32_t phy_set_sw_nn_ppm_para(uint32_t para_id, uint32_t nn_nid,
    int16_t nn_ppm)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp, reg_addr;
    int16_t self_ppm, rx_nn_phase_adj;

    if (para_id > PHY_SW_NN_PPM_PARA_MAX
        || nn_ppm == PLC_MAX_PPM_SUPPORT) {
        return ERR_INVAL;
    }

    /* set nn nid */
    reg_addr = CFG_BB_PHY_NN_NID0_ADDR + \
        ((CFG_BB_PHY_NN_NID1_ADDR - CFG_BB_PHY_NN_NID0_ADDR) * para_id);
    tmp = PHY_READ_REG(reg_addr);
    /* attention to the define of SW_PHY_NN_NID0~7 in the register header file
     * must be consistent.
     */
    REG_FIELD_SET(SW_PHY_NN_NID0, tmp, nn_nid);
    PHY_WRITE_REG(reg_addr, tmp);

    /* st nn ppm and phase ppm adj*/
    self_ppm = REG_FIELD_GET(SW_RX_PPM, \
        PHY_DFE_READ_REG(CFG_BB_PPM_SETTING_ADDR));
    rx_nn_phase_adj = (int16_t)PHY_PPM_TO_NN_PHASE_ADJ(nn_ppm, (self_ppm >> 4));
    reg_addr = CFG_BB_NN_PPM_CFG0_ADDR + \
        ((CFG_BB_NN_PPM_CFG1_ADDR - CFG_BB_NN_PPM_CFG0_ADDR) * para_id);
    tmp = PHY_DFE_READ_REG(reg_addr);
    /* attention to the define of SW_RX_NN_PPM0~7 & SW_RX_NN_PHASE_ADJ_VAL0~7
     * in the register header file must be consistent.
     */
    REG_FIELD_SET(SW_RX_NN_PPM0, tmp, nn_ppm << 4);
    REG_FIELD_SET(SW_RX_NN_PHASE_ADJ_VAL0, tmp, rx_nn_phase_adj);
    PHY_DFE_WRITE_REG(reg_addr, tmp);
#endif
    (void)para_id;
    (void)nn_nid;
    (void)nn_ppm;
    return ERR_OK;
}

uint32_t phy_get_sw_nn_rx_ppm_para(uint32_t para_id, uint32_t *nn_nid,
    int16_t *nn_ppm, int16_t *rx_nn_phase_adj)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp, reg_addr;
    if ((para_id > PHY_SW_NN_PPM_PARA_MAX) ||
        !(nn_nid && nn_ppm && rx_nn_phase_adj)) {
        return ERR_INVAL;
    }

    if (nn_nid) {
        reg_addr = CFG_BB_PHY_NN_NID0_ADDR + \
            ((CFG_BB_PHY_NN_NID1_ADDR - CFG_BB_PHY_NN_NID0_ADDR) * para_id);
        *nn_nid = (uint32_t)(REG_FIELD_GET(SW_PHY_NN_NID0, \
            PHY_READ_REG(reg_addr)));
    }
    if (nn_ppm || rx_nn_phase_adj) {
        reg_addr = CFG_BB_NN_PPM_CFG0_ADDR + \
            ((CFG_BB_NN_PPM_CFG1_ADDR - CFG_BB_NN_PPM_CFG0_ADDR) * para_id);
        tmp = PHY_DFE_READ_REG(reg_addr);
        if (nn_ppm) {
            *nn_ppm = (int16_t)(REG_FIELD_GET(SW_RX_NN_PPM0, tmp) >> 4);
        }
        if (rx_nn_phase_adj) {
            *rx_nn_phase_adj = (int16_t)(REG_FIELD_GET(\
                SW_RX_NN_PHASE_ADJ_VAL0, tmp));
        }
    }
#endif
    (void)para_id;
    (void)nn_nid;
    (void)nn_ppm;
    (void)rx_nn_phase_adj;
    return ERR_OK;
}

uint32_t phy_get_sw_nn_tx_ppm_para(uint32_t para_id, uint32_t *nn_nid,
    int16_t *nn_ppm)
{
    (void)para_id;
    (void)nn_nid;
    (void)nn_ppm;
    return ERR_OK;
}