kunlun/driver/inc/apb_dma.h

/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/

#ifndef _APB_DMA_H_
#define _APB_DMA_H_

#include "iot_config.h"
#include "dma_reg.h"
#include "apb_dma_hw.h"

#ifdef __cplusplus
extern "C" {
#endif

#ifndef OK
#define OK (0)
#define ERROR (-1)
#endif

typedef int STATUS;

enum dma_verify_mode
{
    DMA_NONE, /* Disable this function */
    DMA_CHKSUM,
    DMA_CRC8,
    DMA_CRC16,
    DMA_CRC24,
    DMA_CRC32
};

enum dma_crc_mode
{
    DMA_CRC_NOR,
    DMA_CRC_XOR,
    DMA_CRC_INV,
    DMA_CRC_RAW,
    DMA_CRC_REVERSE,
};

enum dma_crc_polynomial
{
    DMA_CRC8_POLY =  0x00000031,
    DMA_CRC16_POLY = 0x00008005,
    DMA_CRC24_POLY = 0x00800063,
    DMA_CRC32_POLY = 0x04C11DB7
};

#define DESC_BUF_MAX_LEN    0x0FFF
#define DESC_OWNER_CPU      0x0
#define DESC_OWNER_DMA      0x1

typedef void (*dma_int_handler)(int device, int int_status);

typedef struct dma_tx_data_verify {
    enum dma_verify_mode ver_mode;
    /* if ver_mode = DMA_CHKSUM , no need to fill the following items. */
    enum dma_crc_mode crc_mode;
    int crc_init_a0; /* if crc_init_a0 = true, the default value of crc will be 0x0, otherwize will be 0xFFFFFFFF */
    int crc_polynomial;
} dma_verify;

typedef struct dma_int_config {
    dma_int_handler isr;
    int vector;
    int iot_hdl;
} dma_int;

typedef struct dma_entity {
    int base;
    int apb;
    int device;
    desc_t* tx;
    desc_t* rx;
    dma_int int_cfg;
    int verify_value;
    int verify_length;
    dma_verify verify_cfg;
} dma_dev;

typedef struct dma_sw_entity {
    int base;
    int device;
    desc_sw_t* tx;
    desc_sw_t* rx;
    dma_int_handler isr;
    int verify_value;
    int verify_length;
    dma_verify verify_cfg;
} dma_sw_dev;

typedef struct dma_hw_entity {
    int base;
    int device;
    desc_t* tx;
    desc_t* rx;
    dma_int_handler isr;
} dma_hw_dev;

STATUS dma_sw_open(int dev, dma_int_handler isr, dma_verify *verify);
STATUS dma_sw_close(int dev);

int dma_sw_ctrl(int dev, int cmd, int data);
int dma_sw_verify_value_get(int dev);

void dma_hw_init(dma_int_handler isr);
void dma_hw_deinit(int dev);
STATUS dma_hw_open(int dev, dma_int_handler isr, dma_verify *verify);
STATUS dma_hw_close(int dev);
STATUS dma_hw_start_send(int dev, desc_t* lst);
STATUS dma_hw_start_recieve_ext(int dev, desc_t* lst, uint8_t int_en);
void dma_hw_stop_recieve(int dev);
int dma_hw_ctrl(int dev, int cmd, int data);
void dma_hw_rx_octect_num_precise_ctl(int dev, uint8_t en);

#define dma_hw_start_recieve(dev, lst) \
    dma_hw_start_recieve_ext(dev, lst, 1)

/* brief dma_get_link_addr - get dma hw link addr. after dma starts,
 *  link_addr_reg always points to the next desc address.
 * @param dev :  dma drive.
 * @param dir :  1->DMA_HW_RX_LINK_ADDR
 *               0->DMA_HW_TX_LINK_ADDR
 */
uint32_t IRAM_ATTR dma_get_link_addr_reg(int dev, uint8_t dir);

#ifdef __cplusplus
}
#endif

#endif