kunlun/inc/hw/reg/riscv/15/apb_glb_reg.h

//-----------------------------------
#define CFG_APB_RVER_ADDR 0x0000
#define APB_RF_VER_OFFSET 0
#define APB_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_APB_GLB_GEN0_ADDR 0x0004
#define PWM0_EB_OFFSET 30
#define PWM0_EB_MASK 0x40000000
#define SADC_EB_OFFSET 29
#define SADC_EB_MASK 0x20000000
#define IIS_EB_OFFSET 28
#define IIS_EB_MASK 0x10000000
#define DMA10_EB_OFFSET 27
#define DMA10_EB_MASK 0x08000000
#define DMA9_EB_OFFSET 26
#define DMA9_EB_MASK 0x04000000
#define DMA8_EB_OFFSET 25
#define DMA8_EB_MASK 0x02000000
#define DMA7_EB_OFFSET 24
#define DMA7_EB_MASK 0x01000000
#define DMA6_EB_OFFSET 23
#define DMA6_EB_MASK 0x00800000
#define DMA5_EB_OFFSET 22
#define DMA5_EB_MASK 0x00400000
#define DMA4_EB_OFFSET 21
#define DMA4_EB_MASK 0x00200000
#define DMA3_EB_OFFSET 20
#define DMA3_EB_MASK 0x00100000
#define DMA2_EB_OFFSET 19
#define DMA2_EB_MASK 0x00080000
#define DMA1_EB_OFFSET 18
#define DMA1_EB_MASK 0x00040000
#define DMA0_EB_OFFSET 17
#define DMA0_EB_MASK 0x00020000
#define UART_MEM_EB_OFFSET 16
#define UART_MEM_EB_MASK 0x00010000
#define UART_3_EB_OFFSET 15
#define UART_3_EB_MASK 0x00008000
#define CAN_EB_OFFSET 14
#define CAN_EB_MASK 0x00004000
#define WDG0_EB_OFFSET 13
#define WDG0_EB_MASK 0x00002000
#define STMR_EB_OFFSET 12
#define STMR_EB_MASK 0x00001000
#define SPI_S0_EB_OFFSET 11
#define SPI_S0_EB_MASK 0x00000800
#define SPI_M1_EB_OFFSET 10
#define SPI_M1_EB_MASK 0x00000400
#define SPI_M0_EB_OFFSET 9
#define SPI_M0_EB_MASK 0x00000200
#define CLKREG_EB_OFFSET 8
#define CLKREG_EB_MASK 0x00000100
#define PINREG_EB_OFFSET 6
#define PINREG_EB_MASK 0x00000040
#define UART_2_EB_OFFSET 5
#define UART_2_EB_MASK 0x00000020
#define UART_1_EB_OFFSET 4
#define UART_1_EB_MASK 0x00000010
#define INTC0_EB_OFFSET 3
#define INTC0_EB_MASK 0x00000008
#define GTMR0_EB_OFFSET 2
#define GTMR0_EB_MASK 0x00000004
#define GPIO_EB_OFFSET 1
#define GPIO_EB_MASK 0x00000002
#define UART_0_EB_OFFSET 0
#define UART_0_EB_MASK 0x00000001

//-----------------------------------
#define CFG_APB_GLB_GRST0_ADDR 0x0008
#define PWM0_SOFT_RST_OFFSET 30
#define PWM0_SOFT_RST_MASK 0x40000000
#define SADC_SOFT_RST_OFFSET 29
#define SADC_SOFT_RST_MASK 0x20000000
#define IIS_SOFT_RST_OFFSET 28
#define IIS_SOFT_RST_MASK 0x10000000
#define DMA10_SOFT_RST_OFFSET 27
#define DMA10_SOFT_RST_MASK 0x08000000
#define DMA9_SOFT_RST_OFFSET 26
#define DMA9_SOFT_RST_MASK 0x04000000
#define DMA8_SOFT_RST_OFFSET 25
#define DMA8_SOFT_RST_MASK 0x02000000
#define DMA7_SOFT_RST_OFFSET 24
#define DMA7_SOFT_RST_MASK 0x01000000
#define DMA6_SOFT_RST_OFFSET 23
#define DMA6_SOFT_RST_MASK 0x00800000
#define DMA5_SOFT_RST_OFFSET 22
#define DMA5_SOFT_RST_MASK 0x00400000
#define DMA4_SOFT_RST_OFFSET 21
#define DMA4_SOFT_RST_MASK 0x00200000
#define DMA3_SOFT_RST_OFFSET 20
#define DMA3_SOFT_RST_MASK 0x00100000
#define DMA2_SOFT_RST_OFFSET 19
#define DMA2_SOFT_RST_MASK 0x00080000
#define DMA1_SOFT_RST_OFFSET 18
#define DMA1_SOFT_RST_MASK 0x00040000
#define DMA0_SOFT_RST_OFFSET 17
#define DMA0_SOFT_RST_MASK 0x00020000
#define UART_MEM_SOFT_RST_OFFSET 16
#define UART_MEM_SOFT_RST_MASK 0x00010000
#define UART_3_SOFT_RST_OFFSET 15
#define UART_3_SOFT_RST_MASK 0x00008000
#define CAN_SOFT_RST_OFFSET 14
#define CAN_SOFT_RST_MASK 0x00004000
#define WDG0_SOFT_RST_OFFSET 13
#define WDG0_SOFT_RST_MASK 0x00002000
#define STMR_SOFT_RST_OFFSET 12
#define STMR_SOFT_RST_MASK 0x00001000
#define SPI_S0_SOFT_RST_OFFSET 11
#define SPI_S0_SOFT_RST_MASK 0x00000800
#define SPI_M1_SOFT_RST_OFFSET 10
#define SPI_M1_SOFT_RST_MASK 0x00000400
#define SPI_M0_SOFT_RST_OFFSET 9
#define SPI_M0_SOFT_RST_MASK 0x00000200
#define CLKREG_SOFT_RST_OFFSET 8
#define CLKREG_SOFT_RST_MASK 0x00000100
#define PINREG_SOFT_RST_OFFSET 6
#define PINREG_SOFT_RST_MASK 0x00000040
#define UART_2_SOFT_RST_OFFSET 5
#define UART_2_SOFT_RST_MASK 0x00000020
#define UART_1_SOFT_RST_OFFSET 4
#define UART_1_SOFT_RST_MASK 0x00000010
#define INTC0_SOFT_RST_OFFSET 3
#define INTC0_SOFT_RST_MASK 0x00000008
#define GTMR0_SOFT_RST_OFFSET 2
#define GTMR0_SOFT_RST_MASK 0x00000004
#define GPIO_SOFT_RST_OFFSET 1
#define GPIO_SOFT_RST_MASK 0x00000002
#define UART_0_SOFT_RST_OFFSET 0
#define UART_0_SOFT_RST_MASK 0x00000001

//-----------------------------------
#define CFG_APB_GPIO_CFG_ADDR 0x000c
#define GPIO_ENA_CFG_OFFSET 0
#define GPIO_ENA_CFG_MASK 0x000001FF

//-----------------------------------
#define CFG_APB_GLB_CTRL_ADDR 0x0010
#define GLB_CTRL0_OFFSET 0
#define GLB_CTRL0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_APB_UART_LR_ADDR 0x0014
#define PUART3_FIFO_LR_OFFSET 3
#define PUART3_FIFO_LR_MASK 0x00000008
#define PUART2_FIFO_LR_OFFSET 2
#define PUART2_FIFO_LR_MASK 0x00000004
#define PUART1_FIFO_LR_OFFSET 1
#define PUART1_FIFO_LR_MASK 0x00000002
#define PUART0_FIFO_LR_OFFSET 0
#define PUART0_FIFO_LR_MASK 0x00000001

//-----------------------------------
#define CFG_APB_GLB_GEN1_ADDR 0x001c
#define LEDC_EB_OFFSET 9
#define LEDC_EB_MASK 0x00000200
#define I2C1_EB_OFFSET 8
#define I2C1_EB_MASK 0x00000100
#define I2C0_EB_OFFSET 7
#define I2C0_EB_MASK 0x00000080
#define SIG_PWM3_EB_OFFSET 6
#define SIG_PWM3_EB_MASK 0x00000040
#define SIG_PWM2_EB_OFFSET 5
#define SIG_PWM2_EB_MASK 0x00000020
#define SIG_PWM1_EB_OFFSET 4
#define SIG_PWM1_EB_MASK 0x00000010
#define SIG_PWM0_EB_OFFSET 3
#define SIG_PWM0_EB_MASK 0x00000008
#define GMTX_EB_OFFSET 2
#define GMTX_EB_MASK 0x00000004
#define PWM2_EB_OFFSET 1
#define PWM2_EB_MASK 0x00000002
#define PWM1_EB_OFFSET 0
#define PWM1_EB_MASK 0x00000001

//-----------------------------------
#define CFG_APB_GLB_GRST1_ADDR 0x0020
#define LEDC_SOFT_RST_OFFSET 9
#define LEDC_SOFT_RST_MASK 0x00000200
#define I2C1_SOFT_RST_OFFSET 8
#define I2C1_SOFT_RST_MASK 0x00000100
#define I2C0_SOFT_RST_OFFSET 7
#define I2C0_SOFT_RST_MASK 0x00000080
#define SIG_PWM3_SOFT_RST_OFFSET 6
#define SIG_PWM3_SOFT_RST_MASK 0x00000040
#define SIG_PWM2_SOFT_RST_OFFSET 5
#define SIG_PWM2_SOFT_RST_MASK 0x00000020
#define SIG_PWM1_SOFT_RST_OFFSET 4
#define SIG_PWM1_SOFT_RST_MASK 0x00000010
#define SIG_PWM0_SOFT_RST_OFFSET 3
#define SIG_PWM0_SOFT_RST_MASK 0x00000008
#define GMTX_SOFT_RST_OFFSET 2
#define GMTX_SOFT_RST_MASK 0x00000004
#define PWM2_SOFT_RST_OFFSET 1
#define PWM2_SOFT_RST_MASK 0x00000002
#define PWM1_SOFT_RST_OFFSET 0
#define PWM1_SOFT_RST_MASK 0x00000001

//-----------------------------------
#define CFG_APB_UART_CFG_ADDR 0x0024
#define UART3_RXD_FROM_ANA_OFFSET 11
#define UART3_RXD_FROM_ANA_MASK 0x00000800
#define UART2_RXD_FROM_ANA_OFFSET 10
#define UART2_RXD_FROM_ANA_MASK 0x00000400
#define UART1_RXD_FROM_ANA_OFFSET 9
#define UART1_RXD_FROM_ANA_MASK 0x00000200
#define UART0_RXD_FROM_ANA_OFFSET 8
#define UART0_RXD_FROM_ANA_MASK 0x00000100
#define CLK_38KHZ_ENA_OFFSET 4
#define CLK_38KHZ_ENA_MASK 0x00000010
#define UART3_IRDA_MODE_OFFSET 3
#define UART3_IRDA_MODE_MASK 0x00000008
#define UART2_IRDA_MODE_OFFSET 2
#define UART2_IRDA_MODE_MASK 0x00000004
#define UART1_IRDA_MODE_OFFSET 1
#define UART1_IRDA_MODE_MASK 0x00000002
#define UART0_IRDA_MODE_OFFSET 0
#define UART0_IRDA_MODE_MASK 0x00000001

//-----------------------------------
#define CFG_APB_ANA_CFG0_ADDR 0x0028
#define ANA_AFE_MODE_OFFSET 14
#define ANA_AFE_MODE_MASK 0x00004000
#define RX_GLAN_SEL_OFFSET 13
#define RX_GLAN_SEL_MASK 0x00002000
#define DAC_DATA_SEL_OFFSET 12
#define DAC_DATA_SEL_MASK 0x00001000
#define ANA_I2C_SOFT_RST_OFFSET 11
#define ANA_I2C_SOFT_RST_MASK 0x00000800
#define DCDC_DIS_LMTCUR_OFFSET 10
#define DCDC_DIS_LMTCUR_MASK 0x00000400
#define DCDC_EN_PFM_OFFSET 9
#define DCDC_EN_PFM_MASK 0x00000200
#define DCDC_LMTCUR_250M_OFFSET 8
#define DCDC_LMTCUR_250M_MASK 0x00000100
#define SELB_1P8_OFFSET 5
#define SELB_1P8_MASK 0x00000020
#define BURN_IN_OFFSET 4
#define BURN_IN_MASK 0x00000010
#define ANA_DEBUG_SEL_OFFSET 0
#define ANA_DEBUG_SEL_MASK 0x0000000F

//-----------------------------------
#define CFG_SIG_PWM0_CFG_ADDR 0x0030
#define SIG_PWM0_PRESCALAR_OFFSET 8
#define SIG_PWM0_PRESCALAR_MASK 0x0000FF00
#define SIG_PWM0_TARGET_OFFSET 0
#define SIG_PWM0_TARGET_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG_PWM1_CFG_ADDR 0x0034
#define SIG_PWM1_PRESCALAR_OFFSET 8
#define SIG_PWM1_PRESCALAR_MASK 0x0000FF00
#define SIG_PWM1_TARGET_OFFSET 0
#define SIG_PWM1_TARGET_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG_PWM2_CFG_ADDR 0x0038
#define SIG_PWM2_PRESCALAR_OFFSET 8
#define SIG_PWM2_PRESCALAR_MASK 0x0000FF00
#define SIG_PWM2_TARGET_OFFSET 0
#define SIG_PWM2_TARGET_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG_PWM3_CFG_ADDR 0x003c
#define SIG_PWM3_PRESCALAR_OFFSET 8
#define SIG_PWM3_PRESCALAR_MASK 0x0000FF00
#define SIG_PWM3_TARGET_OFFSET 0
#define SIG_PWM3_TARGET_MASK 0x000000FF

//-----------------------------------
#define CFG_APB_SADC_CFG2_ADDR 0x0040
#define SADC_SEL_FAST_OFFSET 0
#define SADC_SEL_FAST_MASK 0x00000001

//-----------------------------------
#define CFG_FTST_CFG_ADDR 0x0044
#define SEC_DMA_FORCE_ON_OFFSET 11
#define SEC_DMA_FORCE_ON_MASK 0x00000800
#define FDMA_AHB_FSM_OFFSET 8
#define FDMA_AHB_FSM_MASK 0x00000700
#define FDMA_IO_MODE_OFFSET 4
#define FDMA_IO_MODE_MASK 0x00000070
#define FUNCTST_FORCE_EB_OFFSET 0
#define FUNCTST_FORCE_EB_MASK 0x00000001

//-----------------------------------
#define CFG_EFUSE_CFG0_ADDR 0x0050
#define EFUSE_RDATA0_OFFSET 0
#define EFUSE_RDATA0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG1_ADDR 0x0054
#define EFUSE_RDATA1_OFFSET 0
#define EFUSE_RDATA1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG2_ADDR 0x0058
#define EFUSE_RDATA2_OFFSET 0
#define EFUSE_RDATA2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG3_ADDR 0x005c
#define EFUSE_RDATA3_OFFSET 0
#define EFUSE_RDATA3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG4_ADDR 0x0060
#define EFUSE_RDATA4_OFFSET 0
#define EFUSE_RDATA4_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG5_ADDR 0x0064
#define EFUSE_RDATA5_OFFSET 0
#define EFUSE_RDATA5_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG6_ADDR 0x0068
#define EFUSE_RDATA6_OFFSET 0
#define EFUSE_RDATA6_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG7_ADDR 0x006c
#define EFUSE_RDATA7_OFFSET 0
#define EFUSE_RDATA7_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG8_ADDR 0x0070
#define EFUSE_RDATA8_OFFSET 0
#define EFUSE_RDATA8_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG9_ADDR 0x0074
#define EFUSE_RDATA9_OFFSET 0
#define EFUSE_RDATA9_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG10_ADDR 0x0078
#define EFUSE_RDATA10_OFFSET 0
#define EFUSE_RDATA10_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG11_ADDR 0x007c
#define EFUSE_RDATA11_OFFSET 0
#define EFUSE_RDATA11_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG12_ADDR 0x0080
#define EFUSE_RDATA12_OFFSET 0
#define EFUSE_RDATA12_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG13_ADDR 0x0084
#define EFUSE_RDATA13_OFFSET 0
#define EFUSE_RDATA13_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG14_ADDR 0x0088
#define EFUSE_RDATA14_OFFSET 0
#define EFUSE_RDATA14_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG15_ADDR 0x008c
#define EFUSE_RDATA15_OFFSET 0
#define EFUSE_RDATA15_MASK 0xFFFFFFFF

//HW module read/write macro
#define APB_GLB_READ_REG(addr) SOC_READ_REG(APB_GLB_BASEADDR + addr)
#define APB_GLB_WRITE_REG(addr,value) SOC_WRITE_REG(APB_GLB_BASEADDR + addr,value)