kunlun/inc/hw/reg/riscv/15/phy_tx_reg.h

//-----------------------------------
#define CFG_BB_TEST_ONLY_ADDR 0x0000

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_ADDR 0x0004
#define SW_PWR_BACKOFF_16QAM_OFFSET 16
#define SW_PWR_BACKOFF_16QAM_MASK 0x000F0000
#define SW_PWR_BACKOFF_QPSK_OFFSET 12
#define SW_PWR_BACKOFF_QPSK_MASK 0x0000F000

//-----------------------------------
#define CFG_BB_TX_IFFT_CTRL_ADDR 0x0008
#define SW_IFFT_TD_BIT_SEL_OFFSET 0
#define SW_IFFT_TD_BIT_SEL_MASK 0x00000007

//-----------------------------------
#define CFG_BB_TX_TURBO_SET_ADDR 0x000C
#define SW_TX_SCRAMBLE_BASED_PPDU_OFFSET 2
#define SW_TX_SCRAMBLE_BASED_PPDU_MASK 0x00000004
#define SW_TX_SCRAMBLE_RESET_MODE_OFFSET 1
#define SW_TX_SCRAMBLE_RESET_MODE_MASK 0x00000002
#define SW_TX_SCRAMBLE_MODE_OFFSET 0
#define SW_TX_SCRAMBLE_MODE_MASK 0x00000001

//-----------------------------------
#define CFG_BB_TX_NSG_PREAM_NUM0_ADDR 0x0010
#define SW_NSG_BMCS_BAND2_PREAM_NUM_OFFSET 16
#define SW_NSG_BMCS_BAND2_PREAM_NUM_MASK 0x00FF0000
#define SW_NSG_BMCS_BAND1_PREAM_NUM_OFFSET 8
#define SW_NSG_BMCS_BAND1_PREAM_NUM_MASK 0x0000FF00
#define SW_NSG_BMCS_BAND0_PREAM_NUM_OFFSET 0
#define SW_NSG_BMCS_BAND0_PREAM_NUM_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_TX_NSG_PREAM_NUM1_ADDR 0x0014
#define SW_NSG_EMCS_BAND2_PREAM_NUM_OFFSET 16
#define SW_NSG_EMCS_BAND2_PREAM_NUM_MASK 0x00FF0000
#define SW_NSG_EMCS_BAND1_PREAM_NUM_OFFSET 8
#define SW_NSG_EMCS_BAND1_PREAM_NUM_MASK 0x0000FF00
#define SW_NSG_EMCS_BAND0_PREAM_NUM_OFFSET 0
#define SW_NSG_EMCS_BAND0_PREAM_NUM_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_RATE0_BAND0_ADDR 0x0020
#define SW_RATE0_BAND0_DB_UP_AMP_PARA_INT_OFFSET 2
#define SW_RATE0_BAND0_DB_UP_AMP_PARA_INT_MASK 0x000001FC
#define SW_RATE0_BAND0_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_RATE0_BAND0_DB_UP_AMP_PARA_FRAC_MASK 0x00000003

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_RATE0_BAND1_ADDR 0x0024
#define SW_RATE0_BAND1_DB_UP_AMP_PARA_INT_OFFSET 2
#define SW_RATE0_BAND1_DB_UP_AMP_PARA_INT_MASK 0x000001FC
#define SW_RATE0_BAND1_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_RATE0_BAND1_DB_UP_AMP_PARA_FRAC_MASK 0x00000003

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_RATE0_BAND2_ADDR 0x0028
#define SW_RATE0_BAND2_DB_UP_AMP_PARA_INT_OFFSET 2
#define SW_RATE0_BAND2_DB_UP_AMP_PARA_INT_MASK 0x000001FC
#define SW_RATE0_BAND2_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_RATE0_BAND2_DB_UP_AMP_PARA_FRAC_MASK 0x00000003

//-----------------------------------
#define CFG_BB_TX_DLY_ADDR 0x002C
#define SW_TX_DLY_SG_OFFSET 16
#define SW_TX_DLY_SG_MASK 0x0FFF0000
#define SW_TX_DLY_GP_OFFSET 0
#define SW_TX_DLY_GP_MASK 0x00000FFF

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_RATE1_BAND0_ADDR 0x0030
#define SW_RATE1_BAND0_DB_UP_AMP_PARA_INT_OFFSET 2
#define SW_RATE1_BAND0_DB_UP_AMP_PARA_INT_MASK 0x000001FC
#define SW_RATE1_BAND0_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_RATE1_BAND0_DB_UP_AMP_PARA_FRAC_MASK 0x00000003

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_RATE1_BAND1_ADDR 0x0034
#define SW_RATE1_BAND1_DB_UP_AMP_PARA_INT_OFFSET 2
#define SW_RATE1_BAND1_DB_UP_AMP_PARA_INT_MASK 0x000001FC
#define SW_RATE1_BAND1_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_RATE1_BAND1_DB_UP_AMP_PARA_FRAC_MASK 0x00000003

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_RATE1_BAND2_ADDR 0x0038
#define SW_RATE1_BAND2_DB_UP_AMP_PARA_INT_OFFSET 2
#define SW_RATE1_BAND2_DB_UP_AMP_PARA_INT_MASK 0x000001FC
#define SW_RATE1_BAND2_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_RATE1_BAND2_DB_UP_AMP_PARA_FRAC_MASK 0x00000003

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_SHORT_PREAM_ADDR 0x003c
#define SW_SHORT_PREAM_DB_UP_AMP_PARA_INT_OFFSET 2
#define SW_SHORT_PREAM_DB_UP_AMP_PARA_INT_MASK 0x000001FC
#define SW_SHORT_PREAM_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_SHORT_PREAM_DB_UP_AMP_PARA_FRAC_MASK 0x00000003

//-----------------------------------
#define CFG_BB_PHY_TX_SPARE0_ADDR 0x0040
#define SW_PHY_TX_SPARE0_OFFSET 0
#define SW_PHY_TX_SPARE0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_PHY_TX_SPARE1_ADDR 0x0044
#define SW_PHY_TX_SPARE1_OFFSET 0
#define SW_PHY_TX_SPARE1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_PHY_TX_SPARE2_ADDR 0x0048
#define SW_PHY_TX_SPARE2_OFFSET 0
#define SW_PHY_TX_SPARE2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_PHY_TX_SPARE3_ADDR 0x004c
#define SW_PHY_TX_SPARE3_OFFSET 0
#define SW_PHY_TX_SPARE3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_NSG_PRE_CAL_ADDR 0x0050
#define SW_MINUS_VALUE_OFFSET 1
#define SW_MINUS_VALUE_MASK 0x0000000E
#define SW_FORBID_ONCE_NSG_ROBO_OFFSET 0
#define SW_FORBID_ONCE_NSG_ROBO_MASK 0x00000001

//-----------------------------------
#define CFG_BB_DIVER_ADD_BAND_INTERVAL_ADDR 0x0054
#define SW_DIVERSITY_ADD_BAND_INTERVAL_OFFSET 0
#define SW_DIVERSITY_ADD_BAND_INTERVAL_MASK 0x00000001

//HW module read/write macro
#define PHY_TX_READ_REG(addr) SOC_READ_REG(PHY_TX_BASEADDR + addr)
#define PHY_TX_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_TX_BASEADDR + addr,value)