kunlun/inc/hw/reg/riscv2/15/dma_reg.h

//-----------------------------------
#define CFG_PDMA_CONF0_ADDR 0x0
#define REG_DEV_RX_BRK_EOF_EN_OFFSET 18
#define REG_DEV_RX_BRK_EOF_EN_MASK 0x00040000
#define REG_CLK_EN_OFFSET 17
#define REG_CLK_EN_MASK 0x00020000
#define REG_MEM_TRANS_EN_OFFSET 15
#define REG_MEM_TRANS_EN_MASK 0x00008000
#define REG_OUT_DATA_BURST_EN_OFFSET 14
#define REG_OUT_DATA_BURST_EN_MASK 0x00004000
#define REG_INDSCR_BURST_EN_OFFSET 13
#define REG_INDSCR_BURST_EN_MASK 0x00002000
#define REG_OUTDSCR_BURST_EN_OFFSET 12
#define REG_OUTDSCR_BURST_EN_MASK 0x00001000
#define REG_DEV2_CE_OFFSET 11
#define REG_DEV2_CE_MASK 0x00000800
#define REG_DEV1_CE_OFFSET 10
#define REG_DEV1_CE_MASK 0x00000400
#define REG_DEV0_CE_OFFSET 9
#define REG_DEV0_CE_MASK 0x00000200
#define REG_OUT_EOF_MODE_OFFSET 8
#define REG_OUT_EOF_MODE_MASK 0x00000100
#define REG_LOOP_BACK_MODE_OFFSET 7
#define REG_LOOP_BACK_MODE_MASK 0x00000080
#define REG_OUT_AUTO_WRBACK_OFFSET 6
#define REG_OUT_AUTO_WRBACK_MASK 0x00000040
#define REG_OUT_LOOP_TEST_OFFSET 5
#define REG_OUT_LOOP_TEST_MASK 0x00000020
#define REG_IN_LOOP_TEST_OFFSET 4
#define REG_IN_LOOP_TEST_MASK 0x00000010
#define REG_AHBM_RST_OFFSET 3
#define REG_AHBM_RST_MASK 0x00000008
#define REG_AHBM_FIFO_RST_OFFSET 2
#define REG_AHBM_FIFO_RST_MASK 0x00000004
#define REG_OUT_RST_OFFSET 1
#define REG_OUT_RST_MASK 0x00000002
#define REG_IN_RST_OFFSET 0
#define REG_IN_RST_MASK 0x00000001

//-----------------------------------
#define CFG_PDMA_INT_RAW_ADDR 0x4
#define DMA_INFIFO_FULL_WM_INT_RAW_OFFSET 9
#define DMA_INFIFO_FULL_WM_INT_RAW_MASK 0x00000200
#define DMA_OUT_TOTAL_EOF_INT_RAW_OFFSET 8
#define DMA_OUT_TOTAL_EOF_INT_RAW_MASK 0x00000100
#define DMA_IN_DSCR_EMPTY_INT_RAW_OFFSET 7
#define DMA_IN_DSCR_EMPTY_INT_RAW_MASK 0x00000080
#define DMA_OUT_DSCR_ERR_INT_RAW_OFFSET 6
#define DMA_OUT_DSCR_ERR_INT_RAW_MASK 0x00000040
#define DMA_IN_DSCR_ERR_INT_RAW_OFFSET 5
#define DMA_IN_DSCR_ERR_INT_RAW_MASK 0x00000020
#define DMA_OUT_EOF_INT_RAW_OFFSET 4
#define DMA_OUT_EOF_INT_RAW_MASK 0x00000010
#define DMA_OUT_DONE_INT_RAW_OFFSET 3
#define DMA_OUT_DONE_INT_RAW_MASK 0x00000008
#define DMA_IN_ERR_EOF_INT_RAW_OFFSET 2
#define DMA_IN_ERR_EOF_INT_RAW_MASK 0x00000004
#define DMA_IN_SUC_EOF_INT_RAW_OFFSET 1
#define DMA_IN_SUC_EOF_INT_RAW_MASK 0x00000002
#define DMA_IN_DONE_INT_RAW_OFFSET 0
#define DMA_IN_DONE_INT_RAW_MASK 0x00000001

//-----------------------------------
#define CFG_PDMA_INT_ST_ADDR 0x8
#define DMA_INFIFO_FULL_WM_INT_ST_OFFSET 9
#define DMA_INFIFO_FULL_WM_INT_ST_MASK 0x00000200
#define DMA_OUT_TOTAL_EOF_INT_ST_OFFSET 8
#define DMA_OUT_TOTAL_EOF_INT_ST_MASK 0x00000100
#define DMA_IN_DSCR_EMPTY_INT_ST_OFFSET 7
#define DMA_IN_DSCR_EMPTY_INT_ST_MASK 0x00000080
#define DMA_OUT_DSCR_ERR_INT_ST_OFFSET 6
#define DMA_OUT_DSCR_ERR_INT_ST_MASK 0x00000040
#define DMA_IN_DSCR_ERR_INT_ST_OFFSET 5
#define DMA_IN_DSCR_ERR_INT_ST_MASK 0x00000020
#define DMA_OUT_EOF_INT_ST_OFFSET 4
#define DMA_OUT_EOF_INT_ST_MASK 0x00000010
#define DMA_OUT_DONE_INT_ST_OFFSET 3
#define DMA_OUT_DONE_INT_ST_MASK 0x00000008
#define DMA_IN_ERR_EOF_INT_ST_OFFSET 2
#define DMA_IN_ERR_EOF_INT_ST_MASK 0x00000004
#define DMA_IN_SUC_EOF_INT_ST_OFFSET 1
#define DMA_IN_SUC_EOF_INT_ST_MASK 0x00000002
#define DMA_IN_DONE_INT_ST_OFFSET 0
#define DMA_IN_DONE_INT_ST_MASK 0x00000001

//-----------------------------------
#define CFG_PDMA_INT_ENA_ADDR 0xC
#define DMA_INFIFO_FULL_WM_INT_ENA_OFFSET 9
#define DMA_INFIFO_FULL_WM_INT_ENA_MASK 0x00000200
#define DMA_OUT_TOTAL_EOF_INT_ENA_OFFSET 8
#define DMA_OUT_TOTAL_EOF_INT_ENA_MASK 0x00000100
#define DMA_IN_DSCR_EMPTY_INT_ENA_OFFSET 7
#define DMA_IN_DSCR_EMPTY_INT_ENA_MASK 0x00000080
#define DMA_OUT_DSCR_ERR_INT_ENA_OFFSET 6
#define DMA_OUT_DSCR_ERR_INT_ENA_MASK 0x00000040
#define DMA_IN_DSCR_ERR_INT_ENA_OFFSET 5
#define DMA_IN_DSCR_ERR_INT_ENA_MASK 0x00000020
#define DMA_OUT_EOF_INT_ENA_OFFSET 4
#define DMA_OUT_EOF_INT_ENA_MASK 0x00000010
#define DMA_OUT_DONE_INT_ENA_OFFSET 3
#define DMA_OUT_DONE_INT_ENA_MASK 0x00000008
#define DMA_IN_ERR_EOF_INT_ENA_OFFSET 2
#define DMA_IN_ERR_EOF_INT_ENA_MASK 0x00000004
#define DMA_IN_SUC_EOF_INT_ENA_OFFSET 1
#define DMA_IN_SUC_EOF_INT_ENA_MASK 0x00000002
#define DMA_IN_DONE_INT_ENA_OFFSET 0
#define DMA_IN_DONE_INT_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_PDMA_INT_CLR_ADDR 0x10
#define REG_DMA_INFIFO_FULL_WM_INT_CLR_OFFSET 9
#define REG_DMA_INFIFO_FULL_WM_INT_CLR_MASK 0x00000200
#define REG_OUT_TOTAL_EOF_INT_CLR_OFFSET 8
#define REG_OUT_TOTAL_EOF_INT_CLR_MASK 0x00000100
#define REG_IN_DSCR_EMPTY_INT_CLR_OFFSET 7
#define REG_IN_DSCR_EMPTY_INT_CLR_MASK 0x00000080
#define REG_OUT_DSCR_ERR_INT_CLR_OFFSET 6
#define REG_OUT_DSCR_ERR_INT_CLR_MASK 0x00000040
#define REG_IN_DSCR_ERR_INT_CLR_OFFSET 5
#define REG_IN_DSCR_ERR_INT_CLR_MASK 0x00000020
#define REG_OUT_EOF_INT_CLR_OFFSET 4
#define REG_OUT_EOF_INT_CLR_MASK 0x00000010
#define REG_OUT_DONE_INT_CLR_OFFSET 3
#define REG_OUT_DONE_INT_CLR_MASK 0x00000008
#define REG_IN_ERR_EOF_INT_CLR_OFFSET 2
#define REG_IN_ERR_EOF_INT_CLR_MASK 0x00000004
#define REG_IN_SUC_EOF_INT_CLR_OFFSET 1
#define REG_IN_SUC_EOF_INT_CLR_MASK 0x00000002
#define REG_IN_DONE_INT_CLR_OFFSET 0
#define REG_IN_DONE_INT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_PDMA_OUT_STATUS_ADDR 0x14
#define OUT_EMPTY_OFFSET 1
#define OUT_EMPTY_MASK 0x00000002
#define OUT_FULL_OFFSET 0
#define OUT_FULL_MASK 0x00000001

//-----------------------------------
#define CFG_PDMA_OUT_PUSH_ADDR 0x18
#define REG_OUTFIFO_PUSH_OFFSET 16
#define REG_OUTFIFO_PUSH_MASK 0x00010000
#define REG_OUTFIFO_WDATA_OFFSET 0
#define REG_OUTFIFO_WDATA_MASK 0x000001FF

//-----------------------------------
#define CFG_PDMA_IN_STATUS_ADDR 0x1C
#define DMA_RX_ERR_CAUSE_OFFSET 4
#define DMA_RX_ERR_CAUSE_MASK 0x00000070
#define IN_EMPTY_OFFSET 1
#define IN_EMPTY_MASK 0x00000002
#define IN_FULL_OFFSET 0
#define IN_FULL_MASK 0x00000001

//-----------------------------------
#define CFG_PDMA_IN_POP_ADDR 0x20
#define REG_INFIFO_POP_OFFSET 16
#define REG_INFIFO_POP_MASK 0x00010000
#define REG_INFIFO_RDATA_OFFSET 0
#define REG_INFIFO_RDATA_MASK 0x00000FFF

//-----------------------------------
#define CFG_PDMA_OUT_LINK_ADDR 0x24
#define REG_OUTLINK_RESTART_OFFSET 30
#define REG_OUTLINK_RESTART_MASK 0x40000000
#define REG_OUTLINK_START_OFFSET 29
#define REG_OUTLINK_START_MASK 0x20000000
#define REG_OUTLINK_STOP_OFFSET 28
#define REG_OUTLINK_STOP_MASK 0x10000000

//-----------------------------------
#define CFG_PDMA_IN_LINK_ADDR 0x28
#define REG_INLINK_AUTO_RET_OFFSET 31
#define REG_INLINK_AUTO_RET_MASK 0x80000000
#define REG_INLINK_RESTART_OFFSET 30
#define REG_INLINK_RESTART_MASK 0x40000000
#define REG_INLINK_START_OFFSET 29
#define REG_INLINK_START_MASK 0x20000000
#define REG_INLINK_STOP_OFFSET 28
#define REG_INLINK_STOP_MASK 0x10000000

//-----------------------------------
#define CFG_PDMA_CONF1_ADDR 0x2C
#define REG_DMA_INFIFO_FULL_THRS_OFFSET 8
#define REG_DMA_INFIFO_FULL_THRS_MASK 0x000FFF00
#define REG_CHECK_OWNER_OFFSET 1
#define REG_CHECK_OWNER_MASK 0x00000002
#define REG_CRC_DISABLE_OFFSET 0
#define REG_CRC_DISABLE_MASK 0x00000001

//-----------------------------------
#define CFG_PDMA_STATE0_ADDR 0x30
#define DMA_STATE0_OFFSET 0
#define DMA_STATE0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_STATE1_ADDR 0x34
#define DMA_STATE1_OFFSET 0
#define DMA_STATE1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_OUT_EOF_DES_ADDR_ADDR 0x38
#define OUT_EOF_DES_ADDR_OFFSET 0
#define OUT_EOF_DES_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_IN_SUC_EOF_DES_ADDR_ADDR 0x3C
#define IN_SUC_EOF_DES_ADDR_OFFSET 0
#define IN_SUC_EOF_DES_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_IN_ERR_EOF_DES_ADDR_ADDR 0x40
#define IN_ERR_EOF_DES_ADDR_OFFSET 0
#define IN_ERR_EOF_DES_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_OUT_EOF_BFR_DES_ADDR_ADDR 0x44
#define OUT_EOF_BFR_DES_ADDR_OFFSET 0
#define OUT_EOF_BFR_DES_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_AHB_TEST_ADDR 0x48
#define REG_AHB_TESTADDR_OFFSET 4
#define REG_AHB_TESTADDR_MASK 0x00000030
#define REG_AHB_TESTMODE_OFFSET 0
#define REG_AHB_TESTMODE_MASK 0x00000007

//-----------------------------------
#define CFG_PDMA_IN_DSCR_ADDR 0x4C
#define INLINK_DSCR_OFFSET 0
#define INLINK_DSCR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_IN_DSCR_BF0_ADDR 0x50
#define INLINK_DSCR_BF0_OFFSET 0
#define INLINK_DSCR_BF0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_IN_DSCR_BF1_ADDR 0x54
#define INLINK_DSCR_BF1_OFFSET 0
#define INLINK_DSCR_BF1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_OUT_DSCR_ADDR 0x58
#define OUTLINK_DSCR_OFFSET 0
#define OUTLINK_DSCR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_OUT_DSCR_BF0_ADDR 0x5C
#define OUTLINK_DSCR_BF0_OFFSET 0
#define OUTLINK_DSCR_BF0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_OUT_DSCR_BF1_ADDR 0x60
#define OUTLINK_DSCR_BF1_OFFSET 0
#define OUTLINK_DSCR_BF1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_CRC_CFG0_ADDR 0x64
#define CRC_OUT_DONE_OFFSET 9
#define CRC_OUT_DONE_MASK 0x00000200
#define CRC_ENA_OFFSET 8
#define CRC_ENA_MASK 0x00000100
#define CRC_MODE_OFFSET 0
#define CRC_MODE_MASK 0x000000FF

//-----------------------------------
#define CFG_PDMA_CRC_CFG1_ADDR 0x68
#define CRC_OUT_OFFSET 0
#define CRC_OUT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_CRC_OUT_ADDR 0x6C
#define CRC_POLYNOMIAL_OFFSET 0
#define CRC_POLYNOMIAL_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_LINK_ST_ADDR 0x70
#define DMA_OUTLINK_PARK_OFFSET 1
#define DMA_OUTLINK_PARK_MASK 0x00000002
#define DMA_INLINK_PARK_OFFSET 0
#define DMA_INLINK_PARK_MASK 0x00000001

//-----------------------------------
#define CFG_PDMA_CRC_INI_ADDR 0x74
#define CRC_INIT_OFFSET 0
#define CRC_INIT_MASK 0x00000001

//-----------------------------------
#define CFG_PDMA_CKSUM_INI_ADDR 0x78
#define CKSUM_INIT_OFFSET 0
#define CKSUM_INIT_MASK 0x00000001

//-----------------------------------
#define CFG_PDMA_CKSUM_CFG_ADDR 0x7C
#define CKSUM_OUT_OFFSET 16
#define CKSUM_OUT_MASK 0xFFFF0000
#define CKSUM_ENA_OFFSET 0
#define CKSUM_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_PDMA_OUT_LINK_ADDR_ADDR 0x80
#define REG_OUTLINK_ADDR_OFFSET 0
#define REG_OUTLINK_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_IN_LINK_ADDR_ADDR 0x84
#define REG_INLINK_ADDR_OFFSET 0
#define REG_INLINK_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_FP_CFG0_ADDR 0x88
#define DMA_FP_ENA_OFFSET 17
#define DMA_FP_ENA_MASK 0x00020000
#define DMA_FP_INIT_OFFSET 16
#define DMA_FP_INIT_MASK 0x00010000
#define DMA_FP_OP_TYPE_OFFSET 12
#define DMA_FP_OP_TYPE_MASK 0x0000F000
#define DMA_FP_SHIFT_OFFSET 4
#define DMA_FP_SHIFT_MASK 0x000003F0
#define DMA_FP_BIG_ENDIAN_OFFSET 3
#define DMA_FP_BIG_ENDIAN_MASK 0x00000008
#define DMA_FP_RND_OFFSET 0
#define DMA_FP_RND_MASK 0x00000007

//-----------------------------------
#define CFG_PDMA_FP_MAX_MIN_ADDR 0x8C
#define DMA_FP_MAX_MIN_OFFSET 0
#define DMA_FP_MAX_MIN_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PDMA_FP_SUM_ADDR 0x90
#define DMA_FP_SUM_OFFSET 0
#define DMA_FP_SUM_MASK 0xFFFFFFFF

//HW module read/write macro
#define DMA0_READ_REG(addr) SOC_READ_REG(SW_DMA_REG0_BASEADDR + addr)
#define DMA0_WRITE_REG(addr,value) SOC_WRITE_REG(SW_DMA_REG0_BASEADDR + addr,value)
#define DMA1_READ_REG(addr) SOC_READ_REG(SW_DMA_REG1_BASEADDR + addr)
#define DMA1_WRITE_REG(addr,value) SOC_WRITE_REG(SW_DMA_REG1_BASEADDR + addr,value)