451 lines
12 KiB
C
451 lines
12 KiB
C
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/****************************************************************************
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*
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* Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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*
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* This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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* be copied by any method or incorporated into another program without
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* the express written consent of Aerospace C.Power. This Information or any portion
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* thereof remains the property of Aerospace C.Power. The Information contained herein
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* is believed to be accurate and Aerospace C.Power assumes no responsibility or
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* liability for its use in any way and conveys no license or title under
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* any patent or copyright and makes no representation or warranty that this
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* Information is free from patent or copyright infringement.
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*
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* ****************************************************************************/
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/* os shim includes */
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#include "os_types.h"
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#include "os_task.h"
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#include "os_utils.h"
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/* common includes */
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#include "iot_io.h"
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#include "iot_bitops.h"
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#include "iot_pkt_api.h"
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#include "iot_ipc.h"
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#include "iot_plc_lib.h"
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#include "iot_dbglog_api.h"
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#include "iot_config.h"
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/* driver includes */
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#include "iot_clock.h"
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#include "iot_uart.h"
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#include "iot_led.h"
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/* cli includes */
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#include "iot_cli.h"
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#include "iot_uart_h.h"
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/* debug includes*/
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#include "dbg_io.h"
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#include "gpio_mtx.h"
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#include "gpio_mtx_reg.h"
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#include "apb_glb_reg.h"
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#include "apb_dma.h"
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#include "apb.h"
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#include "ap_clk_core_rf.h"
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#include "ahb_rf.h"
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#include "phy_ana_glb.h"
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#include "phy_bb.h"
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#include "granite_reg.h"
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#include "phy_dfe_reg.h"
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#include "hw_reg_api.h"
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#include "pin_rf.h"
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#include "ana.h"
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#include "dma_hw.h"
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#include "i2s_reg.h"
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#include "sadc_reg.h"
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#include "sadc.h"
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#include "sadc_hw.h"
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#include "i2s_reg.h"
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#include "i2s.h"
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#include "dma_sw.h"
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#include "hw_sadc.h"
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#include "hal_sadc.h"
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#include "iot_adc_api.h"
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unsigned char buf[4][DMA_BUF_SIZE];
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int phas_int_buf[4][1536]; //[1024];
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desc_t descLs[4];
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desc_t *pdesc_sadc_pool;
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volatile int recieved_done = 1;
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void sadc_i2s_data_buf_diff(volatile unsigned char in_buf[], int raw_buf_size, int *out_buf[])
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{
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int i = 0;
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static int cnt_int[4] = {0, 0, 0, 0};
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int tmp = 0;
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for (i = 0; i < raw_buf_size; i = i + 4)
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{
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if (in_buf[i + 3] & 0x80)
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{
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tmp = ((in_buf[i + 3] << 8) | in_buf[i + 2]) & 0x7FFF;
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if (tmp & (1 << 14))
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{
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tmp |= (1 << 15);
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}
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out_buf[3][cnt_int[3]++] = tmp;
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tmp = (in_buf[i + 1] << 8) | in_buf[i];
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out_buf[2][cnt_int[2]++] = tmp;
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}
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else
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{
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tmp = (in_buf[i + 3] << 8) | in_buf[i + 2];
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if (tmp & (1 << 14))
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{
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tmp |= (1 << 15);
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}
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out_buf[1][cnt_int[1]++] = tmp;
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tmp = (in_buf[i + 1] << 8) | in_buf[i];
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out_buf[0][cnt_int[0]++] = tmp;
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}
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}
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for(i=0; i<4; i++)
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{
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if (cnt_int[i]>=1024)
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{
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cnt_int[i] = 0;
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}
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}
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}
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void sadc_dma_data_buf_diff(volatile unsigned char in_buf[], int raw_buf_size, int *out_buf[])
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{
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int i = 0;
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static int cnt[4] = {0, 0, 0, 0};
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unsigned char phase = 0;
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int tmp = 0;
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for (i = 0; i < raw_buf_size;)
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{
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phase = (in_buf[i + 1] & 0xC0) >> 6;
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tmp = ((in_buf[i + 1] << 8) | in_buf[i]) & 0x3FFF;
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if (tmp & 0x2000)
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{
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tmp |= 0xC000;
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}
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out_buf[phase][cnt[phase]++] = tmp;
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i = i + 2;
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}
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for(i=0; i<4; i++)
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{
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if (cnt[i]>=1024)
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{
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cnt[i] = 0;
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}
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}
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}
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void sadc_dma__handler(int vector, int status)
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{
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desc_t *pdesc1;
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desc_t *pdesc2;
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// int i = 0;
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// Recycle out descroptors
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if (status & DMA_INT_OUT_DONE)
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{
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pdesc1 = NULL;
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if (pdesc1)
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{
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if (pdesc_sadc_pool)
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{
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pdesc2 = pdesc_sadc_pool;
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while (pdesc2->n_ptr)
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{
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pdesc2 = pdesc2->n_ptr;
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}
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pdesc2->n_ptr = pdesc1;
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}
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else
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{
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pdesc_sadc_pool = pdesc1;
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}
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}
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}
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if (status & DMA_INT_IN_DONE)
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{
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if((0 == descLs[1].owner)
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&&(0 == descLs[1].owner)
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&&(0 == descLs[1].owner))
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recieved_done = 1;
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}
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if (status & DMA_INT_ERROR_DEFAULT)
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{
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// TODO: Error handle.
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}
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return;
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}
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void sadc_dma_config(void)
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{
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int cnt;
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dma_hw_open(DMA_DEV_I2S, (dma_int_handler)sadc_dma__handler, NULL);
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#ifdef TEST_DMA_MODE
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*(int *)0x44016000 |= 1 << 10; //enable sadc dev1
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#endif
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for (cnt = 0; cnt < DMA_BUF_SIZE; cnt++)
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{
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buf[1][cnt] = 0x0;
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}
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for (cnt = 1; cnt < 4; cnt++)
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{
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DMA_MAKE_DESC(&descLs[cnt], buf[cnt], DMA_BUF_SIZE, 0, 0, 0, 0, DESC_OWNER_DMA);
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}
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descLs[1].n_ptr = &descLs[2];
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descLs[2].n_ptr = &descLs[3];
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descLs[3].n_ptr = NULL;
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dma_hw_start_recieve(DMA_DEV_I2S, &descLs[1]);
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}
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void sadc_i2s_cfg(void)
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{
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uint32_t tmp = 0;
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tmp = I2S_READ_REG(CFG_PDM_CFG0_ADDR);
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//REG_FIELD_SET(REG_PDM_SADC_DUMP, tmp, 1); //bypass the pdm filter, ignore 8 times down-sampling
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// REG_FIELD_SET(REG_PDM_SADC_HP_BYPASS, tmp, 1); //bypass the high freqs
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I2S_WRITE_REG(CFG_PDM_CFG0_ADDR, tmp);
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tmp = AP_CLK_CORE_RF_READ_REG(CFG_CLK_IIS_CFG1_ADDR);
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REG_FIELD_SET(IIS_DIV_M, tmp, 625); //set M=0x271
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REG_FIELD_SET(IIS_DIV_N, tmp, 128); //set N=0x80
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AP_CLK_CORE_RF_WRITE_REG(CFG_CLK_IIS_CFG1_ADDR, tmp);
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// i2s_rx_eof_num_set(4096);
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i2s_rx_eof_num_set(0, 65536);
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// i2s_rx_eof_num_set(0xFFFFFFFF); //for sadc-i2s sine wave test
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i2s_pdm_slave_mod_en(0, I2S_DIR_RX, ENABLE);
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i2s_pdm_sadc_64bit_en(0, ENABLE);
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i2s_pdm_sadc_en(ENABLE);
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i2s_pdm_rx_tx_en(0, I2S_DIR_RX, ENABLE);
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i2s_rx_start(0);
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}
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void sadc_reg_cfg(void)
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{
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uint8_t reg_id = 0;
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uint8_t rodata = 0;
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uint32_t rdata = 0;
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uint32_t wdata = 0;
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uint32_t wmask = 0;
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uint32_t tmp = 0;
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uint8_t channel[4] = {11, 13, 10, 11};
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//uint8_t channel[4] = {8, 9, 12, 13}; //test single pad 0 1 4 5
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//uint8_t channel[4] = {11, 12, 13, 10}; //test single pad 0 1 4 5
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//uint8_t channel[4] = {10, 9, 12, 13};
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//uint8_t channel[4] = {14, 10, 12, 13};
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//uint8_t channel[4] = {10, 10, 12, 13};
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//uint8_t channel[4] = {15, 8, 12, 13};
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//uint8_t channel[4] = {14, 8, 12, 13};
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//uint8_t channel[4] = {9, 9, 9, 9};//SADC1
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//uint8_t channel[4] = {15, 15, 15, 15};//differential SADC0 & SADC1
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//uint8_t gain[4] = {11, 11, 11, 11};
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//uint8_t gain[4] = {15, 15, 15, 15};
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//uint8_t gain[4] = {25, 25, 25, 25};
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//uint8_t gain[4] = {25, 11, 11, 11};
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uint8_t gain[4] = {9, 9, 9, 9}; //1001 for gain2
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tmp = 0xFFFFFFFF;
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AHB_RF_WRITE_REG(CFG_AHB_REG1_ADDR, tmp);
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/* enable granite top reg */
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reg_id = ANA_GRANITE_TOP_REG;
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wdata = TOP_EN_SADC_MASK;
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wmask = TOP_EN_SADC_MASK;
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ana_i2c_write(reg_id, wdata, wmask);
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tmp = APB_GLB_READ_REG(CFG_APB_GLB_GEN0_ADDR);
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REG_FIELD_SET(SADC_EB, tmp, 1);
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APB_GLB_WRITE_REG(CFG_APB_GLB_GEN0_ADDR, tmp);
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tmp = PHY_DFE_READ_REG(CFG_BB_ADA_FORMAT_CFG_ADDR);
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REG_FIELD_SET(SW_MON_ADC_SEL, tmp, 1);
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PHY_DFE_WRITE_REG(CFG_BB_ADA_FORMAT_CFG_ADDR, tmp);
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/* enable granite sadc reg */
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reg_id = ANA_GRANITE_SADC_REG;
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ana_i2c_read(reg_id, &rdata, &rodata);
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REG_FIELD_SET(SADC_EN, rdata, 1); //sadc_en = 1
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REG_FIELD_SET(SADC_TIMER_DLY, rdata, 14);
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ana_i2c_write(reg_id, rdata, ~0);
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#ifdef TEST_DMA_MODE
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#error "stop support now"
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sadc_data_num_set(ANA_SADC0, 0, 8);
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#else
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sadc_data_num_set(ANA_SADC0, 0, 8); //64 accumulation data
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#endif
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sadc_sum_data_clr(1);
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sadc_discard_num_set(ANA_SADC0, 0, 2); //wait 1 clock cycle, then accumulate
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sadc_phase_mode_set(ANA_SADC0, 0); //0:1 phase mode 1:4 phase mode
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sadc_phase_sel(ANA_SADC0, 0); //for 1 phase mode, only 1 and 3 is valid!!
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sadc_phase_sel_scl_mux(0, channel[0]); //select SADC0
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sadc_phase_sel_scl_mux(1, channel[1]); //select SADC1
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sadc_phase_sel_scl_mux(2, channel[2]); //select SADC4
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sadc_phase_sel_scl_mux(3, channel[3]); //select SADC5
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sadc_adc_gain_set(channel[0] & 0x07, gain[0]); //(channel, gain)
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sadc_adc_gain_set(channel[1] & 0x07, gain[1]);
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sadc_adc_gain_set(channel[2] & 0x07, gain[2]);
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sadc_adc_gain_set(channel[3] & 0x07, gain[3]);
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sadc_dc_thr_set(4); //for gain 1/2, the DC calibration is 4
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//sadc_need_sub_dc_thr_set(I2S_MODE, 1);
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sadc_start_en(ANA_SADC0, 1);
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}
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#if DT_SADC_POLLING_EN
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void sadc_test_task()
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{
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uint32_t sample_data = 0;//, sample_tmp = 0;
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uint8_t timeout = 0;
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*(int *)0x44000004 |= 1 << 29; //enable sadc apb
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*(int *)0x44000004 |= 1 << 28; //enable i2s apb
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*(int *)0x44000004 |= 1 << 21; //enable dma apb
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*(int *)0x44000008 |= 1 << 28; //i2s soft reset enable
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*(int *)0x44000008 &= ~(1 << 28); //i2s soft reset enable
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*(int *)0x44000008 |= 1 << 29; //sadc soft reset enable
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*(int *)0x44000008 &= ~(1 << 29); //sadc soft reset enable
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*(int *)0x44000008 |= 1 << 21; //dma4 soft reset enable
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*(int *)0x44000008 &= ~(1 << 21); //dma4 soft reset enable
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sadc_dma_config();
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sadc_reg_cfg();
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sadc_i2s_cfg();
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iot_printf("sadc_i2s_data_buf_diff:\r\n");
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/*
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gain SADC_GAIN_CFG0
|
||
|
|
1/10 : 7
|
||
|
|
1/5 : 15
|
||
|
|
1/4 : 3
|
||
|
|
1/3 : 12
|
||
|
|
1/2 : 11
|
||
|
|
1 : 27
|
||
|
|
2 : 9
|
||
|
|
3 : 17
|
||
|
|
4 : 25
|
||
|
|
5 : 40
|
||
|
|
10 : 56
|
||
|
|
*/
|
||
|
|
|
||
|
|
while(1)
|
||
|
|
{
|
||
|
|
sample_data = sadc_poll_data_start(ADC_CHANNEL0_1, \
|
||
|
|
6,
|
||
|
|
9,
|
||
|
|
&timeout);
|
||
|
|
if (1 == timeout) {
|
||
|
|
iot_printf("sadc_sum_get time out!\n");
|
||
|
|
} else {
|
||
|
|
#if 0
|
||
|
|
if (sample_data & 0x8000) {
|
||
|
|
sample_tmp = sample_data - 0x10000;
|
||
|
|
} else {
|
||
|
|
sample_tmp = sample_data;
|
||
|
|
}
|
||
|
|
|
||
|
|
iot_printf("%d,\n", sample_tmp);
|
||
|
|
#else
|
||
|
|
iot_printf("%d,\n", sample_data);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#else
|
||
|
|
void sadc_test_task()
|
||
|
|
{
|
||
|
|
int i, j = 0;
|
||
|
|
//int i = 0;
|
||
|
|
*(int *)0x44000004 |= 1 << 29; //enable sadc apb
|
||
|
|
*(int *)0x44000004 |= 1 << 28; //enable i2s apb
|
||
|
|
*(int *)0x44000004 |= 1 << 21; //enable dma apb
|
||
|
|
|
||
|
|
*(int *)0x44000008 |= 1 << 28; //i2s soft reset enable
|
||
|
|
*(int *)0x44000008 &= ~(1 << 28); //i2s soft reset enable
|
||
|
|
|
||
|
|
*(int *)0x44000008 |= 1 << 29; //sadc soft reset enable
|
||
|
|
*(int *)0x44000008 &= ~(1 << 29); //sadc soft reset enable
|
||
|
|
|
||
|
|
*(int *)0x44000008 |= 1 << 21; //dma4 soft reset enable
|
||
|
|
*(int *)0x44000008 &= ~(1 << 21); //dma4 soft reset enable
|
||
|
|
int *pt[4];
|
||
|
|
for (i = 0; i < 4; i++)
|
||
|
|
{
|
||
|
|
pt[i] = phas_int_buf[i];
|
||
|
|
}
|
||
|
|
|
||
|
|
sadc_dma_config();
|
||
|
|
sadc_reg_cfg();
|
||
|
|
sadc_i2s_cfg();
|
||
|
|
|
||
|
|
iot_printf("sadc_i2s_data_buf_diff:\r\n");
|
||
|
|
|
||
|
|
while (1)
|
||
|
|
{
|
||
|
|
os_delay(500);
|
||
|
|
while(!recieved_done) __asm volatile("nop\n");
|
||
|
|
for(i=1; i<4; i++)
|
||
|
|
{
|
||
|
|
#ifdef TEST_DMA_MODE
|
||
|
|
sadc_dma_data_buf_diff(descLs[i].buf, DMA_BUF_SIZE, pt);
|
||
|
|
#else
|
||
|
|
sadc_i2s_data_buf_diff(descLs[i].buf, DMA_BUF_SIZE, pt);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
for (j = 0; j < 4; j++)
|
||
|
|
{
|
||
|
|
// iot_printf("\r\n*******************************************************\r\n");
|
||
|
|
|
||
|
|
//iot_printf("\nPHASE%d_INT_data:\n", j);
|
||
|
|
iot_printf("\n");
|
||
|
|
for (i = 0; i < SDAC_BUF_SIZE / 2; i++)
|
||
|
|
{
|
||
|
|
//iot_printf("%hd, ", (short)pt[j][i]);
|
||
|
|
iot_printf("%x ", (short)pt[j][i]);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
iot_printf("\n*******************************************************\n");
|
||
|
|
for (i = 1; i < 4; i++)
|
||
|
|
{
|
||
|
|
DMA_MAKE_DESC(&descLs[i], buf[i], DMA_BUF_SIZE, 0, 0, 0, 0, DESC_OWNER_DMA);
|
||
|
|
}
|
||
|
|
descLs[1].n_ptr = &descLs[2];
|
||
|
|
descLs[2].n_ptr = &descLs[3];
|
||
|
|
descLs[3].n_ptr = NULL;
|
||
|
|
|
||
|
|
dma_hw_start_recieve(DMA_DEV_I2S, &descLs[1]);
|
||
|
|
recieved_done = 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|