64 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
		
		
			
		
	
	
			64 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
|  | #ifndef __GD25Q32C_H
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|  | #define __GD25Q32C_H
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|  | 
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|  | #define WRITE_EN_CMD                0x06
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|  | #define WRITE_DIS_CMD               0x04
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|  | #define VOLATILE_SR_WR_EN_CMD       0x50
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|  | #define READ_STS_REG1_CMD           0x05
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|  | #define READ_STS_REG2_CMD           0x35
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|  | //#define READ_STS_REG3_CMD           0x15
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|  | #define WRITE_STS_REG1_CMD          0x01
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|  | #define WRITE_STS_REG2_CMD          0x31
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|  | //#define WRITE_STS_REG3_CMD          0x11
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|  | #define READ_DATA_CMD               0x03
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|  | #define FAST_READ_CMD               0x0B
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|  | #define DUAL_OUTPUT_FAST_RD_CMD     0x3B
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|  | #define DUAL_IO_FAST_RD_CMD         0xBB
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|  | #define QUAD_OUTPUT_FAST_RD_CMD     0x6B
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|  | #define QUAD_IO_FAST_RD_CMD         0xEB
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|  | #define QUAD_IO_WORD_FAST_RD_CMD    0xE7
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|  | #define PAGE_PROGRAM_CMD            0x02
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|  | #define QUAD_PAGE_PROGRAM_CMD       0x32
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|  | //#define FAST_PAGE_PROGRAM_CMD       0xF2
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|  | #define PAGE_ERASE_CMD              0x81
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|  | #define SECTOR_ERASE_CMD            0x20
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|  | //#define BLOCK_ERASE_32K_CMD         0x52
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|  | #define BLOCK_ERASE_64K_CMD         0xD8
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|  | #define CHIP_ERASE_CMD              0xC7    /*0x60*/
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|  | #define RESET_EN_CMD                0x66
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|  | #define RESET_CMD                   0x99
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|  | //#define SET_BURST_WITH_WRAP_CMD     0x77
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|  | #define PROGRAM_ERASE_SUSPEND_CMD   0x75
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|  | #define PROGRAM_ERASE_RESUME_CMD    0x7A
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|  | //#define RELEASE_FROM_DEEP_RD_ID_CMD 0xAB
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|  | //#define RELEASE_FROM_DEEP_CMD       0xAB
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|  | //#define DEEP_PWR_DN_CMD             0xB9
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|  | #define MANU_DEV_ID_CMD             0x90
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|  | #define MANU_DEV_ID_DUAL_IO_CMD     0x92
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|  | #define MANU_DEV_ID_QUAD_IO_CMD     0x94
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|  | #define READ_ID_CMD                 0x9F
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|  | //#define HIGH_PERF_MODE_CMD          0xA3
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|  | #define READ_DISCOVERY_PARA_CMD     0x5A
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|  | //#define ERASE_SECURITY_REG_CMD      0x44
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|  | //#define PROGRAM_SECURITY_REG_CMD    0x42
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|  | //#define READ_SECURITY_REG_CMD       0x48
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|  | #define READ_UNIQ_ID_CMD            0x4B
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|  | 
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|  | #define STS_WIP_BIT_S0              0x01
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|  | #define STS_WEL_BIT_S1              0x02
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|  | #define QUAD_ENA_BIT_S9             0x02
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|  | #define STS_SUS2_BIT_S10            0x04
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|  | #define STS_SUS1_BIT_S15            0x80
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|  | #define ADDR_DEFAULT_VAL_ZERO       0x00
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|  | 
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|  | #define PAGE_PROGRAM_MASK           0xFF
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|  | #define SECTOR_ERASE_MASK           0xFFF
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|  | //#define BLOCK_ERASE_32K_MASK        0x1FFFF
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|  | #define BLOCK_ERASE_64K_MASK        0xFFFF
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|  | 
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|  | #define P25Q16_32LE_SFDP            0xF1 /* PUYA 2/4MB 55nm SFDP */
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|  | #define P25Q16_32SL_SFDP            0xF9 /* PUYA 2/4MB 40nm SFDP */
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|  | 
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|  | #endif
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|  | 
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