96 lines
3.1 KiB
C
96 lines
3.1 KiB
C
|
|
||
|
|
//-----------------------------------
|
||
|
|
#define CFG_RTC_TMR_RVER_ADDR 0x0000
|
||
|
|
#define RTC_TMR_RF_VER_OFFSET 0
|
||
|
|
#define RTC_TMR_RF_VER_MASK 0x0000FFFF
|
||
|
|
|
||
|
|
//-----------------------------------
|
||
|
|
#define CFG_RTC_TMR0_CTRL_CFG_ADDR 0x0004
|
||
|
|
#define RTC_TMR0_TICK_SEL_OFFSET 4
|
||
|
|
#define RTC_TMR0_TICK_SEL_MASK 0x00000010
|
||
|
|
#define RTC_TMR0_PAUSE_CFG_OFFSET 3
|
||
|
|
#define RTC_TMR0_PAUSE_CFG_MASK 0x00000008
|
||
|
|
#define RTC_TMR0_INT_ENA_OFFSET 2
|
||
|
|
#define RTC_TMR0_INT_ENA_MASK 0x00000004
|
||
|
|
#define RTC_TMR0_ENA_CFG_OFFSET 1
|
||
|
|
#define RTC_TMR0_ENA_CFG_MASK 0x00000002
|
||
|
|
#define RTC_TMR0_MODE_CFG_OFFSET 0
|
||
|
|
#define RTC_TMR0_MODE_CFG_MASK 0x00000001
|
||
|
|
|
||
|
|
//-----------------------------------
|
||
|
|
#define CFG_RTC_TMR0_CFG_ADDR 0x0008
|
||
|
|
#define RTC_TMR0_CFG_OFFSET 0
|
||
|
|
#define RTC_TMR0_CFG_MASK 0xFFFFFFFF
|
||
|
|
|
||
|
|
//-----------------------------------
|
||
|
|
#define CFG_RTC_TMR0_INT_STATUS_ADDR 0x000C
|
||
|
|
#define RTC_TMR0_INT_RAW_OFFSET 1
|
||
|
|
#define RTC_TMR0_INT_RAW_MASK 0x00000002
|
||
|
|
#define RTC_TMR0_INT_STS_OFFSET 0
|
||
|
|
#define RTC_TMR0_INT_STS_MASK 0x00000001
|
||
|
|
|
||
|
|
//-----------------------------------
|
||
|
|
#define CFG_RTC_TMR0_VAL_ADDR 0x0010
|
||
|
|
#define RTC_TMR0_CNT_OFFSET 0
|
||
|
|
#define RTC_TMR0_CNT_MASK 0xFFFFFFFF
|
||
|
|
|
||
|
|
//-----------------------------------
|
||
|
|
#define CFG_RTC_TMR0_CLR_ADDR 0x0014
|
||
|
|
#define RTC_TMR0_INT_CLR_OFFSET 1
|
||
|
|
#define RTC_TMR0_INT_CLR_MASK 0x00000002
|
||
|
|
#define RTC_TMR0_CNT_CLR_OFFSET 0
|
||
|
|
#define RTC_TMR0_CNT_CLR_MASK 0x00000001
|
||
|
|
|
||
|
|
//-----------------------------------
|
||
|
|
#define CFG_RTC_TMR1_CTRL_CFG_ADDR 0x0018
|
||
|
|
#define RTC_TMR1_TICK_SEL_OFFSET 4
|
||
|
|
#define RTC_TMR1_TICK_SEL_MASK 0x00000010
|
||
|
|
#define RTC_TMR1_PAUSE_CFG_OFFSET 3
|
||
|
|
#define RTC_TMR1_PAUSE_CFG_MASK 0x00000008
|
||
|
|
#define RTC_TMR1_INT_ENA_OFFSET 2
|
||
|
|
#define RTC_TMR1_INT_ENA_MASK 0x00000004
|
||
|
|
#define RTC_TMR1_ENA_CFG_OFFSET 1
|
||
|
|
#define RTC_TMR1_ENA_CFG_MASK 0x00000002
|
||
|
|
#define RTC_TMR1_MODE_CFG_OFFSET 0
|
||
|
|
#define RTC_TMR1_MODE_CFG_MASK 0x00000001
|
||
|
|
|
||
|
|
//-----------------------------------
|
||
|
|
#define CFG_RTC_TMR1_CFG_ADDR 0x001C
|
||
|
|
#define RTC_TMR1_CFG_OFFSET 0
|
||
|
|
#define RTC_TMR1_CFG_MASK 0xFFFFFFFF
|
||
|
|
|
||
|
|
//-----------------------------------
|
||
|
|
#define CFG_RTC_TMR1_INT_STATUS_ADDR 0x0020
|
||
|
|
#define RTC_TMR1_INT_RAW_OFFSET 1
|
||
|
|
#define RTC_TMR1_INT_RAW_MASK 0x00000002
|
||
|
|
#define RTC_TMR1_INT_STS_OFFSET 0
|
||
|
|
#define RTC_TMR1_INT_STS_MASK 0x00000001
|
||
|
|
|
||
|
|
//-----------------------------------
|
||
|
|
#define CFG_RTC_TMR1_VAL_ADDR 0x0024
|
||
|
|
#define RTC_TMR1_CNT_OFFSET 0
|
||
|
|
#define RTC_TMR1_CNT_MASK 0xFFFFFFFF
|
||
|
|
|
||
|
|
//-----------------------------------
|
||
|
|
#define CFG_RTC_TMR1_CLR_ADDR 0x0028
|
||
|
|
#define RTC_TMR1_INT_CLR_OFFSET 1
|
||
|
|
#define RTC_TMR1_INT_CLR_MASK 0x00000002
|
||
|
|
#define RTC_TMR1_CNT_CLR_OFFSET 0
|
||
|
|
#define RTC_TMR1_CNT_CLR_MASK 0x00000001
|
||
|
|
|
||
|
|
//-----------------------------------
|
||
|
|
#define CFG_RTC_TMR0_DIV_ADDR 0x002C
|
||
|
|
#define RTC_TMR0_DIV_OFFSET 0
|
||
|
|
#define RTC_TMR0_DIV_MASK 0x000000FF
|
||
|
|
|
||
|
|
//-----------------------------------
|
||
|
|
#define CFG_RTC_TMR1_DIV_ADDR 0x0030
|
||
|
|
#define RTC_TMR1_DIV_OFFSET 0
|
||
|
|
#define RTC_TMR1_DIV_MASK 0x000000FF
|
||
|
|
|
||
|
|
//HW module read/write macro
|
||
|
|
#define RTC_TMR0_READ_REG(addr) SOC_READ_REG(RTC_TMR0_BASEADDR + addr)
|
||
|
|
#define RTC_TMR0_WRITE_REG(addr,value) SOC_WRITE_REG(RTC_TMR0_BASEADDR + addr,value)
|
||
|
|
#define RTC_TMR1_READ_REG(addr) SOC_READ_REG(RTC_TMR1_BASEADDR + addr)
|
||
|
|
#define RTC_TMR1_WRITE_REG(addr,value) SOC_WRITE_REG(RTC_TMR1_BASEADDR + addr,value)
|