301 lines
9.3 KiB
C
301 lines
9.3 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#ifndef MAC_UNI_CFG_API_H
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#define MAC_UNI_CFG_API_H
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#include "os_types.h"
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#include "mac_rf_scan.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct _cfg_data_tlv {
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uint32_t type;
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uint32_t len;
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} cfg_data_tlv;
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/* get phy support band range*/
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#define PLC_GET_SUPPORT_BAND 0
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/* get plc scan band range*/
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#define PLC_GET_SCAN_BAND 1
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/* type id of cfg */
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/* vdev region */
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#define PLC_VDEV_CFG 50
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#define PLC_VDEV_CFG_SET_SELF_TEI (PLC_VDEV_CFG + 0)
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#define PLC_VDEV_CFG_GET_SELF_TEI (PLC_VDEV_CFG + 1)
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#define PLC_VDEV_CFG_SET_STA_INFO (PLC_VDEV_CFG + 2)
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#define PLC_VDEV_CFG_GET_STA_INFO (PLC_VDEV_CFG + 3)
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#define PLC_VDEV_CFG_ADD_D_SUB_STA (PLC_VDEV_CFG + 4)
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#define PLC_VDEV_CFG_DELETE_D_SUB_STA (PLC_VDEV_CFG + 5)
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#define PLC_VDEV_CFG_SET_BL_NID (PLC_VDEV_CFG + 6)
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#define PLC_VDEV_CFG_SET_PREFER_NID (PLC_VDEV_CFG + 7)
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#define PLC_VDEV_CFG_SET_FIXED_RATE (PLC_VDEV_CFG + 8)
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#define PLC_VDEV_CFG_SET_TX_POWER_CAP (PLC_VDEV_CFG + 9)
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#define PLC_VDEV_CFG_SET_NID_ONLY (PLC_VDEV_CFG + 10)
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#define PLC_VDEV_CFG_SET_TEI_ONLY (PLC_VDEV_CFG + 11)
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#define PLC_VDEV_CFG_DUMP_REQ (PLC_VDEV_CFG + 12)
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#define PLC_VDEV_CFG_SET_NW_VALID (PLC_VDEV_CFG + 13)
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#define PLC_VDEV_CFG_SET_PM_SAVE_CFG (PLC_VDEV_CFG + 14)
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#define PLC_VDEV_CFG_CTL_CHECK_SPUR (PLC_VDEV_CFG + 15)
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#define PLC_VDEV_CFG_SET_RF_CHANNEL (PLC_VDEV_CFG + 16)
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#define PLC_VDEV_CFG_SET_FORCE_PHASE (PLC_VDEV_CFG + 17)
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#define PLC_VDEV_CFG_SET_STA_JOIN (PLC_VDEV_CFG + 18)
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#define PLC_VDEV_CFG_SET_HPLC_RF_ASYNC_TX (PLC_VDEV_CFG + 19)
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#define PLC_VDEV_CFG_SET_NW_NEGO (PLC_VDEV_CFG + 20)
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#define PLC_VDEV_CFG_SET_SEC_KEY (PLC_VDEV_CFG + 21)
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#define PLC_VDEV_CFG_SET_FORCE_LINK (PLC_VDEV_CFG + 22)
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#define PLC_VDEV_CFG_GET_NID_PPM (PLC_VDEV_CFG + 23)
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#define PLC_VDEV_CFG_SET_3PS_OPPOSITE (PLC_VDEV_CFG + 24)
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#define PLC_PDEV_CFG 80
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#define PLC_PDEV_CFG_SET_BAND (PLC_PDEV_CFG + 0)
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#define PLC_PDEV_CFG_SET_SWAGC (PLC_PDEV_CFG + 1)
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#define PLC_PDEV_CFG_SET_SCAN_BAND_TBL (PLC_PDEV_CFG + 2)
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#define PLC_PDEV_CFG_GET_BAND_TBL (PLC_PDEV_CFG + 3)
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#define PLC_PDEV_CFG_SET_RF_SCAN_TBL (PLC_PDEV_CFG + 4)
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#define PLC_BL_NID_LIST_MAX 32
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/* rate adaptation fixed low rate */
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#define PLC_RATE_ADAPT_RATE_LOW 1
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/* rate adaptation fixed medium rate */
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#define PLC_RATE_ADAPT_RATE_MEDIUM 2
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/* rate adaptation fixed high rate */
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#define PLC_RATE_ADAPT_RATE_HIGH 3
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#define MAC_ENCRYPT_SG_MSDU_AES_CBC 1
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#define MAC_ENCRYPT_SG_MSDU_AES_GCM 2
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#define MAC_ENCRYPT_SG_MSDU_SM4_CBC 3
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#define MAC_ENCRYPT_IEEE1901_1_PB_AES_CBC 4
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#define MAC_ENCRYPT_KEY_BIT_LEN_128 128
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#define MAC_ENCRYPT_KEY_BIT_LEN_192 192
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#define MAC_ENCRYPT_KEY_BIT_LEN_256 256
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#define MAC_SEC_KEY_COUNT_MAX 2
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#define MAC_SEC_KEY_LEN 32
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typedef struct _mac_sec_key {
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/* encryption algorithm type, see MAC_ENCRYPT_XXX */
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uint8_t encrypt_type :4,
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/* encryption key type, see ENCRYPT_KEY_TYPE_xxx */
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key_type :2,
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/* reserved for future */
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rsvd :2;
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/* key bit length, see MAC_ENCRYPT_KEY_BIT_LEN_XXX */
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uint16_t keybits;
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/* this cek corresponds to the following key */
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uint8_t cek_seq[MAC_SEC_KEY_COUNT_MAX];
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/* key data */
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uint8_t key[MAC_SEC_KEY_COUNT_MAX][MAC_SEC_KEY_LEN];
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} mac_sec_key_t;
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typedef struct _plc_ppm_status {
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uint32_t nid;
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/* ntb ppm err, unit: 1 ppm */
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int16_t ppm_err;
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} plc_ppm_status_t;
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typedef struct {
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cfg_data_tlv hdr;
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uint16_t self_tei;
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} PLC_VDEV_CFG_SET_SELF_TEI_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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uint16_t self_tei;
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uint16_t proxy_tei;
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uint8_t phase;
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} PLC_VDEV_CFG_SET_STA_INFO_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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tei_t sub_sta;
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} PLC_VDEV_CFG_D_SUB_STA_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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/* number of valid nid in the list */
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uint32_t cnt;
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/* black list nid */
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uint32_t nid[PLC_BL_NID_LIST_MAX];
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} PLC_VDEV_CFG_SET_BL_NID_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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/* preferred nid */
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uint32_t nid;
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/* preferred proxy tei */
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tei_t proxy;
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} PLC_VDEV_CFG_SET_PREFER_NID_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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/* flag to mark if fixed rate enabled */
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uint8_t enable;
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/* fixed rate level, see PLC_RATE_ADAPT_RATE_XXX*/
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uint8_t rate_level;
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} PLC_VDEV_CFG_SET_FIXED_RATE_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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/* flag to mark if hplc power config is valid*/
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uint8_t hplc_valid :1,
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/* flag to mark if rf power config is valid*/
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rf_valid :1,
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rsvd :6;
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/* hplc tx power cap to be set. unit is 1 dbuv, range 95 - 137 */
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uint8_t hplc_power;
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/* rf tx power cap to be set. unit is 1 dbm, range -35 - 20 */
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int8_t rf_power;
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} PLC_VDEV_CFG_SET_TX_POWER_CAP_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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uint8_t rf_channel; //rf channel
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uint8_t rf_option;
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} PLC_VDEV_CFG_SET_RF_CHANNEL_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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/* cco:flag to mark if force phase enabled
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* sta/3ps: not used.
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*/
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uint8_t enable;
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/* cco: force phy phase. see PLC_PHASE_xx.
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* sta/3ps: force tx switch gpio phase. see PLC_PHASE_xx.
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*/
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uint8_t phase;
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} PLC_VDEV_CFG_SET_FORCE_PHASE_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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/* flag to mark if sta joined network */
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uint8_t join_flag;
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} PLC_VDEV_CFG_SET_STA_JOIN_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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/* flag to mark if 3ps sta physical phase is opposite */
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uint8_t opposite_3ps;
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} PLC_VDEV_CFG_SET_3PS_OPPOSITE_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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uint32_t band_id; //band id
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} PLC_PDEV_CFG_SET_BANDID_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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uint32_t nid; //nid
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} PLC_PDEV_CFG_SET_NID_ONLY_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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uint16_t self_tei;
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} PLC_PDEV_CFG_SET_TEI_ONLY_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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uint32_t ena; //ena/dis
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} PLC_PDEV_CFG_SET_SWAGC_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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/* get support band or scan band.
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* 0: SUPPORT BAND.
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* 1: SCAN BAND.
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*/
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uint8_t is_scan_band;
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/* number of valid band in plc scan table */
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uint8_t plc_scan_cnt;
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/* plc scan table */
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plc_scan_band_t plc_scan_tbl[PLC_SCAN_BAND_MAX_CNT];
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} PLC_PDEV_CFG_BAND_RANGE_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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/* number of valid rf in rf scan table */
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uint8_t rf_cnt;
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/* rf scan table */
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mac_rf_scan_op_chn_t rf_scan_tbl[MAC_RF_SCAN_OP_CHN_MAX];
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} PLC_PDEV_CFG_RF_RANGE_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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} PLC_VDEV_CFG_DUMP_REQ_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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} PLC_VDEV_CFG_SET_NW_VALID_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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uint8_t allow_sleep;
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} PLC_VDEV_CFG_SET_PM_SAVE_CFG_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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uint8_t is_start;
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} PLC_PDEV_CFG_CTL_CK_SPUR_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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uint8_t hplc_rf_async_tx;
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} PLC_PDEV_CFG_SET_HPLC_RF_ASYNC_TX;
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typedef struct {
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cfg_data_tlv hdr;
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/* flag to mark if neighbour network negotiation enabled */
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uint8_t enable;
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} PLC_VDEV_CFG_SET_NW_NEGO_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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/* the security key information */
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mac_sec_key_t key_info;
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} PLC_VDEV_CFG_SET_SEC_KEY_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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/* flag to mark if force link enabled */
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uint8_t force_link_en : 1,
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/* force link type, 1 - force rf, 0 - force hplc */
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force_rf_link : 1,
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/* reserved for future */
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rsvd : 6;
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} PLC_VDEV_CFG_SET_FORCE_LINK_STRUCT;
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typedef struct {
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cfg_data_tlv hdr;
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/* number of valid nid ppm */
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uint8_t vaild_nid_cnt;
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/* point to plc_ppm_status_t nid_ppm_tbl[PLC_MAX_NEIGHBOR_NETWORK] */
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void *ppm_tbl;
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} PLC_VDEV_CFG_NID_PPM_STRUCT;
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// place other cfg in the following
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#ifdef __cplusplus
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}
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#endif
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#endif // !MAC_UNI_CFG_API_H
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