kunlun/dtest/bee_sram_test/smc_main.c

/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/
#include "chip_reg_base.h"
#include "hw_reg_api.h"
#include "iot_bitops.h"
#include "os_lock.h"
#include "iot_config.h"
#include "sram.h"
#include "os_mem.h"
#include "smc.h"

#if HW_PLATFORM > HW_PLATFORM_SIMU
#include "dbg_io.h"
#endif
#include "iot_io.h"

#include "ahb.h"
#include "sec_glb.h"

#define     CLK                 48  //16 //48
#define     PSRAM_ACCSEE_WAY    0    //0:cache  1:software

extern void sfc_bus_share_en();


void smc_rst() {

    /* warm reset sfc, set 1 and then clear */
    ahb_cache_disable();
    ahb_enable(AHB_EMC_HCLK_EB);
    ahb_reset(AHB_EMC_HCLK_EB);
    ahb_enable(AHB_EMC_EB);
    ahb_reset(AHB_EMC_EB);

    if(PSRAM_ACCSEE_WAY == 0){
        sram_qspi_enter();
        hal_smc_qspi_quad_cfg(CLK);
        ahb_cache_enable();
        //ahb_cache_reset();
        ahb_cachex_space_ena(0);
        ahb_cachex_space_ena(1);
        ahb_cachex_space_ena(2);
        ahb_cachex_space_ena(3);
    }
}

void smc_main() {
    uint32_t loop = 0x10000;
    uint8_t rdata[0x40] = {0};
    uint8_t wdata[0x40] = {1,2,3,4,5,6,7,8,9,0x11,0x22,0x33,0x44};

    int i = 0, j = 0, k = 0;
    int offset = 0;
    int len = sizeof(wdata);

    for(i = 0; i < len; i++) {
        wdata[i] = 0x5a;
    }

    dbg_uart_init();
    iot_printf("..........test..........\r\n");

    /* rst sfc */
    smc_rst();
    if(PSRAM_ACCSEE_WAY == 0)
    {
       int i,j;
       //int i;
       uint32_t wdat[50];
       uint32_t rdat[50];
       uint32_t rdat2[50];
       for (j=0;j<100;j++)
       {
           for (i=0;i<50;i++)
           {
               wdat[i]=0x12345678+i+j;
               *((volatile uint32_t*)(0x18000000+i*4)) = wdat[i];
               *((volatile uint32_t*)(0x28000000+i*4)) = wdat[i];
           }
           ahb_cachex_flush(1,0x18000000, 0x100);
           ahb_cachex_clear(0);

           ahb_cachex_flush(3,0x28000000, 0x100);
           ahb_cachex_clear(2);

           for (i=0;i<50;i++)
           {
               rdat[i]=((volatile uint32_t)*((volatile uint32_t*)(0x10000000+i*4)));
               rdat2[i]=((volatile uint32_t)*((volatile uint32_t*)(0x20000000+i*4)));
               if((wdat[i] != rdat[i]) || (wdat[i] != rdat2[i]))
               {
                   iot_printf("ERROR addr 0x%x, WR:0x%x, RD 0x%X\r\n",(0x10000000+i*4), wdat[i],rdat[i]);
                   iot_printf("ERROR addr 0x%x, WR:0x%x, RD 0x%X\r\n",(0x20000000+i*4), wdat[i],rdat2[i]);
               }
           }
       }
       iot_printf("finnished\n\r");
    }else{
    /* init sfc and sram */
	sfc_bus_share_en();
    sram_qspi_init();

    hal_smc_spi_cfg(CLK);
    do {
           if(sram_qspi_is_busy() != HAL_SRAM_OK){
              iot_printf("SRAM IS Busy Now!\r\n");
           }else{
            /* spi mode */
              sram_qspi_exit();
              iot_printf("spi write & read \n");
              wdata[10] = 0xaa;
              sram_qspi_write(wdata,0x1000,sizeof(wdata));

              while(sram_qspi_is_busy());
              os_mem_set(rdata,0,sizeof(rdata));
              sram_qspi_read(rdata,0x1000,sizeof(rdata));
              iot_printf("wdata[10]:%x, rdata[10]:%x\n", wdata[10], rdata[10]);
              if (wdata[10] != rdata[10]) {
                   iot_printf("ERROR!! qspi write, qspi read not match\n");
                //return;
           }

           /* qpi mode */
           iot_printf("qpi write & read \n");

           sram_qspi_enter();
           hal_smc_qspi_quad_cfg(CLK);
           wdata[10] = 0xbb;
           sram_qspi_quad_write(wdata,0x2000,sizeof(wdata));
           while(sram_qspi_is_busy());
           os_mem_set(rdata,0,sizeof(rdata));

           sram_qspi_quad_read(rdata,0x2000,sizeof(rdata));
           iot_printf("wdata[10]:%x, rdata[10]:%x\n", wdata[10], rdata[10]);
           if (wdata[10] != rdata[10]) {
               iot_printf(" quad write, quad read not match\n");
               return;
           }
           /* write read test */
           iot_printf(" write read loop test \n");
           offset = 0;
           j = 0;
           for (j = 0; j < 10; j++) {
               iot_printf("\r\n------loop %d offset %x------\r\n", j, offset);
               for(i = 0; i < len; i++) {
                   wdata[i] = 0x5a+1+j;
               }
               sram_qspi_quad_write(wdata, 0x1000+offset,sizeof(wdata));

               while(sram_qspi_is_busy());
               os_mem_set(rdata,0,sizeof(rdata));

               sram_qspi_quad_read(rdata, 0x1000 +offset, sizeof(rdata));

               for(i=0; i<len; i++) {
                   /*
                   iot_printf("addr: %08x %02x - %02x\r\n",
                           i+0x13000000, wdata[i], rdata[i]);
                   */
                   /*
                    if(wdata[i] != rdata[i]) {
                        iot_printf("not equal %d\r\n", i);
                        return ;
                    }
                    */

                   if (i % 4 == 0 ) {
                       iot_printf("\r\naddr: %08x: ", offset+i);
                   }
                   iot_printf("%02x ", rdata[i]);

               }
               k = 0;
               for(k=0;k<1000;k++);
               offset += 0x40;
            }
            sram_qspi_exit();
            return;
       }

       while(sram_qspi_is_busy());
       loop = 0x10000;
       while(loop--);
    } while (false);
  }
    return;
}

#ifdef __GNUC__

int main(void) {
    smc_main();
    return 0;
}
#endif // __GCC__