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kunlun/plc/halphy/hw/hw_phy_txrx_pwr.c

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2024-09-28 14:24:04 +08:00
/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
****************************************************************************/
#include "iot_config.h"
#include "iot_errno_api.h"
#include "iot_io.h"
#include "hw_phy_api.h"
#include "hw_tonemask.h"
#include "phy_txrx_pwr.h"
#include "phy_bb.h"
#include "phy_cfg.h"
#include "phy_dfe_reg.h"
#include "hw_reg_api.h"
#include "phy_rxtd_reg.h"
#include "phy_tx_reg.h"
#include "iot_system.h"
#include "phy_ana.h"
#include "phy_perf.h"
#include "iot_share_task.h"
#include "rx_mpdu_start.h"
#include "rx_desc_reg_api.h"
#define PHY_PWR_FD_RMS_MIN 27
phy_tx_pwr_cfg_tbl_t phy_tx_pwr_ctl_tbl[] = {
/*factor ana*/
{31, 3}, // 124dB
{30, 3}, // 123dB
{29, 3}, // 122dB
{28, 3}, // 121dB
{27, 3}, // 120dB
{26, 3}, // 119dB
{25, 3}, // 118dB
{24, 3}, // 117dB
{23, 3}, // 116dB
{22, 3}, // 115dB
{21, 3}, // 114dB
{20, 3}, // 113dB
{25, 2}, // 112dB
{24, 2}, // 111dB
{23, 2}, // 110dB
{22, 2}, // 109dB
{21, 2}, // 108dB
{20, 2}, // 107dB
{25, 1}, // 106dB
{24, 1}, // 105dB
{23, 1}, // 104dB
{22, 1}, // 103dB
{21, 1}, // 102dB
{20, 1}, // 101dB
{25, 0}, // 100dB
{24, 0}, // 99dB
{23, 0}, // 98dB
{22, 0}, // 97dB
{21, 0}, // 96dB
{20, 0}, // 95dB
};
/* get fd rms info depend on tonemask id */
uint32_t phy_tone_msk_rms_get_by_valid_tone(uint16_t valid_tone_num, \
uint8_t *fd_rms)
{
uint8_t band_idx = 0;
uint32_t ret = ERR_FAIL;
#if IOT_DTEST_ONLY_SUPPORT == 0
if (g_phy_ctxt.indep.tx_pwr_psd_fix_db > 0) {
if (g_phy_cpu_share_ctxt.tx_pwr_ctl_ena) {
*fd_rms = (uint8_t)( \
g_phy_ctxt.indep.tx_pwr_psd_fix_db - \
PHY_PWR_DIG_ATT_MAX);
} else {
*fd_rms = (uint8_t)( \
g_phy_ctxt.indep.tx_pwr_psd_fix_db);
}
return ERR_OK;
}
#endif
for(band_idx = 0; \
band_idx < sizeof(iot_plc_tonemask_rms_all)/sizeof(plc_tonemask_rms_table); \
band_idx++)
{
if (iot_plc_tonemask_rms_all[band_idx].valid_tone_number == \
valid_tone_num) {
#if IOT_DTEST_ONLY_SUPPORT == 0
if (g_phy_cpu_share_ctxt.tx_pwr_ctl_ena)
#else
if (0)
#endif
{
*fd_rms = (uint8_t)( \
iot_plc_tonemask_rms_all[band_idx].fd_rms_max);
} else {
*fd_rms = (uint8_t)( \
iot_plc_tonemask_rms_all[band_idx].fd_rms_max - \
g_phy_ctxt.indep.tx_pwr_reduce_db);
}
ret = ERR_OK;
break;
}
}
#if IOT_DTEST_ONLY_SUPPORT == 0
if (!g_phy_cpu_share_ctxt.tx_pwr_ctl_ena) {
*fd_rms += PHY_PWR_DIG_ATT_MAX;
}
#endif
return ret;
}
/* kunlun1 pwr control */
const phy_fd_td_ana_full_t phy_fd_td_ana_full_tbl[] = {
{IOT_SUPPORT_TONE_80_490, {60, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 125}},
{IOT_SUPPORT_TONE_100_230, {65, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 122}},
{IOT_SUPPORT_TONE_32_120, {67, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 120}},
{IOT_SUPPORT_TONE_72_120, {70, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 118}},
{IOT_SUPPORT_TONE_231_490, {62, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 125}},
{IOT_SUPPORT_TONE_240_370, {65, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 122}},
{IOT_SUPPORT_TONE_200_1000, {57, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 130}},
{IOT_SUPPORT_TONE_1160_1415, {62, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 125}},
{IOT_SUPPORT_TONE_200_500, {62, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 126}},
{IOT_SUPPORT_TONE_TIDE, {67, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 120}},
{IOT_SUPPORT_TONE_100_230_CE,{70, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 118}},
{IOT_SUPPORT_TONE_231_490_CE,{65, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 122}},
};
uint32_t phy_fd_td_ana_full_get(uint32_t band_id,
const phy_fd_td_ana_full_t *tbl,
uint16_t tbl_len,
uint8_t *fd_pwr_int,
uint8_t *fd_pwr_frac,
uint8_t *td_pwr,
uint8_t *ana_pwr)
{
for (int i = 0; i < tbl_len; i++) {
if (tbl[i].band_id == band_id) {
*fd_pwr_int = tbl[i].fd_td_ana_full.fd_pwr_int;
if (phy_get_pwr_ctl_en()) {
*fd_pwr_frac = tbl[i].fd_td_ana_full.fd_pwr_frac;
} else {
*fd_pwr_frac = tbl[i].fd_td_ana_full.fd_pwr_frac_lp;
}
*td_pwr = tbl[i].fd_td_ana_full.td_pwr;
*ana_pwr = tbl[i].fd_td_ana_full.ana_pwr;
return ERR_OK;
}
}
return ERR_INVAL;
}
uint32_t phy_tx_pwr_to_fd_td_ana_value(
uint32_t hw_rate_id,
uint32_t band_id,
uint8_t uint_dbuv,
uint8_t *fd_pwr_int,
uint8_t *fd_pwr_frac,
uint8_t *td_pwr,
uint8_t *ana_pwr)
{
uint32_t ret = ERR_OK;
uint8_t rms_delta = 0;
/* get set delta */
rms_delta = PHY_FULL_PWR_DBUV - uint_dbuv;
ret = phy_fd_td_ana_full_get(band_id,
phy_fd_td_ana_full_tbl,
IOT_ARRAY_CNT(phy_fd_td_ana_full_tbl),
fd_pwr_int,
fd_pwr_frac,
td_pwr,
ana_pwr);
if (ret != ERR_OK) {
iot_printf("phy fd_td_ana full power para get fail\n");
return ret;
}
#if HW_PLATFORM == HW_PLATFORM_FPGA
/* without analog PA */
*fd_pwr_int = *fd_pwr_int - rms_delta;
*ana_pwr = 0;
#elif HW_PLATFORM == HW_PLATFORM_SILICON
int8_t pwr_max;
/* fd power reduce max */
pwr_max = *fd_pwr_int - PHY_PWR_FD_RMS_MIN;
if (rms_delta <= pwr_max) {
*fd_pwr_int -= rms_delta;
} else {
*fd_pwr_int -= pwr_max;
rms_delta -= pwr_max;
/* ana power reduce max */
pwr_max = *ana_pwr * PHY_PWR_ANA_STEP_LEN;
if (rms_delta <= pwr_max) {
*ana_pwr -= rms_delta / PHY_PWR_ANA_STEP_LEN;
rms_delta -= (rms_delta / PHY_PWR_ANA_STEP_LEN)
* PHY_PWR_ANA_STEP_LEN;
} else {
*ana_pwr = 0;
rms_delta -= pwr_max;
}
if (rms_delta > 0) {
/* td power reduce max */
pwr_max = (int8_t)*td_pwr - PHY_PWR_TD_MIN;
if (rms_delta <= pwr_max) {
*td_pwr = (uint8_t)((int8_t)*td_pwr - (int8_t)rms_delta);
} else {
*td_pwr = PHY_PWR_TD_MIN;
}
}
}
#endif
(void)hw_rate_id;
return ret;
}
uint32_t phy_get_default_tx_pwr(uint32_t band_id,uint8_t *uint_dbuv,
uint8_t *dlt_max)
{
uint32_t ret = ERR_INVAL;
uint8_t full_dbuv, lp_dbuv;
for (int i = 0; i < IOT_ARRAY_CNT(phy_fd_td_ana_full_tbl); i++) {
if (phy_fd_td_ana_full_tbl[i].band_id == band_id) {
full_dbuv = phy_fd_td_ana_full_tbl[i].psd_full.full_dbuv;
if (!phy_get_pwr_ctl_en()) {
lp_dbuv = phy_fd_td_ana_full_tbl[i].psd_full.lp_dbuv;
*dlt_max = full_dbuv - lp_dbuv;
*uint_dbuv = lp_dbuv;
ret = ERR_OK;
} else {
*dlt_max = 0;
*uint_dbuv = full_dbuv;
ret = ERR_OK;
break;
}
}
}
return ret;
}
void phy_set_sack_tx_power(uint32_t pwr_db)
{
(void)pwr_db;
}
void phy_high_perf_set(bool_t en)
{
#if IOT_DTEST_ONLY_SUPPORT == 0
uint32_t tmp = 0;
bool_t en_int = false;
/* protect, force en_int to avoid high level call this function by mistake */
#if (PHY_CHIP_CERT_EN == 1)
en_int = true;
#else
en_int = en;
#endif
/* Product test Mode disable high performance setting */
if ((1 == g_phy_cpu_share_ctxt.pt_mode_entry) || \
(MP_MODE == phy_get_fw_mode())) {
en_int = false;
}
if (en_int) {
/* fix gain enable,
* disable power satuation and hw adjust gain req
*/
phy_set_fix_gain_sat_adj_dis(1, 0, -24, 0, 1, 1);
/* bypass dc blocker */
tmp = PHY_DFE_READ_REG(CFG_BB_DC_BLK_STAGE_DLY_ADDR);
REG_FIELD_SET(SW_DC_BLK_BYPASS, tmp, 1);
PHY_DFE_WRITE_REG(CFG_BB_DC_BLK_STAGE_DLY_ADDR, tmp);
/* use 192 point agc */
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
REG_FIELD_SET(SW_AGC_ACC_STEP_LS,tmp,4);
REG_FIELD_SET(SW_AGC_ACC_STEP_HS,tmp,0);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR,tmp);
/* let cpu1 know */
g_phy_cpu_share_ctxt.high_perf_en = 1;
g_phy_cpu_share_ctxt.shift_low = 1;
g_phy_cpu_share_ctxt.shift_high = 2;
/* re-enable cpu1 to protect */
PHY_RXTD_WRITE_REG(CFG_BB_RXTD_SPARE2_ADDR, 0x5A5A5A5A);
} else {
/* not fix gain,
* enable power satuation and hw adjust gain req
*/
phy_set_fix_gain_sat_adj_dis(0, 60, -24, 0, 0, 0);
/* use 1536 point agc */
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
REG_FIELD_SET(SW_AGC_ACC_STEP_LS,tmp,4);
REG_FIELD_SET(SW_AGC_ACC_STEP_HS,tmp,3);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR,tmp);
/* let cpu1 know */
g_phy_cpu_share_ctxt.high_perf_en = 0;
g_phy_cpu_share_ctxt.shift_low = 0;
g_phy_cpu_share_ctxt.shift_high = 0;
}
iot_printf("[PHY] high_perf_en is %d, agc_level:0x%x\n",
en_int, PHY_RXTD_READ_REG(CFG_BB_AGC_GAIN_LEVEL_ADDR));
#else
(void)en;
#endif
}
uint32_t phy_pwr_psd_ctl_update(uint8_t uint_dbuv)
{
uint32_t ret = ERR_OK;
#if IOT_DTEST_ONLY_SUPPORT == 0
uint8_t para_int = 0, para_frac = 0;
uint8_t fix_db_backup = 0;
if (PHY_FULL_PWR_DBUV == uint_dbuv) {
/* switch to default psd mode */
para_int = (uint8_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db);
phy_tx_rms_set(0, HW_FULL_BAND, para_int, para_frac);
phy_tx_rms_set(0, HW_LOW_BAND, para_int, para_frac);
phy_tx_rms_set(0, HW_HIGH_BAND, para_int, para_frac);
phy_tx_rms_set(1, HW_FULL_BAND, para_int, para_frac);
phy_tx_rms_set(1, HW_LOW_BAND, para_int, para_frac);
phy_tx_rms_set(1, HW_HIGH_BAND, para_int, para_frac);
/* td/ana set to default */
phy_tx_gain_factor_set(0);
phy_ana_pga_gain_set(3);
} else {
/* clear psd flag*/
fix_db_backup = (uint8_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db);
g_phy_ctxt.indep.tx_pwr_psd_fix_db = 0;
if (uint_dbuv > PHY_PWR_ADJ_MAX) {
int8_t delta = uint_dbuv;
uint8_t fix_pga;
if (delta <= PHY_PWR_DIG_ATT_MAX) {
phy_tx_gain_factor_set((uint8_t)(
((SW_TX_PWR_SCALE_FACTOR_MASK
>> SW_TX_PWR_SCALE_FACTOR_OFFSET) + 1 - delta)));
delta = 0;
} else {
phy_tx_gain_factor_set((uint8_t)(
((SW_TX_PWR_SCALE_FACTOR_MASK
>> SW_TX_PWR_SCALE_FACTOR_OFFSET) + 1
- PHY_PWR_DIG_ATT_MAX)));
delta -= PHY_PWR_DIG_ATT_MAX;
}
if (delta > 0) {
if (delta <= PHY_PWR_ANA_MAX) {
fix_pga = PHY_PWR_ANA_STEP_NUM
- (delta / PHY_PWR_ANA_STEP_LEN);
delta -= fix_pga * PHY_PWR_ANA_STEP_LEN;
} else {
fix_pga = 0;
delta -= PHY_PWR_ANA_MAX;
}
phy_ana_pga_gain_set(fix_pga);
}
g_phy_ctxt.indep.tx_pwr_reduce_db = delta;
} else {
/* alloc reduce db to glb value */
g_phy_ctxt.indep.tx_pwr_reduce_db = uint_dbuv;
/* td/ana set to default */
phy_tx_gain_factor_set(0);
phy_ana_pga_gain_set(3);
}
/* update fd rms */
phy_fd_rms_update();
/* backup after get valid rms */
g_phy_ctxt.indep.tx_pwr_psd_fix_db = fix_db_backup;
}
#endif
return ret;
}
uint32_t phy_swagc_set(bool_t en)
{
if (en) {
/* enable sw-agc */
phy_high_perf_set(true);
} else {
/* clear shift en */
PHY_RXTD_WRITE_REG(CFG_BB_RXTD_SPARE2_ADDR, 0);
/* dly a cycle */
phy_rx_nf_by_rxtd_get(14);
/* clear shift */
phy_gain_shift_set(0,0,0,0);
/* hw-agc init */
phy_high_perf_set(false);
}
return ERR_OK;
}
void phy_tx_resp_pwr_ctl_en(
uint8_t fd_int_en, uint8_t fd_frac_en, uint8_t td_en, uint8_t ana_en)
{
(void)fd_int_en;
(void)fd_frac_en;
(void)td_en;
(void)ana_en;
}
void phy_set_tx_resp_pwr(
uint8_t fd_int, uint8_t fd_frac, uint8_t td, uint8_t ana)
{
(void)fd_int;
(void)fd_frac;
(void)td;
(void)ana;
}
uint32_t phy_info_check_entry(void *mpdu_st, \
void *fc, uint32_t role, uint8_t mt_mode_sel)
{
uint32_t ret = ERR_OK;
uint32_t tmp = 0;
rx_mpdu_start *mpdu_ptr = (rx_mpdu_start *)mpdu_st;
iot_phy_info_t *ptr = &mpdu_ptr->phy;
(void)role;
/* check beacon pkt */
frame_control_t *sg_fc = (frame_control_t *)fc;
if(sg_fc->delimiter_type == 0) {
if(g_phy_ctxt.indep.work_mode == PHY_MODE_TEST && \
(mt_mode_sel == CERT_TEST_CMD_ENTER_PHY_T || \
mt_mode_sel == CERT_TEST_CMD_ENTER_PHY_LP)) {
/* TODO: replace by dynamic spur check */
if (mt_mode_sel == CERT_TEST_CMD_ENTER_PHY_LP) {
/* diabale sw-agc */
PHY_RXTD_WRITE_REG(CFG_BB_RXTD_SPARE2_ADDR, 0);
/* dly a cycle */
phy_rx_nf_by_rxtd_get(14);
/* clear shift */
phy_gain_shift_set(0,0,0,0);
/* clr spur or pulse setting */
phy_anti_spur_set_clr();
phy_anti_pulse_set_clr();
/* off check spur on loopback mode */
//phy_channel_est_request();
/* use 1536 point agc */
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
REG_FIELD_SET(SW_AGC_ACC_STEP_LS,tmp,4);
REG_FIELD_SET(SW_AGC_ACC_STEP_HS,tmp,3);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR,tmp);
/* shandong cert test. band0 extmi 1 can not pass.
* In the high frequency part, the energy is relatively low.
* so for the TMI(EXTMI 1) copycnt < 2, increase power.
*/
if (phy_band_id_get() == IOT_SUPPORT_TONE_80_490) {
phy_set_soft_shift0(15);
}
iot_printf("[BB] disable sw-agc for loopback!\n");
} else if (mt_mode_sel == CERT_TEST_CMD_ENTER_PHY_T) {
if (phy_band_id_get() == IOT_SUPPORT_TONE_100_230) {
if (phy_cert_is_hw_agc()) {
/* mask 2M spur by notch filter */
phy_anf_option_set(PHY_ANF_MODE_FIX, 1, 1, 0x81ca);
} else {
/* mask 6M spur by notch filter */
phy_anf_option_set(PHY_ANF_MODE_FIX, 1, 1, 0x8fd5);
}
/* mask 3M spur by spur mask, [-7,7] */
phy_spur_mask_set(123, 15);
/* mask 1M spur by notch filter */
phy_anf_option_set(PHY_ANF_MODE_FIX, 1, 2, 0x8073);
} else if (phy_band_id_get() == IOT_SUPPORT_TONE_32_120) {
/* mask 2M spur by spur mask, [-7,7] */
/* NOTE: mendong cert test.
* do not mask tone.
*/
if (!(phy_cert_is_hw_agc())) {
phy_spur_mask_set(82, 15);
}
}
if (phy_cert_is_hw_agc()) {
/* NOTE: mendong cert test,
* low rssi need use swagc.
* but other place(like gansu) cert test,
* low rssi need use hwagc.
*/
/* use rssi judge whether use swagc or not */
uint32_t rssi_t = PHY_RSSI_FROM_RMI_GAIN(ptr->adc_power, \
ptr->agc_tbl_entry);
if (rssi_t < 45) {
phy_swagc_set(true);
phy_rxfd_pkt_det_thd_set(32, 32);
iot_printf("[BB] rssi <= 45 for tt!\n");
}
} else {
/* if adc <= 53 hw-agc */
if (ptr->adc_power <= 114) {
/* diabale sw-agc */
PHY_RXTD_WRITE_REG(CFG_BB_RXTD_SPARE2_ADDR, 0);
/* dly a cycle */
phy_rx_nf_by_rxtd_get(14);
/* clear shift */
phy_gain_shift_set(0,0,0,0);
/* clr spur or pulse setting */
phy_anti_spur_set_clr();
phy_anti_pulse_set_clr();
/* use 1536 point agc */
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
REG_FIELD_SET(SW_AGC_ACC_STEP_LS,tmp,4);
REG_FIELD_SET(SW_AGC_ACC_STEP_HS,tmp,3);
PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR,tmp);
iot_printf("[BB] hwagc if rssi <= 53 for tt!\n");
}
}
phy_channel_est_request();
}
}
/* TODO: check phy channel info */
}
tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE0_BAND0_ADDR);
#if PHY_DBG_EN
iot_printf("[BB] spare2:%x-%x-%x, psd:%d\n", \
PHY_RXTD_READ_REG(CFG_BB_RXTD_SPARE2_ADDR), \
PHY_RXTD_READ_REG(CFG_BB_RXTD_SPARE1_ADDR), \
PHY_RXTD_READ_REG(CFG_BB_RXTD_SPARE3_ADDR), \
REG_FIELD_GET(SW_RATE0_BAND0_DB_UP_AMP_PARA_INT,tmp));
tmp = PHY_DFE_READ_REG(CFG_BB_SW_ADJUST_GAIN_ADDR);
iot_printf("[BB] rx shift:%d-%d\n", \
REG_FIELD_GET(SW_RX_GAIN_LEFT_SHIFT, tmp),
REG_FIELD_GET(SW_RX_GAIN_SHIFT_BITS, tmp));
#endif
return ret;
}
void phy_check_spur_cert_handle(uint16_t notch_alpha)
{
(void)notch_alpha;
}
uint32_t phy_work_mode_set(phy_work_mode_id mode)
{
uint32_t ret = ERR_OK;
uint32_t mask_id = phy_mask_id_get();
uint32_t mac_proto = PHY_PROTO_TYPE_GET();
if(mode < PHY_MODE_END) {
g_phy_ctxt.indep.work_mode = mode;
if(g_phy_ctxt.indep.work_mode == PHY_MODE_TEST) {
/* modify tx power */
if(g_phy_ctxt.indep.tx_pwr_psd_fix_db > 0) {
phy_tx_rms_set(0, HW_FULL_BAND, \
(uint16_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db), 0);
phy_tx_rms_set(0, HW_LOW_BAND, \
(uint16_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db), 0);
phy_tx_rms_set(0, HW_HIGH_BAND, \
(uint16_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db), 0);
phy_tx_rms_set(1, HW_FULL_BAND, \
(uint16_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db), 0);
phy_tx_rms_set(1, HW_LOW_BAND, \
(uint16_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db), 0);
phy_tx_rms_set(1, HW_HIGH_BAND, \
(uint16_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db), 0);
} else {
phy_tx_rms_set(0, HW_FULL_BAND, PHY_CERT_DST_RMS, 0);
phy_tx_rms_set(0, HW_LOW_BAND, PHY_CERT_DST_RMS, 0);
phy_tx_rms_set(0, HW_HIGH_BAND, PHY_CERT_DST_RMS, 0);
phy_tx_rms_set(1, HW_FULL_BAND, PHY_CERT_DST_RMS, 0);
phy_tx_rms_set(1, HW_LOW_BAND, PHY_CERT_DST_RMS, 0);
phy_tx_rms_set(1, HW_HIGH_BAND, PHY_CERT_DST_RMS, 0);
}
/* if box4 or box5, rise the power */
if (1 == g_phy_ctxt.indep.chn.is_pwr_rise) {
phy_pwr_adjust_set(PHY_FULL_PWR_DBUV);
}
/* del time domain shift */
phy_tx_gain_factor_set(0);
/* init tonemask */
phy_tone_mask_amp_phase_tab_load( \
&all_mask_amp_phase_table, mask_id, mac_proto);
/* del shift in cert mode */
g_phy_cpu_share_ctxt.shift_low = 0;
g_phy_cpu_share_ctxt.shift_high = 0;
/* reduce wraning */
if (phy_band_id_get() == IOT_SUPPORT_TONE_32_120 || \
phy_band_id_get() == IOT_SUPPORT_TONE_72_120) {
phy_rxfd_pkt_det_thd_set(32, 48);
phy_rxfd_frame_sync_set(32);
} else if (phy_band_id_get() == IOT_SUPPORT_TONE_100_230) {
if (1 == g_phy_ctxt.indep.chn.is_pwr_rise) {
phy_rxfd_pkt_det_thd_set(16, 32);
} else {
phy_rxfd_pkt_det_thd_set(32, 32);
}
}
iot_printf("[BB] enter cert mode!\n");
}
} else {
ret = ERR_FAIL;
}
return ret;
}
void phy_overstress_power_down(uint32_t dowm_db)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tx_power = phy_get_tx_pwr_limit(phy_proto_single_band_id_get());
if (tx_power > dowm_db) {
tx_power -= dowm_db;
}
g_phy_ctxt.indep.ovs_ctxt.ovr_pwr = max(tx_power, MIN_TX_POWER);
phy_set_tx_pwr_limit(tx_power);
#else
(void)dowm_db;
#endif
}
void phy_overstress_power_up()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
/* ignore overstress power and set sw_set_power */
phy_set_tx_pwr_limit(g_phy_ctxt.dep.sw_set_pwr);
#endif
}
uint32_t phy_set_common_pwr_reg(uint32_t pwr_db)
{
uint8_t fd_pwr_int, fd_pwr_frac, td_pwr, ana_pwr;
uint32_t single_proto_band = phy_proto_single_band_id_get();
phy_tx_pwr_to_fd_td_ana_value(0,
single_proto_band,
(uint8_t)pwr_db,
&fd_pwr_int,
&fd_pwr_frac,
&td_pwr,
&ana_pwr);
/* set td and ana power to register */
/* rate0 band0/1/2 */
phy_tx_rms_set(0, HW_FULL_BAND, fd_pwr_int, fd_pwr_frac);
phy_tx_rms_set(0, HW_LOW_BAND, fd_pwr_int, fd_pwr_frac);
phy_tx_rms_set(0, HW_HIGH_BAND, fd_pwr_int, fd_pwr_frac);
/* rate1 band0/1/2 */
phy_tx_rms_set(1, HW_FULL_BAND, fd_pwr_int, fd_pwr_frac);
phy_tx_rms_set(1, HW_LOW_BAND, fd_pwr_int, fd_pwr_frac);
phy_tx_rms_set(1, HW_HIGH_BAND, fd_pwr_int, fd_pwr_frac);
/* td power */
phy_tx_gain_factor_set(td_pwr);
/* tx pga config */
phy_ana_pga_gain_set(ana_pwr);
iot_printf("[ptr_dbg] set pwr_reg power:%d, td_pwr:%d, ana_pwr:%d, "
"fd_frac:%d, fd_int:%d\n",
pwr_db, td_pwr, ana_pwr, fd_pwr_frac, fd_pwr_int);
return 0;
}
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