kunlun/inc/hw/reg/riscv2/15/pwm_reg.h

//-----------------------------------
#define CFG_PTCON_ADDR 0x00
#define PTEN_OFFSET 15
#define PTEN_MASK 0x00008000
#define PTOPS_OFFSET 4
#define PTOPS_MASK 0x000000F0
#define PTMOD_OFFSET 0
#define PTMOD_MASK 0x00000003

//-----------------------------------
#define CFG_PTMR_ADDR 0x04
#define PTDIR_OFFSET 15
#define PTDIR_MASK 0x00008000
#define PTMR_OFFSET 0
#define PTMR_MASK 0x00007FFF

//-----------------------------------
#define CFG_PTPER_ADDR 0x08
#define PTPER_OFFSET 0
#define PTPER_MASK 0x00007FFF

//-----------------------------------
#define CFG_SEVTCMP_ADDR 0x0C
#define SEVTDIR_OFFSET 15
#define SEVTDIR_MASK 0x00008000
#define SEVTCMP_OFFSET 0
#define SEVTCMP_MASK 0x00007FFF

//-----------------------------------
#define CFG_PWMCON1_ADDR 0x10
#define PMOD4_OFFSET 11
#define PMOD4_MASK 0x00000800
#define PMOD3_OFFSET 10
#define PMOD3_MASK 0x00000400
#define PMOD2_OFFSET 9
#define PMOD2_MASK 0x00000200
#define PMOD1_OFFSET 8
#define PMOD1_MASK 0x00000100

//-----------------------------------
#define CFG_PWM_ICAP_ADDR 0x14
#define SEVOPS_OFFSET 8
#define SEVOPS_MASK 0x00000F00
#define IUE_OFFSET 2
#define IUE_MASK 0x00000004
#define OSYNC_OFFSET 1
#define OSYNC_MASK 0x00000002
#define UDIS_OFFSET 0
#define UDIS_MASK 0x00000001

//-----------------------------------
#define CFG_DTCON1_ADDR 0x18
#define DTBPS_OFFSET 14
#define DTBPS_MASK 0x0000C000
#define DTB_OFFSET 8
#define DTB_MASK 0x00003F00
#define DTAPS_OFFSET 6
#define DTAPS_MASK 0x000000C0
#define DTA_OFFSET 0
#define DTA_MASK 0x0000003F

//-----------------------------------
#define CFG_DTCON2_ADDR 0x1C
#define DTS4A_OFFSET 7
#define DTS4A_MASK 0x00000080
#define DTS4I_OFFSET 6
#define DTS4I_MASK 0x00000040
#define DTS3A_OFFSET 5
#define DTS3A_MASK 0x00000020
#define DTS3I_OFFSET 4
#define DTS3I_MASK 0x00000010
#define DTS2A_OFFSET 3
#define DTS2A_MASK 0x00000008
#define DTS2I_OFFSET 2
#define DTS2I_MASK 0x00000004
#define DTS1A_OFFSET 1
#define DTS1A_MASK 0x00000002
#define DTS1I_OFFSET 0
#define DTS1I_MASK 0x00000001

//-----------------------------------
#define CFG_FLTACON_ADDR 0x20
#define FAOV4H_OFFSET 15
#define FAOV4H_MASK 0x00008000
#define FAOV4L_OFFSET 14
#define FAOV4L_MASK 0x00004000
#define FAOV3H_OFFSET 13
#define FAOV3H_MASK 0x00002000
#define FAOV3L_OFFSET 12
#define FAOV3L_MASK 0x00001000
#define FAOV2H_OFFSET 11
#define FAOV2H_MASK 0x00000800
#define FAOV2L_OFFSET 10
#define FAOV2L_MASK 0x00000400
#define FAOV1H_OFFSET 9
#define FAOV1H_MASK 0x00000200
#define FAOV1L_OFFSET 8
#define FAOV1L_MASK 0x00000100
#define FLTAM_OFFSET 7
#define FLTAM_MASK 0x00000080
#define FAEN4_OFFSET 3
#define FAEN4_MASK 0x00000008
#define FAEN3_OFFSET 2
#define FAEN3_MASK 0x00000004
#define FAEN2_OFFSET 1
#define FAEN2_MASK 0x00000002
#define FAEN1_OFFSET 0
#define FAEN1_MASK 0x00000001

//-----------------------------------
#define CFG_FLTBCON_ADDR 0x24
#define FBOV4H_OFFSET 15
#define FBOV4H_MASK 0x00008000
#define FBOV4L_OFFSET 14
#define FBOV4L_MASK 0x00004000
#define FBOV3H_OFFSET 13
#define FBOV3H_MASK 0x00002000
#define FBOV3L_OFFSET 12
#define FBOV3L_MASK 0x00001000
#define FBOV2H_OFFSET 11
#define FBOV2H_MASK 0x00000800
#define FBOV2L_OFFSET 10
#define FBOV2L_MASK 0x00000400
#define FBOV1H_OFFSET 9
#define FBOV1H_MASK 0x00000200
#define FBOV1L_OFFSET 8
#define FBOV1L_MASK 0x00000100
#define FLTBM_OFFSET 7
#define FLTBM_MASK 0x00000080
#define FBEN4_OFFSET 3
#define FBEN4_MASK 0x00000008
#define FBEN3_OFFSET 2
#define FBEN3_MASK 0x00000004
#define FBEN2_OFFSET 1
#define FBEN2_MASK 0x00000002
#define FBEN1_OFFSET 0
#define FBEN1_MASK 0x00000001

//-----------------------------------
#define CFG_OVDCON_ADDR 0x28
#define POVD4H_OFFSET 15
#define POVD4H_MASK 0x00008000
#define POVD4L_OFFSET 14
#define POVD4L_MASK 0x00004000
#define POVD3H_OFFSET 13
#define POVD3H_MASK 0x00002000
#define POVD3L_OFFSET 12
#define POVD3L_MASK 0x00001000
#define POVD2H_OFFSET 11
#define POVD2H_MASK 0x00000800
#define POVD2L_OFFSET 10
#define POVD2L_MASK 0x00000400
#define POVD1H_OFFSET 9
#define POVD1H_MASK 0x00000200
#define POVD1L_OFFSET 8
#define POVD1L_MASK 0x00000100
#define POUT4H_OFFSET 7
#define POUT4H_MASK 0x00000080
#define POUT4L_OFFSET 6
#define POUT4L_MASK 0x00000040
#define POUT3H_OFFSET 5
#define POUT3H_MASK 0x00000020
#define POUT3L_OFFSET 4
#define POUT3L_MASK 0x00000010
#define POUT2H_OFFSET 3
#define POUT2H_MASK 0x00000008
#define POUT2L_OFFSET 2
#define POUT2L_MASK 0x00000004
#define POUT1H_OFFSET 1
#define POUT1H_MASK 0x00000002
#define POUT1L_OFFSET 0
#define POUT1L_MASK 0x00000001

//-----------------------------------
#define CFG_PDC1_ADDR 0x2C
#define PDC1_OFFSET 0
#define PDC1_MASK 0x0000FFFF

//-----------------------------------
#define CFG_PDC2_ADDR 0x30
#define PDC2_OFFSET 0
#define PDC2_MASK 0x0000FFFF

//-----------------------------------
#define CFG_PDC3_ADDR 0x34
#define PDC3_OFFSET 0
#define PDC3_MASK 0x0000FFFF

//-----------------------------------
#define CFG_PDC4_ADDR 0x38
#define PDC4_OFFSET 0
#define PDC4_MASK 0x0000FFFF

//-----------------------------------
#define CFG_POLAR_ADDR 0x3C
#define POLAR_OFFSET 0
#define POLAR_MASK 0x000000FF

//-----------------------------------
#define CFG_PTDIV_ADDR 0x40
#define PTDIV_OFFSET 0
#define PTDIV_MASK 0x0000FFFF

//-----------------------------------
#define CFG_PWM_INT_ENA_ADDR 0x44
#define PDC_MATCH_DOWN4_INT_ENA_OFFSET 16
#define PDC_MATCH_DOWN4_INT_ENA_MASK 0x00010000
#define PDC_MATCH_UP4_INT_ENA_OFFSET 15
#define PDC_MATCH_UP4_INT_ENA_MASK 0x00008000
#define PDC_MATCH_DOWN3_INT_ENA_OFFSET 14
#define PDC_MATCH_DOWN3_INT_ENA_MASK 0x00004000
#define PDC_MATCH_UP3_INT_ENA_OFFSET 13
#define PDC_MATCH_UP3_INT_ENA_MASK 0x00002000
#define PDC_MATCH_DOWN2_INT_ENA_OFFSET 12
#define PDC_MATCH_DOWN2_INT_ENA_MASK 0x00001000
#define PDC_MATCH_UP2_INT_ENA_OFFSET 11
#define PDC_MATCH_UP2_INT_ENA_MASK 0x00000800
#define PDC_MATCH_DOWN1_INT_ENA_OFFSET 10
#define PDC_MATCH_DOWN1_INT_ENA_MASK 0x00000400
#define PDC_MATCH_UP1_INT_ENA_OFFSET 9
#define PDC_MATCH_UP1_INT_ENA_MASK 0x00000200
#define ENC_UNF_ENA_OFFSET 8
#define ENC_UNF_ENA_MASK 0x00000100
#define ENC_OVF_ENA_OFFSET 7
#define ENC_OVF_ENA_MASK 0x00000080
#define CAP3_INT_ENA_OFFSET 6
#define CAP3_INT_ENA_MASK 0x00000040
#define CAP2_INT_ENA_OFFSET 5
#define CAP2_INT_ENA_MASK 0x00000020
#define CAP1_INT_ENA_OFFSET 4
#define CAP1_INT_ENA_MASK 0x00000010
#define FLTB_INT_ENA_OFFSET 3
#define FLTB_INT_ENA_MASK 0x00000008
#define FLTA_INT_ENA_OFFSET 2
#define FLTA_INT_ENA_MASK 0x00000004
#define PWM_EVENT_INT_ENA_OFFSET 1
#define PWM_EVENT_INT_ENA_MASK 0x00000002
#define PTIMER_INT_ENA_OFFSET 0
#define PTIMER_INT_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_PWM_INT_RAW_ADDR 0x48
#define PDC_MATCH_DOWN4_INT_RAW_OFFSET 16
#define PDC_MATCH_DOWN4_INT_RAW_MASK 0x00010000
#define PDC_MATCH_UP4_INT_RAW_OFFSET 15
#define PDC_MATCH_UP4_INT_RAW_MASK 0x00008000
#define PDC_MATCH_DOWN3_INT_RAW_OFFSET 14
#define PDC_MATCH_DOWN3_INT_RAW_MASK 0x00004000
#define PDC_MATCH_UP3_INT_RAW_OFFSET 13
#define PDC_MATCH_UP3_INT_RAW_MASK 0x00002000
#define PDC_MATCH_DOWN2_INT_RAW_OFFSET 12
#define PDC_MATCH_DOWN2_INT_RAW_MASK 0x00001000
#define PDC_MATCH_UP2_INT_RAW_OFFSET 11
#define PDC_MATCH_UP2_INT_RAW_MASK 0x00000800
#define PDC_MATCH_DOWN1_INT_RAW_OFFSET 10
#define PDC_MATCH_DOWN1_INT_RAW_MASK 0x00000400
#define PDC_MATCH_UP1_INT_RAW_OFFSET 9
#define PDC_MATCH_UP1_INT_RAW_MASK 0x00000200
#define ENC_UNF_INT_RAW_OFFSET 8
#define ENC_UNF_INT_RAW_MASK 0x00000100
#define ENC_OVF_INT_RAW_OFFSET 7
#define ENC_OVF_INT_RAW_MASK 0x00000080
#define CAP3_INT_RAW_OFFSET 6
#define CAP3_INT_RAW_MASK 0x00000040
#define CAP2_INT_RAW_OFFSET 5
#define CAP2_INT_RAW_MASK 0x00000020
#define CAP1_INT_RAW_OFFSET 4
#define CAP1_INT_RAW_MASK 0x00000010
#define FLTB_INT_RAW_OFFSET 3
#define FLTB_INT_RAW_MASK 0x00000008
#define FLTA_INT_RAW_OFFSET 2
#define FLTA_INT_RAW_MASK 0x00000004
#define PWM_EVENTINT_RAW_OFFSET 1
#define PWM_EVENTINT_RAW_MASK 0x00000002
#define PTIMER_INT_RAW_OFFSET 0
#define PTIMER_INT_RAW_MASK 0x00000001

//-----------------------------------
#define CFG_PWM_INT_ST_ADDR 0x4c
#define PDC_MATCH_DOWN4_INT_ST_OFFSET 16
#define PDC_MATCH_DOWN4_INT_ST_MASK 0x00010000
#define PDC_MATCH_UP4_INT_ST_OFFSET 15
#define PDC_MATCH_UP4_INT_ST_MASK 0x00008000
#define PDC_MATCH_DOWN3_INT_ST_OFFSET 14
#define PDC_MATCH_DOWN3_INT_ST_MASK 0x00004000
#define PDC_MATCH_UP3_INT_ST_OFFSET 13
#define PDC_MATCH_UP3_INT_ST_MASK 0x00002000
#define PDC_MATCH_DOWN2_INT_ST_OFFSET 12
#define PDC_MATCH_DOWN2_INT_ST_MASK 0x00001000
#define PDC_MATCH_UP2_INT_ST_OFFSET 11
#define PDC_MATCH_UP2_INT_ST_MASK 0x00000800
#define PDC_MATCH_DOWN1_INT_ST_OFFSET 10
#define PDC_MATCH_DOWN1_INT_ST_MASK 0x00000400
#define PDC_MATCH_UP1_INT_ST_OFFSET 9
#define PDC_MATCH_UP1_INT_ST_MASK 0x00000200
#define ENC_UNF_INT_ST_OFFSET 8
#define ENC_UNF_INT_ST_MASK 0x00000100
#define ENC_OVF_INT_ST_OFFSET 7
#define ENC_OVF_INT_ST_MASK 0x00000080
#define CAP3_INT_ST_OFFSET 6
#define CAP3_INT_ST_MASK 0x00000040
#define CAP2_INT_ST_OFFSET 5
#define CAP2_INT_ST_MASK 0x00000020
#define CAP1_INT_ST_OFFSET 4
#define CAP1_INT_ST_MASK 0x00000010
#define FLTB_INT_ST_OFFSET 3
#define FLTB_INT_ST_MASK 0x00000008
#define FLTA_INT_ST_OFFSET 2
#define FLTA_INT_ST_MASK 0x00000004
#define PWM_EVENTINT_ST_OFFSET 1
#define PWM_EVENTINT_ST_MASK 0x00000002
#define PTIMER_INT_ST_OFFSET 0
#define PTIMER_INT_ST_MASK 0x00000001

//-----------------------------------
#define CFG_PWM_INT_CLR_ADDR 0x50
#define PDC_MATCH_DOWN4_INT_CLR_OFFSET 16
#define PDC_MATCH_DOWN4_INT_CLR_MASK 0x00010000
#define PDC_MATCH_UP4_INT_CLR_OFFSET 15
#define PDC_MATCH_UP4_INT_CLR_MASK 0x00008000
#define PDC_MATCH_DOWN3_INT_CLR_OFFSET 14
#define PDC_MATCH_DOWN3_INT_CLR_MASK 0x00004000
#define PDC_MATCH_UP3_INT_CLR_OFFSET 13
#define PDC_MATCH_UP3_INT_CLR_MASK 0x00002000
#define PDC_MATCH_DOWN2_INT_CLR_OFFSET 12
#define PDC_MATCH_DOWN2_INT_CLR_MASK 0x00001000
#define PDC_MATCH_UP2_INT_CLR_OFFSET 11
#define PDC_MATCH_UP2_INT_CLR_MASK 0x00000800
#define PDC_MATCH_DOWN1_INT_CLR_OFFSET 10
#define PDC_MATCH_DOWN1_INT_CLR_MASK 0x00000400
#define PDC_MATCH_UP1_INT_CLR_OFFSET 9
#define PDC_MATCH_UP1_INT_CLR_MASK 0x00000200
#define ENC_UNF_INT_CLR_OFFSET 8
#define ENC_UNF_INT_CLR_MASK 0x00000100
#define ENC_OVF_INT_SCLR_OFFSET 7
#define ENC_OVF_INT_SCLR_MASK 0x00000080
#define CAP3_INT_CLR_OFFSET 6
#define CAP3_INT_CLR_MASK 0x00000040
#define CAP2_INT_CLR_OFFSET 5
#define CAP2_INT_CLR_MASK 0x00000020
#define CAP1_INT_CLR_OFFSET 4
#define CAP1_INT_CLR_MASK 0x00000010
#define FLTB_INT_CLR_OFFSET 3
#define FLTB_INT_CLR_MASK 0x00000008
#define FLTA_INT_CLR_OFFSET 2
#define FLTA_INT_CLR_MASK 0x00000004
#define PWM_EVENTINT_CLR_OFFSET 1
#define PWM_EVENTINT_CLR_MASK 0x00000002
#define PTIMER_INT_CLR_OFFSET 0
#define PTIMER_INT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_CAP_MOD_ADDR 0x54
#define CAP_ENA_OFFSET 15
#define CAP_ENA_MASK 0x00008000
#define CAP_POLAR_OFFSET 8
#define CAP_POLAR_MASK 0x00000700
#define CAP3_MOD_OFFSET 4
#define CAP3_MOD_MASK 0x00000030
#define CAP2_MOD_OFFSET 2
#define CAP2_MOD_MASK 0x0000000C
#define CAP1_MOD_OFFSET 0
#define CAP1_MOD_MASK 0x00000003

//-----------------------------------
#define CFG_CAP_ST_ADDR 0x58
#define CAP3_ST_OFFSET 4
#define CAP3_ST_MASK 0x00000030
#define CAP2_ST_OFFSET 2
#define CAP2_ST_MASK 0x0000000C
#define CAP1_ST_OFFSET 0
#define CAP1_ST_MASK 0x00000003

//-----------------------------------
#define CFG_CAP1_TIME_ADDR 0x5C
#define CAP1_TIME_OFFSET 0
#define CAP1_TIME_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAP2_TIME_ADDR 0x60
#define CAP2_TIME_OFFSET 0
#define CAP2_TIME_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CAP3_TIME_ADDR 0x64
#define CAP3_TIME_OFFSET 0
#define CAP3_TIME_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PWM_ST_ADDR 0x68
#define CAP3_IN_OFFSET 6
#define CAP3_IN_MASK 0x00000040
#define CAP2_IN_OFFSET 5
#define CAP2_IN_MASK 0x00000020
#define CAP1_IN_OFFSET 4
#define CAP1_IN_MASK 0x00000010
#define FLTB_OFFSET 3
#define FLTB_MASK 0x00000008
#define FLTA_OFFSET 2
#define FLTA_MASK 0x00000004
#define PWM_EVENT_OFFSET 1
#define PWM_EVENT_MASK 0x00000002
#define PTINT_OFFSET 0
#define PTINT_MASK 0x00000001

//-----------------------------------
#define CFG_PWM_ENC_MOD_ADDR 0x6C
#define ENC_ENA_OFFSET 15
#define ENC_ENA_MASK 0x00008000
#define ROT_DIR_OFFSET 2
#define ROT_DIR_MASK 0x00000004
#define ENC_POLAR_OFFSET 0
#define ENC_POLAR_MASK 0x00000003

//-----------------------------------
#define CFG_PWM_ENC_CNT_ADDR 0x70
#define PWM_ENC_CNT_OFFSET 0
#define PWM_ENC_CNT_MASK 0x0000FFFF

//-----------------------------------
#define CFG_PWM_MISC_CTL_ADDR 0x80
#define PWM_OE_OFFSET 8
#define PWM_OE_MASK 0x0000FF00
#define EVT1_SEL_OFFSET 4
#define EVT1_SEL_MASK 0x000000F0
#define EVT0_SEL_OFFSET 0
#define EVT0_SEL_MASK 0x0000000F

//HW module read/write macro
#define PWM_READ_REG(addr) SOC_READ_REG(PWM_BASEADDR + addr)
#define PWM_WRITE_REG(addr,value) SOC_WRITE_REG(PWM_BASEADDR + addr,value)