213 lines
6.3 KiB
C
213 lines
6.3 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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***************************************************************************/
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#ifndef __PHY_PHASE_H
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#define __PHY_PHASE_H
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#include "iot_config.h"
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#include "os_types.h"
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#include "phy_bb.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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PHY_PHASE_OVR_ALL = 0,
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PHY_PHASE_OVR_A = 1,
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PHY_PHASE_OVR_B = 2,
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PHY_PHASE_OVR_C = 3
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} PHY_PHASE_OVR_ID;
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typedef enum {
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PHY_TXRX_OVR_IDLE,
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PHY_TXRX_OVR_RX,
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PHY_TXRX_OVR_TX,
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PHY_TXRX_OVR_TXRX
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} PHY_TXRX_OVR_ID;
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#if K48_CCO_MULTI_CHANNEL_SELECT_ENABLE
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#define TX_EN_CMB_A (3 << 0)
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#define RX_EN_CMB_A (3 << 0)
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#define TX_EN_CMB_B (3 << 2)
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#define RX_EN_CMB_B (3 << 2)
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#define TX_EN_CMB_C (3 << 4)
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#define RX_EN_CMB_C (3 << 4)
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#else
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#define TX_EN_CMB_A (1 << 0)
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#define RX_EN_CMB_A (1 << 1)
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#define TX_EN_CMB_B (1 << 2)
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#define RX_EN_CMB_B (1 << 3)
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#define TX_EN_CMB_C (1 << 4)
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#define RX_EN_CMB_C (1 << 5)
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#endif
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/**
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*@brief phy_phase_ovr_set.
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*
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* force phase select with A/B/C/ALL,
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*
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*@param phase [A,B,C,ALL]
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*@param en [true/false]
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*@param mode [0:idle,1:rx,2:tx,3:txrx]
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*@exception [none.]
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*@return [none.]
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*/
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void phy_phase_ovr_set(PHY_PHASE_OVR_ID phase, bool_t en, PHY_TXRX_OVR_ID mode);
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/**
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*@brief phy_set_phase_overwrite() - set the tx&rx descriptor(0~3) map to
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* hw phase(phase A/B/C/ALL)
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*
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* set user protocol phase value map to kunlun chip's actual phase.
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* for example:
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* smart grid phase A = 1, then set desc1_to_hw_phae = HW_DESC_PHASE_A,
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* since then, set descriptor's tx_phase/rx_phase = PLC_PHASE_A(1), kunlun chip
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* will (tx&rx) work in phase A.
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* if is_enable != false, desc0_to_hw_phase/desc1_to_hw_phase/desc2_to_hw_phase/
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* desc3_to_hw_phase must be set to HW_DESC_PHASE_ALL/HW_DESC_PHASE_A/
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* HW_DESC_PHASE_B/ HW_DESC_PHASE_C one of the values.
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*
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*@param is_enable: is enable phase overwrite.
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* true - enable, false - disable
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*@param desc0_to_hw_phase: tx&rx descriptor value 0 map to hw phase, this value
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* must be HW_DESC_PHASE_ALL/HW_DESC_PHASE_A/
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* HW_DESC_PHASE_B/HW_DESC_PHASE_C
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*@param desc1_to_hw_phase: tx&rx descriptor value 1 map to hw phase, same as
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* desc0_to_hw_phase.
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*@param desc2_to_hw_phase: tx&rx descriptor value 2 map to hw phase, same as
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* desc0_to_hw_phase.
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*@param desc3_to_hw_phase: tx&rx descriptor value 3 map to hw phase, same as
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* desc0_to_hw_phase.
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*@return none
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*/
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void phy_set_phase_overwrite(bool_t is_enable,
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uint8_t desc0_to_hw_phase, uint8_t desc1_to_hw_phase,
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uint8_t desc2_to_hw_phase, uint8_t desc3_to_hw_phase);
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/**
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*@brief register_get_rx_phase_cb phy get mac rx phase cb.
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*@exception [none.]
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*@return [none.]
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*/
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void register_get_rx_phase_cb(mac_get_rx_phase_cb_t cb);
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/**
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*@brief phy_get_mac_rx_phase get phy callback value, rx phase.
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*@exception [none.]
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*@return [rx phase.]
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*/
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uint32_t phy_get_mac_rx_phase();
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/**
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*@brief phy_force_0_access_require
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* require the privilage to access force 0 register.
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*
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*@param void [void]
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*@exception [none.]
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*@return [none.]
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*/
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void phy_force_0_access_require();
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/**
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*@brief phy_force_0_access_release
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* release the privilage to access force 0 register.
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*
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*@param void [void]
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*@exception [none.]
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*@return [none.]
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*/
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void phy_force_0_access_release();
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/**
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*@brief phy_force_0_access_require_from_isr
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* require the privilage to access force 0 register from ISR.
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*
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*@param void [void]
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*@exception [none.]
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*@return uint32_t [require the privilage success or not]
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*/
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void phy_force_0_access_require_from_isr();
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/**
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*@brief phy_force_0_access_release_from_isr
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* release the privilage to access force 0 register from ISR.
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*
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*@param void [void]
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*@exception [none.]
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*@return uint32_t [release the privilage success or not]
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*/
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void phy_force_0_access_release_from_isr();
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/**
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*@brief phy_rx_phase_force_set
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* force phy rx phase from mac.
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*
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*@param enable [true or false]
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*@param hw_phase [ALL/A/B/C]
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*@exception [none.]
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*@return [none.]
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*/
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void phy_rx_phase_force_set(bool_t enable, uint8_t hw_phase);
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/**
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*@brief phy_rx_phase_force_set_on_dump
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* force phy rx phase from mac on dump mode.
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*
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*@param enable [true or false]
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*@param hw_phase [ALL/A/B/C]
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*@exception [none.]
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*@return [none.]
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*/
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void phy_rx_phase_force_set_on_dump(bool_t enable, uint8_t hw_phase);
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/**
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*@brief phy_get_rx_force_phase_val get rx force phase.
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*
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*@return [force phase]
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*/
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uint32_t phy_get_rx_force_phase_val();
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/**
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*@brief phy_get_rx_phase_force_en get rx force phase enable/disable.
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*
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*@return [0]
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*/
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uint32_t phy_get_rx_phase_force_en();
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/**
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* @brief phy_get_hw_phy_rx_phase_sel() - get phy rx phase select
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*
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* @param none
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*
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* @return phy rx phase num
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*/
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uint32_t phy_get_hw_phy_rx_phase_sel(void);
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/**
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* @brief enable/disable force phy tx
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*
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* @param is_enable: 0 - disable force phy tx
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* 1 - enable force phy tx
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*
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* @return none
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*/
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void phy_set_tx_force_enable(uint8_t is_enable);
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#ifdef __cplusplus
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}
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#endif
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#endif
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