529 lines
16 KiB
C
529 lines
16 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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/* os shim includes */
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#include "iot_config.h"
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#include "os_types.h"
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#include "os_utils.h"
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#include "hw_reg_api.h"
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#include "iot_errno_api.h"
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#include "iot_mem.h"
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/* driver includes */
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#include "phy_nf.h"
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#include "phy_bb.h"
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#include "os_timer_api.h"
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#include "phy_rxtd_reg.h"
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#include "mac_sys_reg.h"
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#include "iot_io.h"
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#include "hw_phy_api.h"
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#include "iot_system.h"
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#include "phy_ana.h"
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#include "granite_reg.h"
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#include "phy_status.h"
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#include "iot_adc.h"
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#include "phy_phase.h"
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#include "os_utils_api.h"
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#define CAL_NF_INVAILD_PHASE (PLC_PHASE_C + 1)
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typedef enum{
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CAL_NF_PHASE_STATE_IDLE = 0,
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CAL_NF_PHASE_STATE_ON_GOING = 1,
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CAL_NF_PHASE_STATE_COMPLETED = 2,
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CAL_NF_PHASE_STATE_FAIL = 3,
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} CAL_NF_PHASE_STATE;
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/* callback for phy call mac dsr function */
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phy_call_mac_dsr_cb_t phy_call_mac_dsr_cb = NULL;
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/* callback for phy call mac spur function */
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phy_call_mac_spur_cb_t phy_call_mac_spur_cb = NULL;
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/* callback for phy call mac scan band function */
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phy_call_mac_scan_band_cb_t phy_call_mac_scan_band_cb = NULL;
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void register_phy_call_mac_dsr_cb(phy_call_mac_dsr_cb_t cb)
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{
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phy_call_mac_dsr_cb = cb;
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}
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void register_phy_call_mac_spur_cb(phy_call_mac_spur_cb_t cb)
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{
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phy_call_mac_spur_cb = cb;
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}
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void register_phy_call_mac_scan_band_cb(phy_call_mac_scan_band_cb_t cb)
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{
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phy_call_mac_scan_band_cb = cb;
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}
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uint8_t IRAM_ATTR phy_agc_acc_dly_get(void)
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{
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uint32_t tmp = 0;
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uint8_t dly_exp = 0;
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/*
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* get 20ms dly for different acc step
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* 192/ 384/ 768/ 1536/ 3072/ 6144/
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*/
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tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
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uint32_t acc_step = REG_FIELD_GET(SW_AGC_ACC_STEP_HS, tmp);
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if (acc_step == 0) {
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dly_exp = 13;
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} else if (acc_step == 1) {
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dly_exp = 12;
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} else if (acc_step == 2) {
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dly_exp = 11;
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} else if (acc_step == 3) {
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dly_exp = 10;
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} else if (acc_step == 4) {
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dly_exp = 9;
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} else if (acc_step == 4) {
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dly_exp = 8;
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} else {
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dly_exp = 10;
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}
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return dly_exp;
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}
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#if PLC_SUPPORT_3PHASE_NF
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static void IRAM_ATTR phy_cal_nf_start()
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{
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/* get dly depend on ACC_STEP */
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uint8_t dly_exp = phy_agc_acc_dly_get();
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uint32_t tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_NOISE_CAL_ADDR);
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/* config dly */
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REG_FIELD_SET(SW_CAL_NOISE_DLY_EXP, tmp, dly_exp);
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/* trig again */
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REG_FIELD_SET(SW_CAL_NOISE_START, tmp, 1);
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PHY_RXTD_WRITE_REG(CFG_BB_AGC_NOISE_CAL_ADDR, tmp);
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/* clear cal nf cnt */
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g_phy_ctxt.dep.cal_nf_cnt = 0;
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}
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static uint32_t IRAM_ATTR phy_cal_nf_get_nf()
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{
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uint32_t tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_NOISE_CAL_ADDR);
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return REG_FIELD_GET(SW_CAL_NOISE_PWR, tmp);
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}
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static uint32_t IRAM_ATTR phy_cal_nf_check_done()
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{
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uint32_t tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_NOISE_CAL_ADDR);
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return REG_FIELD_GET(SW_CAL_NOISE_DONE, tmp);
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}
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static uint32_t IRAM_ATTR phy_cal_nf_get_phase()
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{
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uint32_t tmp = RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_0_ADDR);
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return REG_FIELD_GET(PHY_RX_PHASE_SEL, tmp);
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}
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void phy_cal_nf_systick_stop()
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{
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#define PHY_CAL_NF_REQUIRE_TIMEOUT 50
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if (!g_phy_cpu_share_ctxt.cal_3phase_nf_init) {
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return;
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}
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g_phy_ctxt.dep.cal_nf_stop = 1;
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uint32_t start_ms = os_boot_time32();
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uint32_t span = 0;
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do {
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span = os_boot_time32() - start_ms;
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} while (g_phy_ctxt.dep.cal_nf_stop != 0 &&
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span < PHY_CAL_NF_REQUIRE_TIMEOUT);
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if (g_phy_ctxt.dep.cal_nf_stop) {
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IOT_ASSERT(0);
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}
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}
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void phy_cal_nf_systick_start()
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{
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g_phy_ctxt.dep.cal_nf_triger = 1;
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}
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void phy_cal_nf_init()
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{
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g_phy_cpu_share_ctxt.cal_3phase_nf_init = 1;
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g_phy_ctxt.dep.cal_nf_stop = 0;
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g_phy_ctxt.dep.cal_nf_triger = 0;
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g_phy_ctxt.dep.cal_nf_running = 0;
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g_phy_cpu_share_ctxt.nf_phase[PLC_PHASE_A] = 0;
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g_phy_cpu_share_ctxt.nf_phase[PLC_PHASE_B] = 0;
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g_phy_cpu_share_ctxt.nf_phase[PLC_PHASE_C] = 0;
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g_phy_ctxt.dep.nf_cal_ms[PLC_PHASE_A] = 0;
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g_phy_ctxt.dep.nf_cal_ms[PLC_PHASE_B] = 0;
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g_phy_ctxt.dep.nf_cal_ms[PLC_PHASE_C] = 0;
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g_phy_ctxt.dep.cal_nf_last_phase = CAL_NF_INVAILD_PHASE;
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g_phy_ctxt.dep.cal_nf_phase_fsm[PLC_PHASE_A] = CAL_NF_PHASE_STATE_IDLE;
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g_phy_ctxt.dep.cal_nf_phase_fsm[PLC_PHASE_B] = CAL_NF_PHASE_STATE_IDLE;
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g_phy_ctxt.dep.cal_nf_phase_fsm[PLC_PHASE_C] = CAL_NF_PHASE_STATE_IDLE;
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}
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void IRAM_ATTR phy_cal_nf_fsm()
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{
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#define CAL_NF_TIMEOUT_MS 150
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uint32_t cur_phase, last_phase;
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uint8_t cal_nf = PHY_NF_RST_VAL;
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if (g_phy_ctxt.dep.cal_nf_stop) {
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g_phy_ctxt.dep.cal_nf_stop = 0;
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/* reset fsm */
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g_phy_ctxt.dep.cal_nf_triger = 0;
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g_phy_ctxt.dep.cal_nf_running = 0;
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return;
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}
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/* recalculate every second */
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if (g_phy_ctxt.dep.cal_nf_triger) {
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g_phy_ctxt.dep.cal_nf_triger = 0;
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g_phy_ctxt.dep.cal_nf_running = 1;
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g_phy_ctxt.dep.nf_cal_ms[PLC_PHASE_A] = 0;
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g_phy_ctxt.dep.nf_cal_ms[PLC_PHASE_B] = 0;
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g_phy_ctxt.dep.nf_cal_ms[PLC_PHASE_C] = 0;
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g_phy_ctxt.dep.cal_nf_last_phase = CAL_NF_INVAILD_PHASE;
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g_phy_ctxt.dep.cal_nf_phase_fsm[PLC_PHASE_A] = CAL_NF_PHASE_STATE_IDLE;
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g_phy_ctxt.dep.cal_nf_phase_fsm[PLC_PHASE_B] = CAL_NF_PHASE_STATE_IDLE;
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g_phy_ctxt.dep.cal_nf_phase_fsm[PLC_PHASE_C] = CAL_NF_PHASE_STATE_IDLE;
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}
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if (!g_phy_ctxt.dep.cal_nf_running) {
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return;
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}
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cur_phase = phy_cal_nf_get_phase();
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if (cur_phase == PLC_PHASE_ALL) {
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cur_phase = PLC_PHASE_A;
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}
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if (cur_phase > PLC_PHASE_C) {
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/* reset fsm */
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g_phy_ctxt.dep.cal_nf_triger = 0;
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g_phy_ctxt.dep.cal_nf_running = 0;
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return;
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}
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last_phase = g_phy_ctxt.dep.cal_nf_last_phase;
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if (CAL_NF_INVAILD_PHASE == last_phase) {
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if (CAL_NF_PHASE_STATE_COMPLETED ==
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g_phy_ctxt.dep.cal_nf_phase_fsm[cur_phase]) {
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return;
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}
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/* restart cal nf */
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phy_cal_nf_start();
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g_phy_ctxt.dep.cal_nf_phase_fsm[cur_phase] =
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CAL_NF_PHASE_STATE_ON_GOING;
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g_phy_ctxt.dep.cal_nf_last_phase = cur_phase;
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} else {
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if (last_phase != cur_phase) {
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g_phy_ctxt.dep.cal_nf_phase_fsm[last_phase] =
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CAL_NF_PHASE_STATE_FAIL;
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g_phy_ctxt.dep.cal_nf_last_phase = CAL_NF_INVAILD_PHASE;
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} else {
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if (phy_cal_nf_check_done()) {
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cal_nf = phy_cal_nf_get_nf();
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if (cal_nf != PHY_NF_RST_VAL) {
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g_phy_cpu_share_ctxt.nf_phase[cur_phase] = cal_nf;
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g_phy_ctxt.dep.nf_cal_ms[cur_phase] =
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g_phy_ctxt.dep.cal_nf_cnt;
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g_phy_ctxt.dep.cal_nf_phase_fsm[cur_phase] =
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CAL_NF_PHASE_STATE_COMPLETED;
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g_phy_ctxt.dep.cal_nf_last_phase = CAL_NF_INVAILD_PHASE;
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if (g_phy_ctxt.dep.cal_nf_phase_fsm[PLC_PHASE_A] ==
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CAL_NF_PHASE_STATE_COMPLETED &&
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g_phy_ctxt.dep.cal_nf_phase_fsm[PLC_PHASE_B] ==
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CAL_NF_PHASE_STATE_COMPLETED &&
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g_phy_ctxt.dep.cal_nf_phase_fsm[PLC_PHASE_C] ==
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CAL_NF_PHASE_STATE_COMPLETED) {
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g_phy_ctxt.dep.cal_nf_running = 0;
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}
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} else {
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/* restart cal nf */
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phy_cal_nf_start();
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}
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} else {
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g_phy_ctxt.dep.cal_nf_cnt++;
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if (g_phy_ctxt.dep.cal_nf_cnt >= CAL_NF_TIMEOUT_MS) {
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/* restart cal nf */
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phy_cal_nf_start();
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}
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}
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}
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}
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}
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void phy_cal_nf_on_3phase()
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{
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uint32_t tmp;
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uint8_t origin_hs, phase_idx, tmp_nf_192p;
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uint8_t rx_phase_force_en, rx_phase_force;
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/* save force value */
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tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
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rx_phase_force_en = REG_FIELD_GET(CFG_PHY_RX_PHASE_SEL_FORCE_EN, tmp);
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rx_phase_force = REG_FIELD_GET(CFG_PHY_RX_PHASE_SEL, tmp);
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/* 192 point */
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tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
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/* backup hs */
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origin_hs = (uint8_t)REG_FIELD_GET(SW_AGC_ACC_STEP_HS, tmp);
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REG_FIELD_SET(SW_AGC_ACC_STEP_HS, tmp, PHY_AGC_ACC_STEP_192P);
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PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR, tmp);
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for (phase_idx = PLC_PHASE_A; phase_idx <= PLC_PHASE_C; phase_idx++) {
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phy_rx_phase_force_set_on_dump(true, phase_idx);
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tmp_nf_192p = phy_rx_nf_by_rxtd_get(phy_agc_acc_dly_get());
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if (tmp_nf_192p != PHY_NF_RST_VAL) {
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g_phy_cpu_share_ctxt.nf_phase[phase_idx] = tmp_nf_192p;
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}
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}
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g_phy_ctxt.dep.nf =
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max(g_phy_cpu_share_ctxt.nf_phase[PLC_PHASE_A],
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max(g_phy_cpu_share_ctxt.nf_phase[PLC_PHASE_B],
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g_phy_cpu_share_ctxt.nf_phase[PLC_PHASE_C]));
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/* revert hs */
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REG_FIELD_SET(SW_AGC_ACC_STEP_HS, tmp, origin_hs);
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PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR, tmp);
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phy_rx_phase_force_set_on_dump(rx_phase_force_en, rx_phase_force);
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}
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#else
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void phy_cal_nf_systick_stop()
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{
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}
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void IRAM_ATTR phy_cal_nf_fsm()
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{
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}
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void phy_cal_nf_init()
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{
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g_phy_cpu_share_ctxt.cal_3phase_nf_init = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void phy_cal_nf_on_3phase()
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
void phy_cal_nf_systick_start()
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* PLC_SUPPORT_3PHASE_NF */
|
||
|
|
|
||
|
|
void phy_snr_cal_timer_handler()
|
||
|
|
{
|
||
|
|
#if HW_PLATFORM >= HW_PLATFORM_FPGA
|
||
|
|
static uint8_t cnt = 0;
|
||
|
|
iot_phy_sts_info_t total_sts = {0};
|
||
|
|
uint8_t rodata = 0;
|
||
|
|
uint32_t phy_status = 0;
|
||
|
|
|
||
|
|
if (g_phy_cpu_share_ctxt.cal_3phase_nf_init) {
|
||
|
|
g_phy_ctxt.dep.nf =
|
||
|
|
max(g_phy_cpu_share_ctxt.nf_phase[PLC_PHASE_A],
|
||
|
|
max(g_phy_cpu_share_ctxt.nf_phase[PLC_PHASE_B],
|
||
|
|
g_phy_cpu_share_ctxt.nf_phase[PLC_PHASE_C]));
|
||
|
|
|
||
|
|
/* print current noise floor */
|
||
|
|
iot_printf("[PHY] a_nf:%d, t_ms:%lu, b_nf:%d, t_ms:%lu, "
|
||
|
|
"c_nf:%d, t_ms:%d\n",
|
||
|
|
g_phy_cpu_share_ctxt.nf_phase[PLC_PHASE_A],
|
||
|
|
g_phy_ctxt.dep.nf_cal_ms[PLC_PHASE_A],
|
||
|
|
g_phy_cpu_share_ctxt.nf_phase[PLC_PHASE_B],
|
||
|
|
g_phy_ctxt.dep.nf_cal_ms[PLC_PHASE_B],
|
||
|
|
g_phy_cpu_share_ctxt.nf_phase[PLC_PHASE_C],
|
||
|
|
g_phy_ctxt.dep.nf_cal_ms[PLC_PHASE_C]);
|
||
|
|
|
||
|
|
phy_cal_nf_systick_start();
|
||
|
|
} else {
|
||
|
|
/* check cal noise done */
|
||
|
|
uint32_t tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_NOISE_CAL_ADDR);
|
||
|
|
if(REG_FIELD_GET(SW_CAL_NOISE_DONE,tmp))
|
||
|
|
{
|
||
|
|
/*121 is reset value, not valid value*/
|
||
|
|
if(REG_FIELD_GET(SW_CAL_NOISE_PWR,tmp) != PHY_NF_RST_VAL){
|
||
|
|
g_phy_ctxt.dep.nf = REG_FIELD_GET(SW_CAL_NOISE_PWR,tmp);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* update cpu share nf */
|
||
|
|
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
|
||
|
|
switch(REG_FIELD_GET(SW_AGC_ACC_STEP_HS, tmp))
|
||
|
|
{
|
||
|
|
case 0:
|
||
|
|
g_phy_cpu_share_ctxt.nf_192p = g_phy_ctxt.dep.nf;
|
||
|
|
break;
|
||
|
|
case 1:
|
||
|
|
g_phy_cpu_share_ctxt.nf_384p = g_phy_ctxt.dep.nf;
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
g_phy_cpu_share_ctxt.nf_768p = g_phy_ctxt.dep.nf;
|
||
|
|
break;
|
||
|
|
case 3:
|
||
|
|
g_phy_cpu_share_ctxt.nf_1536p = g_phy_ctxt.dep.nf;
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
g_phy_cpu_share_ctxt.nf_3072p = g_phy_ctxt.dep.nf;
|
||
|
|
break;
|
||
|
|
case 5:
|
||
|
|
g_phy_cpu_share_ctxt.nf_6144p = g_phy_ctxt.dep.nf;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* get dly depend on ACC_STEP */
|
||
|
|
uint32_t dly_exp = phy_agc_acc_dly_get();
|
||
|
|
|
||
|
|
/* config dly */
|
||
|
|
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_NOISE_CAL_ADDR);
|
||
|
|
REG_FIELD_SET(SW_CAL_NOISE_DLY_EXP, tmp, dly_exp);
|
||
|
|
PHY_RXTD_WRITE_REG(CFG_BB_AGC_NOISE_CAL_ADDR, tmp);
|
||
|
|
|
||
|
|
/* trig again */
|
||
|
|
tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_NOISE_CAL_ADDR);
|
||
|
|
REG_FIELD_SET(SW_CAL_NOISE_START, tmp, 1);
|
||
|
|
PHY_RXTD_WRITE_REG(CFG_BB_AGC_NOISE_CAL_ADDR, tmp);
|
||
|
|
|
||
|
|
/* print current noise floor */
|
||
|
|
iot_printf("[PHY] nf:%d, rx_phase:%d\n", g_phy_ctxt.dep.nf,
|
||
|
|
(RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_0_ADDR) &
|
||
|
|
PHY_RX_PHASE_SEL_MASK) >> PHY_RX_PHASE_SEL_OFFSET);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* print phy tx/rx cnt for each 4s */
|
||
|
|
if (phy_get_fw_mode() == MM_MODE && \
|
||
|
|
cnt >= 3) {
|
||
|
|
phy_sts_get(&total_sts);
|
||
|
|
iot_printf("mac tx ok:%d/4s, fc_ok:%d/4s, fc_err:%d/4s,", \
|
||
|
|
total_sts.mac_tx_ok_cnt, total_sts.fc_crc_ok_cnt, \
|
||
|
|
total_sts.fc_crc_fail_cnt);
|
||
|
|
|
||
|
|
iot_printf("pld_ok:%d/4s, pld fail:%d/4s, sync ok:%d/4s\r\n", \
|
||
|
|
total_sts.pld_crc_ok_cnt, total_sts.pld_crc_fail_cnt, \
|
||
|
|
total_sts.sync_ok_cnt);
|
||
|
|
|
||
|
|
uint8_t thd0_dft, thd1_dft;
|
||
|
|
phy_rxfd_pkt_det_thd_get(&thd0_dft, &thd1_dft);
|
||
|
|
iot_printf("rxfd_thd0:%d, rxfd_thd1:%d,", thd0_dft, thd1_dft);
|
||
|
|
|
||
|
|
phy_ana_i2c_read(CFG_ANA_TOP_REG_ADDR, &phy_status, &rodata);
|
||
|
|
iot_printf("ANA_TOP:%x ",phy_status);
|
||
|
|
|
||
|
|
iot_printf("F_0:%x F_1:%x F_2:%x ",\
|
||
|
|
RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR), \
|
||
|
|
RGF_MAC_READ_REG(CFG_PHY_FORCE_1_ADDR), \
|
||
|
|
RGF_MAC_READ_REG(CFG_PHY_FORCE_2_ADDR));
|
||
|
|
|
||
|
|
extern uint32_t mac_get_tx_rifs();
|
||
|
|
iot_printf("INTF_0:%x INTF_1:%x, agc_level:0x%x, rifs:%lu\r\n", \
|
||
|
|
RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_0_ADDR),\
|
||
|
|
RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_1_ADDR),\
|
||
|
|
PHY_RXTD_READ_REG(CFG_BB_AGC_GAIN_LEVEL_ADDR),
|
||
|
|
mac_get_tx_rifs());
|
||
|
|
|
||
|
|
phy_get_granite_reg();
|
||
|
|
|
||
|
|
#if IOT_SMART_CONFIG
|
||
|
|
/* just open update tempeerature on IOT preject */
|
||
|
|
iot_adc_temperature_val_update();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* update log cnt */
|
||
|
|
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_fc_ok_cnt += \
|
||
|
|
total_sts.fc_crc_ok_cnt;
|
||
|
|
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_fc_fail_cnt += \
|
||
|
|
total_sts.fc_crc_fail_cnt;
|
||
|
|
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_fc_fail_cnt_clr = \
|
||
|
|
total_sts.fc_crc_fail_cnt;
|
||
|
|
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_pld_ok_cnt += \
|
||
|
|
total_sts.pld_crc_ok_cnt;
|
||
|
|
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_pld_fail_cnt += \
|
||
|
|
total_sts.pld_crc_fail_cnt;
|
||
|
|
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_pkt_cnt += \
|
||
|
|
total_sts.sync_ok_cnt;
|
||
|
|
g_phy_ctxt.dep.phy_status.phy_tx_pkt_cnt += total_sts.mac_tx_ok_cnt;
|
||
|
|
g_phy_ctxt.dep.phy_status.phy_tx_pkt_cnt_clr = total_sts.mac_tx_ok_cnt;
|
||
|
|
|
||
|
|
cnt = 0;
|
||
|
|
} else {
|
||
|
|
cnt++;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* overstress handle */
|
||
|
|
phy_overstress_timer_handler();
|
||
|
|
|
||
|
|
if (phy_call_mac_scan_band_cb) {
|
||
|
|
phy_call_mac_scan_band_cb();
|
||
|
|
}
|
||
|
|
|
||
|
|
if (phy_call_mac_spur_cb) {
|
||
|
|
phy_call_mac_spur_cb();
|
||
|
|
}
|
||
|
|
|
||
|
|
if (os_boot_time32() > 60000) {
|
||
|
|
g_phy_cpu_share_ctxt.sym_num_fix_dis = 1;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
void phy_timer_handle()
|
||
|
|
{
|
||
|
|
if (phy_call_mac_dsr_cb) {
|
||
|
|
phy_call_mac_dsr_cb();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t phy_nf_timer_start()
|
||
|
|
{
|
||
|
|
uint32_t ret = ERR_FAIL;
|
||
|
|
|
||
|
|
#if HW_PLATFORM >= HW_PLATFORM_FPGA
|
||
|
|
if (g_phy_ctxt.dep.phy_snr_cal_timer == 0) {
|
||
|
|
#if IOT_DTEST_ONLY_SUPPORT == 0
|
||
|
|
g_phy_ctxt.dep.phy_snr_cal_timer = \
|
||
|
|
os_create_timer(PLC_PHY_COMMON_MID, true,
|
||
|
|
phy_timer_handle, NULL);
|
||
|
|
#else
|
||
|
|
g_phy_ctxt.dep.phy_snr_cal_timer = \
|
||
|
|
os_create_timer(PLC_PHY_COMMON_MID, true,
|
||
|
|
phy_snr_cal_timer_handler, NULL);
|
||
|
|
#endif
|
||
|
|
os_start_timer( \
|
||
|
|
g_phy_ctxt.dep.phy_snr_cal_timer, \
|
||
|
|
PHY_SNR_CAL_TIMER_PERIOD);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|