kunlun/plc/halphy/inc/phy_ana.h

/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/

#ifndef PHY_ANA_H
#define PHY_ANA_H
#include "plc_fr.h"
#include "os_types.h"

#ifdef __cplusplus
extern "C" {
#endif

#define PHY_ANA_HW_EN   (0xFFFFFFFF)

#define MAC_RX_BUF_SIZE (32*1024-1)
#define MAC_RX_SAMPLE_SIZE (31*1024)

typedef enum
{
    DA_B_PATH_PHY           = 0x00U,
    DA_B_PATH_TONE          = 0x01U,
}DA_B_PATH_CFG;

typedef enum
{
    ADC_MODE_FORCE          = 0x00U,
    ADC_MODE_AUTO           = 0x01U,
}ADC_MODE_CFG;

typedef enum {
    PHY_ENLIC_TXRX_IDLE,
    PHY_ENLIC_TXRX_RX,
    PHY_ENLIC_TXRX_TX,
    PHY_ENLIC_TXRX_LP
} PHY_ENLIC_TXRX_ID;

/* tx para */
typedef struct
{
    uint32_t buf_size;
    DA_B_PATH_CFG path;
    bool_t inv_en;
    bool_t tone_mode_en;
    uint32_t tone_num;
}DaTxPara_t;

/* rx para */
typedef struct
{
    /***/
    uint32_t buf_size;
    uint32_t sample_size;
    ADC_MODE_CFG mode;
    uint32_t thrd;
    bool_t clk_inv_en;
    bool_t dmsb_inv_en;
}DaRxPara_t;


void phy_ada_enable(uint32_t enable);
void phy_ada_clk_ratio_cfg(uint8_t data);
void phy_ada_tx_cfg(DaTxPara_t *tp);
void phy_ada_rx_cfg(DaRxPara_t *rp);
void phy_adc_en_cfg(uint32_t enable);
void phy_dac_en_cfg(uint32_t enable);
bool_t phy_adc_is_sample_done();
void phy_adc_thrd_cfg(uint32_t thrd);
void phy_adc_trig_en_cfg(uint32_t enable);
void warm_rst_ada();
uint32_t phy_adc_trig_addr_get();
uint32_t phy_ada_get_power_on();
void phy_adc_mode_cfg(ADC_MODE_CFG mode);
void phy_ana_top_reset_n_set(bool_t en);

/**
 *@brief enable_ada
 *
 * enable ada clock.
 *
 *@param enable             [clock enable/disable]
 *@exception                [none.]
 *@return                   [none.]
 */
void enable_ada(uint32_t enable);

/**
 *@brief phy_ana_init.
 *
 * initialize granite and geode depend on band id.
 *
 *@param band_id            [band index.]
 *@exception                [none.]
 *@return                   [none.]
 */
void phy_ana_init(uint32_t band_id);

/**
 *@brief phy_ana_tx_set.
 *
 * enable or disable analog TX and DAC.
 *
 *@param tx_en              [analog TX enable.]
 *@param dac_en             [analog DAC enable.]
 *@exception                [none.]
 *@return                   [none.]
 */
void phy_ana_tx_set(bool_t tx_en, bool_t dac_en);

/**
 *@brief phy_ana_rx_set.
 *
 * enable or disable analog RX and ADC.
 *
 *@param rx_en              [analog RX enable.]
 *@param adc_en             [analog ADC enable.]
 *@exception                [none.]
 *@return                   [none.]
 */
void phy_ana_rx_set(bool_t rx_en, bool_t adc_en);


/**
 *@brief phy_ana_sadc_enable.
 *
 * enable or disable sadc.
 *
 *@param enable             [analog RX enable.]
 *@return                   [none.]
 */
void phy_ana_sadc_enable(bool_t enable);

/**
 *@brief phy_ana_dfe_init.
 *
 * initialize bias switch auto for low power.
 *
 *@param none               [none.]
 *@return                   [none.]
 */

void phy_ana_dfe_init(void);

/**
 *@brief phy_ana_i2c_write.
 *
 * analog write interface.
 *
 *@param reg_id             [register index from 0 to 10.]
 *@param wdata              [the data will be written.]
 *@param mask               [mask for the data.]
 *@return                   [none.]
 */
void phy_ana_i2c_write(uint32_t reg_id, uint32_t wdata, uint32_t mask);

/**
 *@brief phy_ana_i2c_read.
 *
 * read the value from analog register.
 *
 *@param reg_id             [register index from 0 to 10.]
 *@param rdata              [the data read from analog with the reg_id.]
 *@param rodata             [extend status value.]
 *@return                   [none.]
 */
void phy_ana_i2c_read(uint32_t reg_id, uint32_t *rdata, uint8_t *rodata);

/**
 *@brief phy_ana_pga_gain_set.
 *
 * set the gpa gain value to analog register.
 *
 *@param val                [0-3.]
 *@return                   [none.]
 */
void phy_ana_pga_gain_set(uint32_t val);

/**
 *@brief phy_ana_pga_gain_get.
 *
 * get the gpa gain value
 *
 *@return                   [0-3.]
 */
uint32_t phy_ana_pga_gain_get(void);

/**
 *@brief phy_ana_tx_en.
 *
 * enable analog tx.
 *
 *@param en                 [true for enable and false for disable.]
 *@exception                [none.]
 *@return                   [none.]
 */
void phy_ana_tx_en(bool_t en);

/**
 *@brief phy_ana_rx_en.
 *
 * enable analog rx.
 *
 *@param en                 [true for enable and false for disable.]
 *@exception                [none.]
 *@return                   [none.]
 */
void phy_ana_rx_en(bool_t en);

/**
 *@brief phy_ana_enlic_en.
 *
 * enable analog enlic.
 *
 *@param val                [0:off, 1:rx, 2:tx, 3:loopback.]
 *@exception                [none.]
 *@return                   [none.]
 */
void phy_ana_enlic_en(uint8_t val);

/**
 *@brief phy_ana_filter_set.
 *
 * set analog filter value.
 *
 *@param val                [valid value from 7 to 63.]
 *@exception                [none.]
 *@return                   [none.]
 */
void phy_ana_filter_set(uint8_t val);

/**
 *@brief phy_ana_dbg_print.
 *
 * print analog debug register value.
 *
 *@param none               [none.]
 *@exception                [none.]
 *@return                   [none.]
 */
void phy_ana_dbg_print();

/**
 *@brief phy_sadc_pt_init.
 *
 * init sadc reg for pt.
 *
 *@param none               [none.]
 *@return                   [none.]
 */
void phy_sadc_pt_init();

void phy_ana_tx_comp_set(bool_t tx_en);
void phy_ana_tx_gpga_set(uint32_t data);
void phy_ana_rx_pgfloop_set(bool_t en);
void phy_ana_rx_fe_set(bool_t en);
void phy_ana_rx_fe_gpga_offset(uint32_t data);
void phy_ana_rx_fe_gpga(uint8_t data);
void phy_ana_rx_bq_qvalue(uint8_t data);
void phy_ana_rx_fe_gbq(uint8_t data);
void phy_ana_rx_fe_gpgf_offset(uint32_t data);
void phy_ana_rx_fe_gpgf(uint8_t data);
void phy_ana_rx_fe_hpfenord2_set(bool_t en);
void phy_ana_rx_fe_byphpf_set(bool_t en);
void phy_ana_rx_fe_pwdpgf_offset_set(bool_t en);
void phy_ana_rx_fe_pwdpga_offset_set(bool_t en);
void phy_ana_rx_glna(uint8_t data);
void phy_ana_top_tx_en(bool_t en);
void phy_ana_top_rx_en(bool_t en);
void phy_ana_top_adc_en(bool_t en);
void phy_ana_top_dac_en(bool_t en);
void phy_ana_top_enlic_rx_set(bool_t en);
void phy_ana_top_enlic_tx_set(bool_t en);
void phy_ana_rx_fe_selc_hpf(uint8_t data);
void phy_ana_rx_fe_selc_pgf_bq(uint8_t data);
void phy_ana_adc_set(bool_t en);
uint32_t phy_ana_tx_pgacomp_read();
void phy_ana_bias_ic0_cfg(uint32_t value);
void phy_ana_bias_ic1_cfg(uint32_t value);
void phy_ana_bias_ir0_cfg(uint32_t value);
void phy_ana_bias_ir1_cfg(uint32_t value);
/**
 *@brief phy_ana_hw_en_bitmap.
 *
 * init analog hw or sw control.
 *
 *@param value              [value 0 for sw contrl,0xFFFFFFFF for hw contrl]
 *@return                   [none.]
 */
void phy_ana_hw_en_bitmap(uint32_t value);

/**
 *@brief phy_ana_set_filter_init.  ana filter init
 *
 *@param band_id                   [band id]
 *@return                          [none.]
 */
void phy_ana_set_filter_init(uint32_t band_id);

#ifdef __cplusplus
}
#endif

#endif // !PHY_ANA_H