90 lines
3.0 KiB
C
90 lines
3.0 KiB
C
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//-----------------------------------
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#define CFG_AUDIO_FFT_RVER_ADDR 0x0000
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#define AUDIO_FFT_VER_OFFSET 0
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#define AUDIO_FFT_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_AUDIO_FFT_CMD_ADDR 0x0004
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#define SW_FFT_DONE_OFFSET 1
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#define SW_FFT_DONE_MASK 0x00000002
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#define SW_FFT_START_OFFSET 0
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#define SW_FFT_START_MASK 0x00000001
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//-----------------------------------
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#define CFG_AUDIO_FFT_CFG_ADDR 0x0008
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#define SW_FLT_RND_SEL_OFFSET 14
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#define SW_FLT_RND_SEL_MASK 0x0001C000
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#define SW_IS_SIGNED_EXT_OFFSET 13
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#define SW_IS_SIGNED_EXT_MASK 0x00002000
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#define SW_DATA_MODE_OFFSET 10
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#define SW_DATA_MODE_MASK 0x00001C00
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#define SW_DBG_ON_OFFSET 8
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#define SW_DBG_ON_MASK 0x00000100
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#define SW_CLK_FORCE_ON_OFFSET 7
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#define SW_CLK_FORCE_ON_MASK 0x00000080
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#define SW_IGNORE_FLT2I_ST_OFFSET 6
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#define SW_IGNORE_FLT2I_ST_MASK 0x00000040
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#define SW_ST_CLR_OFFSET 5
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#define SW_ST_CLR_MASK 0x00000020
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#define SW_IS_COMPLEX_OFFSET 4
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#define SW_IS_COMPLEX_MASK 0x00000010
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#define SW_IS_FFT_OFFSET 3
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#define SW_IS_FFT_MASK 0x00000008
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#define SW_FFT_SIZE_OFFSET 0
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#define SW_FFT_SIZE_MASK 0x00000007
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//-----------------------------------
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#define CFG_AUDIO_FFT_SHIFT_ADDR 0x000C
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#define SW_IN_LSH_BIT_SEL_OFFSET 13
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#define SW_IN_LSH_BIT_SEL_MASK 0x00006000
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#define SW_OUT_RSH_BIT_SEL_OFFSET 10
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#define SW_OUT_RSH_BIT_SEL_MASK 0x00001C00
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#define SW_FFT_STAGE4_SHIFT_OFFSET 8
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#define SW_FFT_STAGE4_SHIFT_MASK 0x00000300
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#define SW_FFT_STAGE3_SHIFT_OFFSET 6
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#define SW_FFT_STAGE3_SHIFT_MASK 0x000000C0
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#define SW_FFT_STAGE2_SHIFT_OFFSET 4
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#define SW_FFT_STAGE2_SHIFT_MASK 0x00000030
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#define SW_FFT_STAGE1_SHIFT_OFFSET 2
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#define SW_FFT_STAGE1_SHIFT_MASK 0x0000000C
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#define SW_FFT_STAGE0_SHIFT_OFFSET 0
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#define SW_FFT_STAGE0_SHIFT_MASK 0x00000003
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//-----------------------------------
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#define CFG_AUDIO_FLT_CFG_ADDR 0x0010
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#define SW_I2FLT_ST_OFFSET 24
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#define SW_I2FLT_ST_MASK 0xFF000000
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#define SW_FLT2I_ST_OFFSET 16
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#define SW_FLT2I_ST_MASK 0x00FF0000
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#define SW_FLTOUT_EXP_BIAS_OFFSET 8
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#define SW_FLTOUT_EXP_BIAS_MASK 0x0000FF00
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#define SW_FLTIN_EXP_BIAS_OFFSET 0
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#define SW_FLTIN_EXP_BIAS_MASK 0x000000FF
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//-----------------------------------
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#define CFG_FLT2I_REG0_ADDR 0x0020
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#define SW_FLT2I_REG0_OFFSET 0
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#define SW_FLT2I_REG0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_FLT2I_REG1_ADDR 0x0024
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#define SW_FLT2I_REG1_OFFSET 0
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#define SW_FLT2I_REG1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_FLT2I_REG2_ADDR 0x0028
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#define SW_FLT2I_REG2_OFFSET 0
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#define SW_FLT2I_REG2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_FLT2I_REG3_ADDR 0x002C
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#define SW_FLT2I_REG3_OFFSET 0
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#define SW_FLT2I_REG3_MASK 0xFFFFFFFF
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//HW module read/write macro
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#define AUDIO_FFT_RF0_READ_REG(addr) SOC_READ_REG(AUDIO_FFT_RF0_BASEADDR + addr)
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#define AUDIO_FFT_RF0_WRITE_REG(addr,value) SOC_WRITE_REG(AUDIO_FFT_RF0_BASEADDR + addr,value)
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#define AUDIO_FFT_RF1_READ_REG(addr) SOC_READ_REG(AUDIO_FFT_RF1_BASEADDR + addr)
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#define AUDIO_FFT_RF1_WRITE_REG(addr,value) SOC_WRITE_REG(AUDIO_FFT_RF1_BASEADDR + addr,value)
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