kunlun/rom/riscv2/inc/rom.h

/****************************************************************************
 
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
****************************************************************************/
#ifndef _ROM_H_
#define _ROM_H_

#include <stdint.h>

typedef  unsigned int UINT32;
typedef  unsigned short UINT16;

#ifndef NULL
#define NULL 0
#endif

#define REG32(a)		(*((volatile UINT32 *)(a)))

#ifndef BIT
#define BIT(b)  (1<<(b))
#endif

#define DEFAULT_PLL_FRQ     25000000

#define ROM_HASH_IV_LEN     16
#define ROM_AES_KEY_LEN     16

typedef struct vendor_config
{
    uint16_t checksum;
    uint8_t program_done;
    uint8_t test_en;
    uint8_t bond_valid;
    uint8_t sfc_cfg_valid;
    uint8_t mac[6];
    uint8_t gpio_sfc_clk;
    uint8_t gpio_sfc_cs;
    uint8_t gpio_sfc_d0;
    uint8_t gpio_sfc_d1;
    uint8_t gpio_sfc_d2;
    uint8_t gpio_sfc_d3;
    uint8_t flash_cmd_valid;
    uint8_t flash_cmd_read;
    uint8_t flash_cmd_enable;
    uint8_t flash_cmd_reset;
    uint8_t chip_id;
}vendor_config;

typedef struct user_config
{
    uint16_t checksum;
    uint8_t	 program_done;
    uint8_t	 cfg_valid;
    uint8_t	 uart_jtag0_enable;
    uint8_t	 uart_jtag1_enable;
    uint8_t	 jtag0_enable;
    uint8_t  jtag1_enable;
    uint8_t	 cpu0_efuse_rd_enable;
    uint8_t	 cpu1_flash_key_rd_enable;
    uint8_t  security_mode;
    uint8_t  boot_mode;
    uint8_t  flash_mode;
    uint8_t  download_enable;
    uint8_t  fastboot_enable;
    uint8_t  autobaud_enable;
}user_config;

typedef struct user_key
{
	uint8_t  hash_iv[ROM_HASH_IV_LEN];
	uint8_t  aes_key[ROM_AES_KEY_LEN];
}user_key;

typedef struct efuse_config
{
    vendor_config v_config;
    user_config u_config;
    user_key	u_key;
}efuse_config;

/* --------------------- APB --------------------------- */
typedef enum {
    APB_UART0		= BIT(0),
    APB_GPIO		= BIT(1),
    APB_GPTMR		= BIT(2),
    APB_GMTX        = BIT(2),
    APB_PIN         = BIT(6),
    APB_WDG0        = BIT(13),
    APB_UART_MEM    = BIT(16),
}APB_MODULE;


typedef enum {
    SEC_EMC        = BIT(0),
}SEC_GLB_MODULE;

typedef enum {
    PMU_EFUSE   = BIT(29),
}PMU_MODULE;

typedef enum {
    BOND_BOOT_MODE = BIT(0),
    BOND_BOOT_PMU = BIT(1),
    BOND_FAST_BOOT = BIT(4),
}BOND_OPT_MODULE;

typedef enum {
     AHB_ICACHE     = BIT(3),
     AHB_DCACHE     = BIT(4),
}AHB_GLB_MODULE;

/* For serial flash controller (SFC) */
#define SFC_BUFFER_SIZE	    256
#define SFC_BUFFER_ADDR	    0x61001000
#define REG_SFC_BASE 		0x61000100
#define REG_SFC_CMD0		(0x04 + REG_SFC_BASE)
#define REG_SFC_CMD1		(0x08 + REG_SFC_BASE)
#define REG_SFC_CFG1		(0x40 + REG_SFC_BASE)
#define REG_SFC_RDATA		(0x4C + REG_SFC_BASE)
#define REG_SFC_WDATA	    (0x50 + REG_SFC_BASE)
#define REG_SFC_DBG		    (0x54 + REG_SFC_BASE)
#define REG_SFC_SWM_CFG0	(0x80 + REG_SFC_BASE)
#define REG_SFC_SWM_CFG1	(0x84 + REG_SFC_BASE)
#define REG_SFC_SWM_CFG2	(0x88 + REG_SFC_BASE)
#define REG_SFC_CACHE_CFG0	(0x8C + REG_SFC_BASE)
#define REG_SFC_CACHE_CFG1	(0x90 + REG_SFC_BASE)
#define REG_SFC_WIM_CFG0	(0x94 + REG_SFC_BASE)
#define REG_SFC_WIM_CFG1	(0x98 + REG_SFC_BASE)
#define REG_SFC_RSM_CFG0	(0x9C + REG_SFC_BASE)
#define REG_SFC_RSM_CFG1	(0xA0 + REG_SFC_BASE)
#define REG_SFC_SUS_CFG0	(0xA4 + REG_SFC_BASE)
#define REG_SFC_SUS_CFG1	(0xA8 + REG_SFC_BASE)


typedef struct
{
       UINT16 dTpye;
       UINT16 iTpye;
       UINT32 sOff;
       UINT32 iLen;
}flTb;

#endif