87 lines
2.4 KiB
C
87 lines
2.4 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#ifndef _CLK_H
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#define _CLK_H
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#if HW_PLATFORM > HW_PLATFORM_SIMU
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#include "clk_hw.h"
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#else
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typedef enum {
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CPU_FREQ_25M = 0,
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CPU_FREQ_75M,
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CPU_FREQ_150M,
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CPU_FREQ_160M,
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CPU_FREQ_170M,
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CPU_FREQ_180M,
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CPU_FREQ_200M,
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CPU_FREQ_MAX,
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} CPU_FREQ;
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#endif
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extern uint32_t g_cpu_freq;
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int clk_core_freq_set(uint32_t freq);
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uint32_t clk_core_freq_get();
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void clk_i2s_dev_set(uint32_t div, uint32_t m, uint32_t n);
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void clk_core_freq_slip_25m_set();
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void clk_core_freq_slip_150m_set();
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uint32_t clk_pwm_src_freq_get(void);
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void clk_pwm_src_freq_set(uint32_t frq);
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/**
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* @brief clk_core_init() - set clock source and frequency division coefficient.
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* @return none.
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*/
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void clk_core_init(void);
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/* Clock source type */
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#define CLK_TYPE_XTL 1
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#define CLK_TYPE_APB 2
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#define CLK_TYPE_MPLL 3
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#define CLK_TYPE_WPHY_FCLK 4
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#define CLK_TYPE_PLC_ADC 5
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#define CLK_TYPE_PLC_DAC 6
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#define CLK_TYPE_TPID 7
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#define CLK_TYPE_METER 8
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#define CLK_TYPE_AHB 9
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#define CLK_TYPE_PLC_50 10
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#define CLK_TYPE_PLC_75 11
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#define CLK_TYPE_PLC_150 12
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/* Frequency division coefficient */
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#define CLK_DIV1 0x0
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#define CLK_DIV2 0x1
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#define CLK_DIV4 0x3
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#define CLK_DIV8 0x7
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#define CLK_DIV16 0xF
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/*
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* Type : 1-XTL, 2-APB, 3-MPLL, 4-WPHY_FCLK, 5-PLC_ADC, 6-PLC_DAC, 7-TPID,
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* 8-METER, 9-AHB, 10-PLC_50, 11-PLC_75, 12-PLC_150.
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* div : 0x0 - DIV1, 0x1 - DIV2, 0x3 - DIV4, 0x7 - DIV8, 0xF - DIV16.
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* gpio : gpio to output the selected clock.
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*/
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uint32_t clk_debug_output_set(uint32_t type, uint32_t div, uint32_t gpio);
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#endif //_CLK_H
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