kunlun/inc/hw/reg/riscv2/15/sec_glb_rf.h

//-----------------------------------
#define CFG_SEC_RVER_ADDR 0x0000
#define SEC_RF_VER_OFFSET 0
#define SEC_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SEC_GLB_ENA_ADDR 0x0004
#define RV5_CORE1_BTB_EB_OFFSET 8
#define RV5_CORE1_BTB_EB_MASK 0x00000100
#define MBOX_EB_OFFSET 7
#define MBOX_EB_MASK 0x00000080
#define RV5_CORE1_EB_OFFSET 6
#define RV5_CORE1_EB_MASK 0x00000040
#define INTC1_EB_OFFSET 5
#define INTC1_EB_MASK 0x00000020
#define WDG1_EB_OFFSET 4
#define WDG1_EB_MASK 0x00000010
#define GTMR1_EB_OFFSET 3
#define GTMR1_EB_MASK 0x00000008
#define SEC_EB_OFFSET 1
#define SEC_EB_MASK 0x00000002
#define EMC_EB_OFFSET 0
#define EMC_EB_MASK 0x00000001

//-----------------------------------
#define CFG_SEC_GLB_RST_ADDR 0x0008
#define RV5_CORE1_SOFT_RST_LEN_OFFSET 25
#define RV5_CORE1_SOFT_RST_LEN_MASK 0xFE000000
#define RV5_CORE1_SOFT_RST_P_OFFSET 24
#define RV5_CORE1_SOFT_RST_P_MASK 0x01000000
#define CHIP_SOFT_RST_OFFSET 8
#define CHIP_SOFT_RST_MASK 0x00000100
#define MBOX_SOFT_RST_OFFSET 7
#define MBOX_SOFT_RST_MASK 0x00000080
#define RV5_CORE1_SOFT_RST_OFFSET 6
#define RV5_CORE1_SOFT_RST_MASK 0x00000040
#define INTC1_SOFT_RST_OFFSET 5
#define INTC1_SOFT_RST_MASK 0x00000020
#define WDG1_SOFT_RST_OFFSET 4
#define WDG1_SOFT_RST_MASK 0x00000010
#define GTMR1_SOFT_RST_OFFSET 3
#define GTMR1_SOFT_RST_MASK 0x00000008
#define SEC_SOFT_RST_OFFSET 1
#define SEC_SOFT_RST_MASK 0x00000002
#define EMC_SOFT_RST_OFFSET 0
#define EMC_SOFT_RST_MASK 0x00000001

//-----------------------------------
#define CFG_SEC_LP_CTRL_ADDR 0x000C
#define CORE1_INT_MASK_OFFSET 4
#define CORE1_INT_MASK_MASK 0x00000010
#define SEC_DEEP_SLEEP_ENA_OFFSET 3
#define SEC_DEEP_SLEEP_ENA_MASK 0x00000008
#define RV5_CORE1_SLEEP_ENA_OFFSET 2
#define RV5_CORE1_SLEEP_ENA_MASK 0x00000004
#define FORCE_SEC_DEEP_SLEEP_OFFSET 1
#define FORCE_SEC_DEEP_SLEEP_MASK 0x00000002
#define FORCE_RV5_CORE1_STOP_OFFSET 0
#define FORCE_RV5_CORE1_STOP_MASK 0x00000001

//-----------------------------------
#define CFG_SMP_IC1_CFG_ADDR 0x0010
#define CORE2_IC1_REMAP_ENA_OFFSET 1
#define CORE2_IC1_REMAP_ENA_MASK 0x00000002
#define CORE0_IC1_REMAP_ENA_OFFSET 0
#define CORE0_IC1_REMAP_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_MTX_MST_BURST_CFG_ADDR 0x0014
#define MST_BURST_ENA_OFFSET 0
#define MST_BURST_ENA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_PERI_DEV_CFG_ADDR 0x0018
#define CLK_REG_WR_ENA_OFFSET 1
#define CLK_REG_WR_ENA_MASK 0x00000002
#define PIN_REG_WR_ENA_OFFSET 0
#define PIN_REG_WR_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_WDG_RST_EN_ADDR 0x001C
#define WDG2_CHIP_RST_ENA_OFFSET 6
#define WDG2_CHIP_RST_ENA_MASK 0x00000040
#define WDG1_CHIP_RST_ENA_OFFSET 5
#define WDG1_CHIP_RST_ENA_MASK 0x00000020
#define WDG0_CHIP_RST_ENA_OFFSET 4
#define WDG0_CHIP_RST_ENA_MASK 0x00000010
#define WDG2_DIG_RST_ENA_OFFSET 2
#define WDG2_DIG_RST_ENA_MASK 0x00000004
#define WDG1_DIG_RST_ENA_OFFSET 1
#define WDG1_DIG_RST_ENA_MASK 0x00000002
#define WDG0_DIG_RST_ENA_OFFSET 0
#define WDG0_DIG_RST_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_CPU1_START_PC_ADDR 0x004c
#define CORE1_START_PC_OFFSET 0
#define CORE1_START_PC_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MTX_MST0_ACC_ADDR 0x0060
#define MST0_ACC_ENA_OFFSET 0
#define MST0_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST1_ACC_ADDR 0x0064
#define MST1_ACC_ENA_OFFSET 0
#define MST1_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST2_ACC_ADDR 0x0068
#define MST2_ACC_ENA_OFFSET 0
#define MST2_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST3_ACC_ADDR 0x006C
#define MST3_ACC_ENA_OFFSET 0
#define MST3_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST4_ACC_ADDR 0x0070
#define MST4_ACC_ENA_OFFSET 0
#define MST4_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST5_ACC_ADDR 0x0074
#define MST5_ACC_ENA_OFFSET 0
#define MST5_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST6_ACC_ADDR 0x0078
#define MST6_ACC_ENA_OFFSET 0
#define MST6_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST7_ACC_ADDR 0x007c
#define MST7_ACC_ENA_OFFSET 0
#define MST7_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST8_ACC_ADDR 0x0080
#define MST8_ACC_ENA_OFFSET 0
#define MST8_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST9_ACC_ADDR 0x0084
#define MST9_ACC_ENA_OFFSET 0
#define MST9_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST10_ACC_ADDR 0x0088
#define MST10_ACC_ENA_OFFSET 0
#define MST10_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST11_ACC_ADDR 0x008c
#define MST11_ACC_ENA_OFFSET 0
#define MST11_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST12_ACC_ADDR 0x0090
#define MST12_ACC_ENA_OFFSET 0
#define MST12_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST13_ACC_ADDR 0x0094
#define MST13_ACC_ENA_OFFSET 0
#define MST13_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST14_ACC_ADDR 0x0098
#define MST14_ACC_ENA_OFFSET 0
#define MST14_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST15_ACC_ADDR 0x009c
#define MST15_ACC_ENA_OFFSET 0
#define MST15_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST16_ACC_ADDR 0x00a0
#define MST16_ACC_ENA_OFFSET 0
#define MST16_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST17_ACC_ADDR 0x00a4
#define MST17_ACC_ENA_OFFSET 0
#define MST17_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST18_ACC_ADDR 0x00a8
#define MST18_ACC_ENA_OFFSET 0
#define MST18_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST19_ACC_ADDR 0x00ac
#define MST19_ACC_ENA_OFFSET 0
#define MST19_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST20_ACC_ADDR 0x00b0
#define MST20_ACC_ENA_OFFSET 0
#define MST20_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST21_ACC_ADDR 0x00b4
#define MST21_ACC_ENA_OFFSET 0
#define MST21_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_MTX_MST22_ACC_ADDR 0x00b8
#define MST22_ACC_ENA_OFFSET 0
#define MST22_ACC_ENA_MASK 0x00FFFFFF

//-----------------------------------
#define CFG_DIG_CPU0_IEXPT_CFG0_ADDR 0x00bC
#define RV5_CORE1_I_EXPT_MASK_OFFSET 24
#define RV5_CORE1_I_EXPT_MASK_MASK 0x01000000
#define RV5_CORE1_I_ACCESS_EN_OFFSET 0
#define RV5_CORE1_I_ACCESS_EN_MASK 0x0001FFFF

//-----------------------------------
#define CFG_DIG_CPU0_DEXPT_CFG0_ADDR 0x00C0
#define RV5_CORE1_D_EXPT_MASK_OFFSET 24
#define RV5_CORE1_D_EXPT_MASK_MASK 0x3F000000
#define RV5_CORE1_D_ACCESS_EN_OFFSET 0
#define RV5_CORE1_D_ACCESS_EN_MASK 0x0001FFFF

//-----------------------------------
#define CFG_SEC_GLB_ENA_SET_ADDR 0x00D0
#define RV5_CORE1_BTB_EB_SET_OFFSET 8
#define RV5_CORE1_BTB_EB_SET_MASK 0x00000100
#define MBOX_EB_SET_OFFSET 7
#define MBOX_EB_SET_MASK 0x00000080
#define RV5_CORE1_EB_SET_OFFSET 6
#define RV5_CORE1_EB_SET_MASK 0x00000040
#define INTC1_EB_SET_OFFSET 5
#define INTC1_EB_SET_MASK 0x00000020
#define WDG1_EB_SET_OFFSET 4
#define WDG1_EB_SET_MASK 0x00000010
#define GTMR1_EB_SET_OFFSET 3
#define GTMR1_EB_SET_MASK 0x00000008
#define SEC_EB_SET_OFFSET 1
#define SEC_EB_SET_MASK 0x00000002
#define EMC_EB_SET_OFFSET 0
#define EMC_EB_SET_MASK 0x00000001

//-----------------------------------
#define CFG_SEC_GLB_ENA_CLR_ADDR 0x00D4
#define RV5_CORE1_BTB_EB_CLR_OFFSET 8
#define RV5_CORE1_BTB_EB_CLR_MASK 0x00000100
#define MBOX_EB_CLR_OFFSET 7
#define MBOX_EB_CLR_MASK 0x00000080
#define RV5_CORE1_EB_CLR_OFFSET 6
#define RV5_CORE1_EB_CLR_MASK 0x00000040
#define INTC1_EB_CLR_OFFSET 5
#define INTC1_EB_CLR_MASK 0x00000020
#define WDG1_EB_CLR_OFFSET 4
#define WDG1_EB_CLR_MASK 0x00000010
#define GTMR1_EB_CLR_OFFSET 3
#define GTMR1_EB_CLR_MASK 0x00000008
#define SEC_EB_CLR_OFFSET 1
#define SEC_EB_CLR_MASK 0x00000002
#define EMC_EB_CLR_OFFSET 0
#define EMC_EB_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_SEC_GLB_RST_SET_ADDR 0x00D8
#define CHIP_SOFT_RST_SET_OFFSET 8
#define CHIP_SOFT_RST_SET_MASK 0x00000100
#define MBOX_SOFT_RST_SET_OFFSET 7
#define MBOX_SOFT_RST_SET_MASK 0x00000080
#define RV5_CORE1_SOFT_RST_SET_OFFSET 6
#define RV5_CORE1_SOFT_RST_SET_MASK 0x00000040
#define INTC1_SOFT_RST_SET_OFFSET 5
#define INTC1_SOFT_RST_SET_MASK 0x00000020
#define WDG1_SOFT_RST_SET_OFFSET 4
#define WDG1_SOFT_RST_SET_MASK 0x00000010
#define GTMR1_SOFT_RST_SET_OFFSET 3
#define GTMR1_SOFT_RST_SET_MASK 0x00000008
#define SEC_SOFT_RST_SET_OFFSET 1
#define SEC_SOFT_RST_SET_MASK 0x00000002
#define EMC_SOFT_RST_SET_OFFSET 0
#define EMC_SOFT_RST_SET_MASK 0x00000001

//-----------------------------------
#define CFG_SEC_GLB_RST_CLR_ADDR 0x00DC
#define CHIP_SOFT_RST_CLR_OFFSET 8
#define CHIP_SOFT_RST_CLR_MASK 0x00000100
#define MBOX_SOFT_RST_CLR_OFFSET 7
#define MBOX_SOFT_RST_CLR_MASK 0x00000080
#define RV5_CORE1_SOFT_RST_CLR_OFFSET 6
#define RV5_CORE1_SOFT_RST_CLR_MASK 0x00000040
#define INTC1_SOFT_RST_CLR_OFFSET 5
#define INTC1_SOFT_RST_CLR_MASK 0x00000020
#define WDG1_SOFT_RST_CLR_OFFSET 4
#define WDG1_SOFT_RST_CLR_MASK 0x00000010
#define GTMR1_SOFT_RST_CLR_OFFSET 3
#define GTMR1_SOFT_RST_CLR_MASK 0x00000008
#define SEC_SOFT_RST_CLR_OFFSET 1
#define SEC_SOFT_RST_CLR_MASK 0x00000002
#define EMC_SOFT_RST_CLR_OFFSET 0
#define EMC_SOFT_RST_CLR_MASK 0x00000001

//HW module read/write macro
#define SEC_GLB_RF_READ_REG(addr) SOC_READ_REG(SEC_GLB_RF_BASEADDR + addr)
#define SEC_GLB_RF_WRITE_REG(addr,value) SOC_WRITE_REG(SEC_GLB_RF_BASEADDR + addr,value)