292 lines
8.5 KiB
C
292 lines
8.5 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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***************************************************************************/
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#include "hw_reg_api.h"
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#include "phy_phase.h"
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#include "phy_bb.h"
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#include "phy_dfe_reg.h"
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#include "mac_sys_reg.h"
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#include "hw_desc.h"
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#include "os_task.h"
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#include "hw_phy_api.h"
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void phy_phase_ovr_set(PHY_PHASE_OVR_ID phase, bool_t en, PHY_TXRX_OVR_ID mode)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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/* enable a/b/c and tx & rx*/
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tmp = PHY_DFE_READ_REG(CFG_BB_DFE_OPTION_0_ADDR);
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switch(phase)
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{
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case PHY_PHASE_OVR_A:
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REG_FIELD_SET(SW_ENLIC_A_OVR_EN, tmp, en);
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REG_FIELD_SET(SW_ENLIC_A_OVR, tmp, mode);
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break;
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case PHY_PHASE_OVR_B:
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REG_FIELD_SET(SW_ENLIC_B_OVR_EN, tmp, en);
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REG_FIELD_SET(SW_ENLIC_B_OVR, tmp, mode);
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break;
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case PHY_PHASE_OVR_C:
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REG_FIELD_SET(SW_ENLIC_C_OVR_EN, tmp, en);
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REG_FIELD_SET(SW_ENLIC_C_OVR, tmp, mode);
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break;
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case PHY_PHASE_OVR_ALL:
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REG_FIELD_SET(SW_ENLIC_A_OVR_EN, tmp, en);
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REG_FIELD_SET(SW_ENLIC_A_OVR, tmp, mode);
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REG_FIELD_SET(SW_ENLIC_B_OVR_EN, tmp, en);
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REG_FIELD_SET(SW_ENLIC_B_OVR, tmp, mode);
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REG_FIELD_SET(SW_ENLIC_C_OVR_EN, tmp, en);
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REG_FIELD_SET(SW_ENLIC_C_OVR, tmp, mode);
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break;
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default:
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break;
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}
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PHY_DFE_WRITE_REG(CFG_BB_DFE_OPTION_0_ADDR, tmp);
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#else
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(void)phase;
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(void)en;
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(void)mode;
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#endif
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}
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void register_get_rx_phase_cb(mac_get_rx_phase_cb_t cb)
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{
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#if IOT_DTEST_ONLY_SUPPORT == 0
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g_phy_cpu_share_ctxt.rx_phase_cb = cb;
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#endif
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}
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uint32_t IRAM_ATTR phy_get_mac_rx_phase()
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{
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#if IOT_DTEST_ONLY_SUPPORT == 0
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if (g_phy_cpu_share_ctxt.rx_phase_cb) {
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return g_phy_cpu_share_ctxt.rx_phase_cb();
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} else {
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return 0;
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}
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#else
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return 0;
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#endif
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}
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static inline uint8_t hw_phase_map_to_rx_cmb(uint8_t hw_phase)
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{
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switch (hw_phase)
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{
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case HW_DESC_PHASE_A:
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return RX_EN_CMB_A;
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case HW_DESC_PHASE_B:
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return RX_EN_CMB_B;
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case HW_DESC_PHASE_C:
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return RX_EN_CMB_C;
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case HW_DESC_PHASE_ALL:
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return (RX_EN_CMB_A | RX_EN_CMB_B | RX_EN_CMB_C);
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default:
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return 0;
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}
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}
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static inline uint8_t hw_phase_map_to_tx_cmb(uint8_t hw_phase)
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{
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switch (hw_phase)
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{
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case HW_DESC_PHASE_A:
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return TX_EN_CMB_A;
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case HW_DESC_PHASE_B:
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return TX_EN_CMB_B;
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case HW_DESC_PHASE_C:
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return TX_EN_CMB_C;
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case HW_DESC_PHASE_ALL:
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return (TX_EN_CMB_A | TX_EN_CMB_B | TX_EN_CMB_C);
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default:
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return 0;
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}
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}
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void phy_set_phase_overwrite(bool_t is_enable,
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uint8_t desc0_to_hw_phase, uint8_t desc1_to_hw_phase,
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uint8_t desc2_to_hw_phase, uint8_t desc3_to_hw_phase)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp_tx, tmp_rx;
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tmp_tx = PHY_DFE_READ_REG(CFG_BB_ENLIC_TBL_0_ADDR);
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tmp_rx = PHY_DFE_READ_REG(CFG_BB_ENLIC_TBL_1_ADDR);
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if (is_enable) {
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if ((HW_DESC_PHASE_ALL < desc0_to_hw_phase) && \
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(HW_DESC_PHASE_ALL < desc1_to_hw_phase) && \
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(HW_DESC_PHASE_ALL < desc2_to_hw_phase) && \
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(HW_DESC_PHASE_ALL < desc3_to_hw_phase)) {
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/* set rx default */
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REG_FIELD_SET(SW_RX_PHASE_TBL_0, tmp_rx, \
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(RX_EN_CMB_A | RX_EN_CMB_B | RX_EN_CMB_C));
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REG_FIELD_SET(SW_RX_PHASE_TBL_1, tmp_rx, RX_EN_CMB_A);
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REG_FIELD_SET(SW_RX_PHASE_TBL_2, tmp_rx, RX_EN_CMB_B);
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REG_FIELD_SET(SW_RX_PHASE_TBL_3, tmp_rx, RX_EN_CMB_C);
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/* set tx default */
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REG_FIELD_SET(SW_TX_PHASE_TBL_0, tmp_tx, \
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(TX_EN_CMB_A | TX_EN_CMB_B | TX_EN_CMB_C));
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REG_FIELD_SET(SW_TX_PHASE_TBL_1, tmp_tx, TX_EN_CMB_A);
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REG_FIELD_SET(SW_TX_PHASE_TBL_2, tmp_tx, TX_EN_CMB_B);
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REG_FIELD_SET(SW_TX_PHASE_TBL_3, tmp_tx, TX_EN_CMB_C);
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/*enable tx/rx phase overwrite*/
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REG_FIELD_SET(SW_CFG_PHASE_EN, tmp_tx, true);
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} else {
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/* set rx value */
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REG_FIELD_SET(SW_RX_PHASE_TBL_0, tmp_rx, \
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hw_phase_map_to_rx_cmb(desc0_to_hw_phase));
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REG_FIELD_SET(SW_RX_PHASE_TBL_1, tmp_rx, \
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hw_phase_map_to_rx_cmb(desc1_to_hw_phase));
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REG_FIELD_SET(SW_RX_PHASE_TBL_2, tmp_rx, \
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hw_phase_map_to_rx_cmb(desc2_to_hw_phase));
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REG_FIELD_SET(SW_RX_PHASE_TBL_3, tmp_rx, \
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hw_phase_map_to_rx_cmb(desc3_to_hw_phase));
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/* set tx value */
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REG_FIELD_SET(SW_TX_PHASE_TBL_0, tmp_tx, \
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hw_phase_map_to_tx_cmb(desc0_to_hw_phase));
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REG_FIELD_SET(SW_TX_PHASE_TBL_1, tmp_tx, \
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hw_phase_map_to_tx_cmb(desc1_to_hw_phase));
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REG_FIELD_SET(SW_TX_PHASE_TBL_2, tmp_tx, \
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hw_phase_map_to_tx_cmb(desc2_to_hw_phase));
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REG_FIELD_SET(SW_TX_PHASE_TBL_3, tmp_tx, \
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hw_phase_map_to_tx_cmb(desc3_to_hw_phase));
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/*enable tx/rx phase overwrite*/
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REG_FIELD_SET(SW_CFG_PHASE_EN, tmp_tx, true);
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}
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} else {
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REG_FIELD_SET(SW_CFG_PHASE_EN, tmp_tx, false);
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}
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PHY_DFE_WRITE_REG(CFG_BB_ENLIC_TBL_0_ADDR, tmp_tx);
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PHY_DFE_WRITE_REG(CFG_BB_ENLIC_TBL_1_ADDR, tmp_rx);
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#else
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(void)is_enable;
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(void)desc0_to_hw_phase;
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(void)desc1_to_hw_phase;
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(void)desc2_to_hw_phase;
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(void)desc3_to_hw_phase;
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#endif
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}
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void phy_force_0_access_require()
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{
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/* disable irq */
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os_disable_irq();
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}
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void phy_force_0_access_release()
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{
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/* enable irq */
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os_enable_irq();
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}
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void IRAM_ATTR phy_force_0_access_require_from_isr()
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{
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}
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void IRAM_ATTR phy_force_0_access_release_from_isr()
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{
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}
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/* NOTE: this function cannot call in interrupt */
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/* force phy rx phase */
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void phy_rx_phase_force_set(bool_t enable, uint8_t hw_phase)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp;
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/* record force phase en and force phase */
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g_phy_cpu_share_ctxt.rx_phase_force_en = enable;
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g_phy_cpu_share_ctxt.rx_phase_force = hw_phase;
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phy_force_0_access_require();
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tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
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REG_FIELD_SET(CFG_PHY_RX_PHASE_SEL_FORCE_EN, tmp, enable);
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REG_FIELD_SET(CFG_PHY_RX_PHASE_SEL, tmp, hw_phase);
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RGF_MAC_WRITE_REG(CFG_PHY_FORCE_0_ADDR, tmp);
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phy_force_0_access_release();
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#else
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(void)enable;
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(void)hw_phase;
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#endif
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return;
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}
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/* force phy rx phase */
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void phy_rx_phase_force_set_on_dump(bool_t enable, uint8_t hw_phase)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp;
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phy_force_0_access_require();
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tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
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REG_FIELD_SET(CFG_PHY_RX_PHASE_SEL_FORCE_EN, tmp, enable);
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REG_FIELD_SET(CFG_PHY_RX_PHASE_SEL, tmp, hw_phase);
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RGF_MAC_WRITE_REG(CFG_PHY_FORCE_0_ADDR, tmp);
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phy_force_0_access_release();
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#else
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(void)enable;
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(void)hw_phase;
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#endif
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}
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uint32_t phy_get_rx_force_phase_val()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
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return REG_FIELD_GET(CFG_PHY_RX_PHASE_SEL, tmp);
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#else
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return 0;
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#endif
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}
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uint32_t phy_get_rx_phase_force_en()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
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return REG_FIELD_GET(CFG_PHY_RX_PHASE_SEL_FORCE_EN, tmp);
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#else
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return 0;
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#endif
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}
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uint32_t phy_get_hw_phy_rx_phase_sel(void)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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return (REG_FIELD_GET(PHY_RX_PHASE_SEL, \
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RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_0_ADDR)));
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#else
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return 0;
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#endif
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}
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void phy_set_tx_force_enable(uint8_t is_enable)
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{
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uint32_t tmp;
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is_enable = !!is_enable;
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tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_1_ADDR);
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REG_FIELD_SET(CFG_PHY_TX_ENABLE, tmp, is_enable);
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REG_FIELD_SET(CFG_PHY_TX_ENABLE_FORCE_EN, tmp, is_enable);
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RGF_MAC_WRITE_REG(CFG_PHY_FORCE_1_ADDR, tmp);
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}
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