kunlun/plc/halphy/hw2/hw_phy_perf.c

/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/
#include "chip_reg_base.h"
#include "iot_config.h"
#include "iot_errno_api.h"
#include "iot_io_api.h"
#include "iot_system.h"
#include "hw_reg_api.h"
#include "hw_phy_api.h"
#include "phy_perf.h"

#include "phy_dfe_reg.h"
#include "phy_rxtd_reg.h"
#include "phy_rx_fd_reg.h"
#include "phy_tx_reg.h"
#include "phy_reg.h"
#include "phy_rxtd_reg.h"

void phy_acc_seg_pwr_en_set(uint8_t en)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_RXTD_READ_REG(CFG_BB_ACC_PWR_ADDR);
    REG_FIELD_SET(SW_SEG_PWR_EN, tmp, en);
    PHY_RXTD_WRITE_REG(CFG_BB_ACC_PWR_ADDR, tmp);
#else
    (void)en;
#endif
}

void phy_acc_normal_coeff_set(uint8_t coeff)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_RXTD_READ_REG(CFG_BB_ACC_PWR_ADDR);
    REG_FIELD_SET(SW_NORMAL_COEFF, tmp, coeff);
    PHY_RXTD_WRITE_REG(CFG_BB_ACC_PWR_ADDR, tmp);
#else
    (void)coeff;
#endif
}

void phy_acc_seg_pwr_mask_en(uint8_t en)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_RXTD_READ_REG(CFG_BB_ACC_PWR_ADDR);
    REG_FIELD_SET(SW_SEG_PWR_MASK_EN, tmp, en);
    PHY_RXTD_WRITE_REG(CFG_BB_ACC_PWR_ADDR, tmp);
#else
    (void)en;
#endif
}

void phy_acc_seg_pwr_mask_thr(uint8_t thrd)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_RXTD_READ_REG(CFG_BB_ACC_PWR_ADDR);
    REG_FIELD_SET(SW_SEG_PWR_MASK_THR, tmp, thrd);
    PHY_RXTD_WRITE_REG(CFG_BB_ACC_PWR_ADDR, tmp);
#else
    (void)thrd;
#endif
}

void phy_acc_seg_pwr_mask_sel(uint8_t sel)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    tmp = PHY_RXTD_READ_REG(CFG_BB_ACC_PWR_ADDR);
    REG_FIELD_SET(SW_SEG_PWR_MASK_SEL, tmp, sel);
    PHY_RXTD_WRITE_REG(CFG_BB_ACC_PWR_ADDR, tmp);
#else
    (void)sel;
#endif
}

void phy_impuse_cancel_mode_set(uint8_t mode)
{
    uint32_t tmp = 0;
    tmp = PHY_DFE_READ_REG(CFG_BB_IMPULSE_CANCEL_CFG_ADDR);
    REG_FIELD_SET(SW_IMPULSE_CANCEL_MODE, tmp, mode);
    PHY_DFE_WRITE_REG(CFG_BB_IMPULSE_CANCEL_CFG_ADDR, tmp);
}

void phy_impuse_cancel_clip_ratio_set(uint8_t ratio)
{
    uint32_t tmp = 0;
    tmp = PHY_DFE_READ_REG(CFG_BB_IMPULSE_CANCEL_CFG_ADDR);
    REG_FIELD_SET(SW_IMPULSE_CANCEL_CLIP_RATIO, tmp, ratio);
    PHY_DFE_WRITE_REG(CFG_BB_IMPULSE_CANCEL_CFG_ADDR, tmp);
}

void phy_impuse_cancel_blank_ratio_set(uint8_t ratio)
{
    uint32_t tmp = 0;
    tmp = PHY_DFE_READ_REG(CFG_BB_IMPULSE_CANCEL_CFG_ADDR);
    REG_FIELD_SET(SW_IMPULSE_CANCEL_BLANK_RATIO, tmp, ratio);
    PHY_DFE_WRITE_REG(CFG_BB_IMPULSE_CANCEL_CFG_ADDR, tmp);
}


void phy_hpf_bypass_set(uint8_t hpf_bypass)
{
    uint32_t tmp = 0;
    tmp = PHY_DFE_READ_REG(CFG_BB_HPF_CFG_ADDR);
    REG_FIELD_SET(SW_BB_HPF_BYPASS, tmp, hpf_bypass);
    PHY_DFE_WRITE_REG(CFG_BB_HPF_CFG_ADDR, tmp);
}

void phy_hpf_alpha_set(uint8_t hpf_alpha)
{
    uint32_t tmp = 0;
    tmp = PHY_DFE_READ_REG(CFG_BB_HPF_CFG_ADDR);
    REG_FIELD_SET(SW_BB_HPF_ALPHA, tmp, hpf_alpha);
    PHY_DFE_WRITE_REG(CFG_BB_HPF_CFG_ADDR, tmp);
}

void phy_impuse_cancel_set(\
    uint8_t mode, uint8_t clip_ratio, uint8_t blank_ratio)
{
    phy_impuse_cancel_mode_set(mode);
    phy_impuse_cancel_clip_ratio_set(clip_ratio);
    phy_impuse_cancel_blank_ratio_set(blank_ratio);
}

void phy_hpf_set(uint8_t hpf_bypass, uint8_t hpf_alpha)
{
    phy_hpf_bypass_set(hpf_bypass);
    phy_hpf_alpha_set(hpf_alpha);
}

void phy_chn_spike_check(void)
{
    if (phy_spike_shift_en_get()) {
        if (1 == g_phy_cpu_share_ctxt.pt_mode_entry) {
            /* set defalt value in production test mode */
            phy_spike_check_set(0xFF, 0, 3);
            phy_impuse_cancel_set(0, 6, 14);
            phy_hpf_set(1, 230);
            iot_printf("spike check disable \n");
        } else {
            /* detect spike, set spike enable */
            phy_spike_check_set(0x3, 1, 3);
            phy_impuse_cancel_set(2, 6, 14);
            phy_hpf_set(0, 230);
            iot_printf("spike check enable \n");
        }
    } else {
        /* No detection spike, reset defalt value */
        phy_spike_check_set(0xFF, 0, 3);
        phy_impuse_cancel_set(0, 6, 14);
        phy_hpf_set(1, 230);
        iot_printf("spike check disable \n");
    }
}

void phy_spike_check_set(uint8_t seg_pwr_en, \
    uint8_t seg_pwr_mask_en, uint8_t coeff)
{
    phy_acc_seg_pwr_en_set(seg_pwr_en);
    phy_acc_normal_coeff_set(coeff);
    phy_acc_seg_pwr_mask_en(seg_pwr_mask_en);
    phy_acc_seg_pwr_mask_thr(2);
    phy_acc_seg_pwr_mask_sel(1);

    phy_agc_sat_adj_set(1, 0);

    phy_agc_sat_jug_cnt_set(64);
    phy_agc_seg_num_set(4);
    phy_agc_sat_seg_en(1);
}

void phy_spike_check_reg_print()
{
    uint32_t tmp = 0;

    tmp = PHY_RXTD_READ_REG(CFG_BB_ACC_PWR_ADDR);
    iot_printf("CFG_BB_ACC_PWR_ADDR:%x\n", tmp);

    tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_GAIN_LEVEL_ADDR);
    iot_printf("CFG_BB_AGC_GAIN_LEVEL_ADDR:%x\n", tmp);

    tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_SAT_JUDGE_ADDR);
    iot_printf("CFG_BB_AGC_SAT_JUDGE_ADDR:%x\n", tmp);
}

void phy_high_perf_set(bool_t en)
{
#if IOT_DTEST_ONLY_SUPPORT == 0
    uint32_t tmp = 0;

    /* not fix gain*/
    phy_agc_gain_lvl_set(0,60,-24,0);
    /* enable power satuation and hw adjust gain req*/
    phy_agc_sat_adj_set(1, 0);
    /* use 1536 point agc */
    tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
    REG_FIELD_SET(SW_AGC_ACC_STEP_LS,tmp,4);
    REG_FIELD_SET(SW_AGC_ACC_STEP_HS,tmp,3);
    PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR,tmp);

#endif
    (void)en;
}

/* todo: spur check different between kl and kl2 */