100 lines
2.7 KiB
INI
100 lines
2.7 KiB
INI
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#source [file join [file dirname [string map {"\\" "/"} [info script]]] openocd_jtag.cfg]
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source [find /opt/riscv/share/openocd/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg]
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adapter_khz 1000
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set _CHIPNAME riscv
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jtag newtap $_CHIPNAME cpu -irlen 5
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gdb_port 3333
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proc disable_watchdog {} {
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echo "Disabling watchdog..."
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halt
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mww 0x40040080 0x57444750
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mww 0x40040008 0
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mww 0x40040080 0
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mww 0x40041080 0x57444750
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mww 0x40041008 0
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mww 0x40041080 0
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mww 0x40042080 0x57444750
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mww 0x40042008 0
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mww 0x40042080 0
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# mww 0x012c0080 0x57444750
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# mww 0x012c0008 0
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# mww 0x012c0080 0
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# mww 0x108C0080 0x57444750
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# mww 0x108C0008 0
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# mww 0x108C0080 0
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# mww 0x10B00080 0x57444750
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# mww 0x10B00008 0
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# mww 0x10B00080 0
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# mww 0x208C0080 0x57444750
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# mww 0x208C0008 0
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# mww 0x208C0080 0
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# mww 0x0194F080 0x57444750
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# mww 0x0194F008 0
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# mww 0x0194F080 0
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}
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# mrw: "memory read word", returns value of $reg
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proc mrw {reg} {
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set value ""
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mem2array value 32 $reg 1
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return $value(0)
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}
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# core 0
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set _TARGETNAME0 $_CHIPNAME.cpu0
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target create $_TARGETNAME0 riscv -chain-position $_CHIPNAME.cpu -coreid 0
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$_TARGETNAME0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
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$_TARGETNAME0 configure -event reset-init disable_watchdog
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$_TARGETNAME0 configure -event examine-end {
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echo "start core 1 & core 2"
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halt
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# core 1 & 2 clk
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# mww 0x10800010 0x00000900
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mww 0x50019400 0x00000006
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# core 1 start pc
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mww 0x10030000 0x0000006F
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mww 0x50019024 0x10030000
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# core 2 start pc
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mww 0x10060000 0x0000006F
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mww 0x50019028 0x10060000
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# core 1 enable
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mww 0x50019004 [expr [mrw 0x50019004] & 0x2]
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# core 2 enable
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mww 0x50019004 [expr [mrw 0x50019004] & 0x4]
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# # core 1 & 2 clk
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# mww 0x10800010 0x00000900
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#
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# # core 1 start pc
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# mww 0x1023EFF0 0x0000006F
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# mww 0x10800040 0x1023EFF0
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# # core 2 start pc
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# mww 0x1023EFF4 0x0000006F
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# mww 0x10800044 0x1023EFF4
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# # core 1 enable
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# mww 0x01200160 [expr [mrw 0x01200160] | 0x20]
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# # core 2 enable
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# mww 0x01200160 [expr [mrw 0x01200160] | 0x40]
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sleep 100
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}
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# core 1
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set _TARGETNAME1 $_CHIPNAME.cpu1
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target create $_TARGETNAME1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
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$_TARGETNAME1 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
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$_TARGETNAME1 configure -event examine-end halt
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# core 2
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set _TARGETNAME2 $_CHIPNAME.cpu2
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target create $_TARGETNAME2 riscv -chain-position $_CHIPNAME.cpu -coreid 2
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$_TARGETNAME2 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
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$_TARGETNAME2 configure -event examine-end halt
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