308 lines
11 KiB
C
308 lines
11 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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/* os shim includes */
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#include "os_types.h"
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#include "hw_reg_api.h"
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#include "pmu_rf.h"
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void pmu_enable(uint32_t module)
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{
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volatile uint32_t delay = 100;
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uint32_t i = 0;
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uint32_t tmp;
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//enable module;
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tmp = PMU_RF_READ_REG(CFG_PMU_CLK_ENABLE_ADDR);
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if(tmp & (1<< module))
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return;
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tmp |= (1<< module);
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PMU_RF_WRITE_REG(CFG_PMU_CLK_ENABLE_ADDR, tmp);
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//soft reset module;
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tmp = PMU_RF_READ_REG(CFG_PMU_SOFT_RESET_ADDR);
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tmp |= (1<< module);
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PMU_RF_WRITE_REG(CFG_PMU_SOFT_RESET_ADDR, tmp);
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//delay
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for(i = 0; i < delay; i++);
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//reset done
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tmp = PMU_RF_READ_REG(CFG_PMU_SOFT_RESET_ADDR);
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tmp &= ~(1<< module);
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PMU_RF_WRITE_REG(CFG_PMU_SOFT_RESET_ADDR, tmp);
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}
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void pmu_disable(uint32_t module)
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{
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volatile uint32_t delay = 100;
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uint32_t i = 0;
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uint32_t tmp;
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if(module < 32){
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//enable module;
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tmp = PMU_RF_READ_REG(CFG_PMU_CLK_ENABLE_ADDR);
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tmp &= ~(1<< module);
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PMU_RF_WRITE_REG(CFG_PMU_CLK_ENABLE_ADDR, tmp);
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//soft reset module;
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tmp = PMU_RF_READ_REG(CFG_PMU_SOFT_RESET_ADDR);
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tmp |= (1<< module);
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PMU_RF_WRITE_REG(CFG_PMU_SOFT_RESET_ADDR, tmp);
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//delay
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for(i = 0; i < delay; i++);
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//reset done
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tmp = PMU_RF_READ_REG(CFG_PMU_SOFT_RESET_ADDR);
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tmp &= ~(1<< module);
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PMU_RF_WRITE_REG(CFG_PMU_SOFT_RESET_ADDR, tmp);
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}
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}
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void pmu_clk_set(uint32_t clk_sel)
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{
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(void)clk_sel;
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/* The PMU clock configuration is completed during hardware initialization
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* and will not be modified later. Refer to clk_pmu_clk_set().
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*/
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}
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void pmu_bpll_calibration_binary_search()
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{
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uint32_t tmp;
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// calibration bpll
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tmp = PMU_RF_READ_REG(CFG_CALIB_VCO_CFG0_ADDR);
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REG_FIELD_SET(PLL_VCO_CALIB_READY_MANU, tmp, 0);
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REG_FIELD_SET(PLL_VCO_CALIB_RESTART, tmp, 0);
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REG_FIELD_SET(VCO_CALIB_PRECISION_CYCLE_NUM, tmp, 4000);
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PMU_RF_WRITE_REG(CFG_CALIB_VCO_CFG0_ADDR, tmp);
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tmp = PMU_RF_READ_REG(CFG_CALIB_VCO_CFG0_ADDR);
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REG_FIELD_SET(PLL_VCO_CALIB_MANU_EN, tmp, 1);
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PMU_RF_WRITE_REG(CFG_CALIB_VCO_CFG0_ADDR, tmp);
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tmp = PMU_RF_READ_REG(CFG_PMU_SOFT_RESET_ADDR);
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REG_FIELD_SET(VCO_CALIB_SOFT_RST, tmp, 1);
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PMU_RF_WRITE_REG(CFG_PMU_SOFT_RESET_ADDR, tmp);
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tmp = PMU_RF_READ_REG(CFG_PMU_SOFT_RESET_ADDR);
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REG_FIELD_SET(VCO_CALIB_SOFT_RST, tmp, 0);
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PMU_RF_WRITE_REG(CFG_PMU_SOFT_RESET_ADDR, tmp);
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tmp = PMU_RF_READ_REG(CFG_CALIB_VCO_CFG1_ADDR);
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REG_FIELD_SET(VCO_CALIB_CODE_SWH_WAIT_CN, tmp, 200);
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PMU_RF_WRITE_REG(CFG_CALIB_VCO_CFG1_ADDR, tmp);
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tmp = PMU_RF_READ_REG(CFG_CALIB_VCO_CFG0_ADDR);
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REG_FIELD_SET(PLL_VCO_CALIB_MANU_EN, tmp, 0);
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PMU_RF_WRITE_REG(CFG_CALIB_VCO_CFG0_ADDR, tmp);
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tmp = PMU_RF_READ_REG(CFG_CALIB_VCO_CFG0_ADDR);
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REG_FIELD_SET(PLL_VCO_CALIB_RESTART, tmp, 1);
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PMU_RF_WRITE_REG(CFG_CALIB_VCO_CFG0_ADDR, tmp);
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while(1) {
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tmp = PMU_RF_READ_REG(CFG_CALIB_VCO_CFG1_ADDR);
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if(REG_FIELD_GET(PLL_VCO_CALIB_READY, tmp)) {
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break;
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}
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}
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}
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void pmu_bpll_calibration()
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{
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uint32_t tmp;
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uint8_t code_result=0;
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uint32_t comp_result=0;
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uint32_t diff_result=0xffff;
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uint32_t precison_value=2500;
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uint32_t fb_cnt=0;
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tmp=PMU_RF_READ_REG(CFG_CALIB_VCO_CFG0_ADDR);
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REG_FIELD_SET(VCO_CALIB_PRECISION_CYCLE_NUM,tmp,precison_value);
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REG_FIELD_SET(PLL_VCO_CALIB_READY_MANU,tmp,0);
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REG_FIELD_SET(PLL_VCO_CALIB_MANU_EN,tmp,1);
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PMU_RF_WRITE_REG(CFG_CALIB_VCO_CFG0_ADDR,tmp);
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tmp=PMU_RF_READ_REG(CFG_CALIB_VCO_CFG1_ADDR);
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REG_FIELD_SET(VCO_CALIB_CODE_SWH_WAIT_CN,tmp,100);
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PMU_RF_WRITE_REG(CFG_CALIB_VCO_CFG1_ADDR,tmp);
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for(uint8_t i=0;i<64;i++) {
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tmp=PMU_RF_READ_REG(CFG_CALIB_VCO_CFG0_ADDR);
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REG_FIELD_SET(PLL_VCO_CALIB_MANU_CAL,tmp,i);
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PMU_RF_WRITE_REG(CFG_CALIB_VCO_CFG0_ADDR,tmp);
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tmp=PMU_RF_READ_REG(CFG_CALIB_VCO_CFG1_ADDR);
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REG_FIELD_SET(VCO_PLL_FB_CNT_CLR,tmp,1);
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REG_FIELD_SET(VCO_CALIB_DONE_CLR,tmp,1);
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PMU_RF_WRITE_REG(CFG_CALIB_VCO_CFG1_ADDR,tmp);
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REG_FIELD_SET(VCO_PLL_FB_CNT_CLR,tmp,0);
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REG_FIELD_SET(VCO_CALIB_DONE_CLR,tmp,0);
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PMU_RF_WRITE_REG(CFG_CALIB_VCO_CFG1_ADDR,tmp);
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tmp=PMU_RF_READ_REG(CFG_CALIB_VCO_CFG0_ADDR);
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REG_FIELD_SET(PLL_VCO_CALIB_RESTART,tmp,0);
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PMU_RF_WRITE_REG(CFG_CALIB_VCO_CFG0_ADDR,tmp);
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REG_FIELD_SET(PLL_VCO_CALIB_RESTART,tmp,1);
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PMU_RF_WRITE_REG(CFG_CALIB_VCO_CFG0_ADDR,tmp);
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while (1) {
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tmp=PMU_RF_READ_REG(CFG_CALIB_VCO_CFG1_ADDR);
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if (REG_FIELD_GET(VCO_CALIB_DONE,tmp)) {
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tmp=PMU_RF_READ_REG(CFG_CALIB_VCO_CFG2_ADDR);
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fb_cnt = (tmp>>4) & 0xffff;
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comp_result = (fb_cnt > precison_value) ? \
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(fb_cnt-precison_value) : (precison_value-fb_cnt);
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if (comp_result <= diff_result) {
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code_result=i;
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diff_result=comp_result;
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}
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break;
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}
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}
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}
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tmp=PMU_RF_READ_REG(CFG_CALIB_VCO_CFG0_ADDR);
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REG_FIELD_SET(PLL_VCO_CALIB_READY_MANU,tmp,0);
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REG_FIELD_SET(PLL_VCO_CALIB_MANU_EN,tmp,1);
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REG_FIELD_SET(PLL_VCO_CALIB_MANU_CAL,tmp,code_result);
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PMU_RF_WRITE_REG(CFG_CALIB_VCO_CFG0_ADDR,tmp);
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tmp=PMU_RF_READ_REG(CFG_CALIB_VCO_CFG0_ADDR);
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REG_FIELD_SET(PLL_VCO_CALIB_READY_MANU,tmp,1);
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PMU_RF_WRITE_REG(CFG_CALIB_VCO_CFG0_ADDR,tmp);
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}
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void pmu_mpll_calibration_binary_search()
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{
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uint32_t tmp;
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tmp=PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR);
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REG_FIELD_SET(MIPIPLL_VCO_CALIB_READY_MANU,tmp,0);
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REG_FIELD_SET(MIPIPLL_VCO_CALIB_RESTART,tmp,0);
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REG_FIELD_SET(MIPIVCO_CALIB_PRECISION_CYCLE_NUM, tmp, 4000);
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PMU_RF_WRITE_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR,tmp);
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tmp=PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR);
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REG_FIELD_SET(MIPIPLL_VCO_CALIB_MANU_EN,tmp,1);
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PMU_RF_WRITE_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR,tmp);
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tmp=PMU_RF_READ_REG(CFG_PMU_SOFT_RESET_ADDR);
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REG_FIELD_SET(MIPIVCO_CALIB_SOFT_RST,tmp,1);
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PMU_RF_WRITE_REG(CFG_PMU_SOFT_RESET_ADDR,tmp);
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tmp=PMU_RF_READ_REG(CFG_PMU_SOFT_RESET_ADDR);
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REG_FIELD_SET(MIPIVCO_CALIB_SOFT_RST,tmp,0);
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PMU_RF_WRITE_REG(CFG_PMU_SOFT_RESET_ADDR,tmp);
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tmp=PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG1_ADDR);
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REG_FIELD_SET(MIPIVCO_CALIB_CODE_SWH_WAIT_CN, tmp, 200);
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PMU_RF_WRITE_REG(CFG_CALIB_MIPIVCO_CFG1_ADDR,tmp);
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tmp=PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR);
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REG_FIELD_SET(MIPIPLL_VCO_CALIB_MANU_EN,tmp,0);
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PMU_RF_WRITE_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR,tmp);
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tmp=PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR);
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REG_FIELD_SET(MIPIPLL_VCO_CALIB_RESTART,tmp,1);
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PMU_RF_WRITE_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR,tmp);
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while(1) {
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tmp = PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG1_ADDR);
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if(REG_FIELD_GET(MIPIPLL_VCO_CALIB_READY, tmp)) {
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break;
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}
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}
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}
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void pmu_mpll_calibration()
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{
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uint32_t tmp;
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uint8_t code_result=0;
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uint32_t comp_result=0;
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uint32_t diff_result=0xffff;
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uint32_t precison_value=2500;
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uint32_t fb_cnt=0;
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tmp=PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR);
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REG_FIELD_SET(MIPIVCO_CALIB_PRECISION_CYCLE_NUM,tmp,precison_value);
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REG_FIELD_SET(MIPIPLL_VCO_CALIB_READY_MANU,tmp,0);
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REG_FIELD_SET(MIPIPLL_VCO_CALIB_MANU_EN,tmp,1);
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PMU_RF_WRITE_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR,tmp);
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tmp=PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG1_ADDR);
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REG_FIELD_SET(MIPIVCO_CALIB_CODE_SWH_WAIT_CN,tmp,100);
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PMU_RF_WRITE_REG(CFG_CALIB_MIPIVCO_CFG1_ADDR,tmp);
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for(uint8_t i=0;i<64;i++) {
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tmp=PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR);
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REG_FIELD_SET(MIPIPLL_VCO_CALIB_MANU_CAL,tmp,i);
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PMU_RF_WRITE_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR,tmp);
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tmp=PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG1_ADDR);
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REG_FIELD_SET(MIPIVCO_PLL_FB_CNT_CLR,tmp,1);
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REG_FIELD_SET(MIPIVCO_CALIB_DONE_CLR,tmp,1);
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PMU_RF_WRITE_REG(CFG_CALIB_MIPIVCO_CFG1_ADDR,tmp);
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REG_FIELD_SET(MIPIVCO_PLL_FB_CNT_CLR,tmp,0);
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REG_FIELD_SET(MIPIVCO_CALIB_DONE_CLR,tmp,0);
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PMU_RF_WRITE_REG(CFG_CALIB_MIPIVCO_CFG1_ADDR,tmp);
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tmp=PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR);
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REG_FIELD_SET(MIPIPLL_VCO_CALIB_RESTART,tmp,0);
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PMU_RF_WRITE_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR,tmp);
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REG_FIELD_SET(MIPIPLL_VCO_CALIB_RESTART,tmp,1);
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PMU_RF_WRITE_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR,tmp);
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while (1) {
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tmp=PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG1_ADDR);
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if (REG_FIELD_GET(MIPIVCO_CALIB_DONE,tmp)) {
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tmp=PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG2_ADDR);
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fb_cnt = (tmp>>4) & 0xffff;
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comp_result = (fb_cnt > precison_value) ? \
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(fb_cnt-precison_value) : (precison_value-fb_cnt);
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if (comp_result <= diff_result) {
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code_result=i;
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diff_result=comp_result;
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}
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break;
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}
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}
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}
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tmp=PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR);
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REG_FIELD_SET(MIPIPLL_VCO_CALIB_READY_MANU,tmp,0);
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REG_FIELD_SET(MIPIPLL_VCO_CALIB_MANU_EN,tmp,1);
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REG_FIELD_SET(MIPIPLL_VCO_CALIB_MANU_CAL,tmp,code_result);
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PMU_RF_WRITE_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR,tmp);
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tmp=PMU_RF_READ_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR);
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REG_FIELD_SET(MIPIPLL_VCO_CALIB_READY_MANU,tmp,1);
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PMU_RF_WRITE_REG(CFG_CALIB_MIPIVCO_CFG0_ADDR,tmp);
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}
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void pmu_soft_reset(uint32_t module)
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{
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volatile uint32_t delay = 100;
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uint32_t tmp;
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//soft reset module;
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tmp = PMU_RF_READ_REG(CFG_PMU_SOFT_RESET_ADDR);
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tmp |= (1<< module);
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PMU_RF_WRITE_REG(CFG_PMU_SOFT_RESET_ADDR, tmp);
|
||
|
|
|
||
|
|
//delay
|
||
|
|
for(uint32_t i = 0; i < delay; i++);
|
||
|
|
|
||
|
|
//reset done
|
||
|
|
tmp = PMU_RF_READ_REG(CFG_PMU_SOFT_RESET_ADDR);
|
||
|
|
tmp &= ~(1<< module);
|
||
|
|
PMU_RF_WRITE_REG(CFG_PMU_SOFT_RESET_ADDR, tmp);
|
||
|
|
}
|