141 lines
6.0 KiB
C
141 lines
6.0 KiB
C
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#ifndef __MEM_MAP_ORG_H__
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#define __MEM_MAP_ORG_H__
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#include "chip_reg_base.h"
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//CHIP BASE
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#define MEM_CFG_CHIP_ROM_BASE AHB_ROM_BASEADDR //internal rom
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#define MEM_CFG_CHIP_ROM_SIZE (AHB_ROM_ENDADDR - AHB_ROM_BASEADDR) //256k
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#define MEM_CFG_CHIP_RAM_BASE AHB_RAM0_BASEADDR //internal ram
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#define MEM_CFG_CHIP_RAM_SIZE (AHB_RAM3_ENDADDR - AHB_RAM0_BASEADDR) //448k
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#define MEM_CFG_CHIP_ICACHE0_SMC_BASE ICACHE0_SMC_RAM_BASEADDR // icache0 smc base
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#define MEM_CFG_CHIP_ICACHE0_SFC_BASE ICACHE0_SFC_RAM_BASEADDR // icache0 sfc base
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#define MEM_CFG_CHIP_ICACHE1_SMC_BASE ICACHE1_SMC_RAM_BASEADDR // icache1 smc base
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#define MEM_CFG_CHIP_ICACHE1_SFC_BASE ICACHE1_SFC_RAM_BASEADDR // icache1 sfc base
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#define MEM_CFG_CHIP_ICACHE2_SMC_BASE ICACHE2_SMC_RAM_BASEADDR // icache2 smc base
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#define MEM_CFG_CHIP_ICACHE2_SFC_BASE ICACHE2_SFC_RAM_BASEADDR // icache2 sfc base
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#define MEM_CFG_CHIP_DCACHE0_SMC_BASE DCACHE0_SMC_RAM_BASEADDR // dcache0 smc base
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#define MEM_CFG_CHIP_DCACHE0_SFC_BASE DCACHE0_SFC_RAM_BASEADDR // dcache0 sfc base
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#define MEM_CFG_CHIP_DCACHE1_SMC_BASE DCACHE1_SMC_RAM_BASEADDR // dcache1 smc base
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#define MEM_CFG_CHIP_DCACHE1_SFC_BASE DCACHE1_SFC_RAM_BASEADDR // dcache1 sfc base
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#define MEM_CFG_CHIP_ICACHE0_RAM_BASE ICACHE0_SMC_RAM_BASEADDR // as ram base addr
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#define MEM_CFG_CHIP_ICACHE0_RAM_SIZE (0x8000) //32k
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#define MEM_CFG_CHIP_ICACHE1_RAM_BASE ICACHE1_SMC_RAM_BASEADDR // as ram base addr
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#define MEM_CFG_CHIP_ICACHE1_RAM_SIZE (0x8000) //32k
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#define MEM_CFG_CHIP_ICACHE2_RAM_BASE ICACHE2_SMC_RAM_BASEADDR // as ram base addr
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#define MEM_CFG_CHIP_ICACHE2_RAM_SIZE (0x8000) //32k
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#define MEM_CFG_CHIP_DCACHE0_RAM_BASE DCACHE0_SMC_RAM_BASEADDR // as ram base addr
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#define MEM_CFG_CHIP_DCACHE0_RAM_SIZE (0x10000) //64k
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#define MEM_CFG_CHIP_DCACHE1_RAM_BASE DCACHE1_SMC_RAM_BASEADDR // as ram base addr
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#define MEM_CFG_CHIP_DCACHE1_RAM_SIZE (0x10000) //64k
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/*address mapping. */
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#define FLASH_BASE_ADDRESS (ICACHE0_SFC_RAM_BASEADDR)
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#define PSRAM_CORE0_BASE_ADDRESS (ICACHE0_SMC_RAM_BASEADDR)
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#define PSRAM_CORE1_BASE_ADDRESS (ICACHE1_SMC_RAM_BASEADDR)
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//SBL
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#define MEM_CFG_SBL_IRAM_ADDRS (MEM_CFG_CHIP_RAM_BASE + 0x00000800)
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#define MEM_CFG_SBL_IRAM_SIZE (0x10000) //64k
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#define MEM_CFG_SBL_DRAM_ADDRS (MEM_CFG_CHIP_RAM_BASE + 0x0010800)
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#define MEM_CFG_SBL_DRAM_SIZE (0x10000) //64k
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/*
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* FLASH space for SBL code.
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*/
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#define MEM_CFG_FLASH_SBL1_CODE_OFFSET (0x00000000)
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#define MEM_CFG_FLASH_SBL2_CODE_OFFSET (0x00000000 + 0x8000)
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/*
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* PSRAM space for run offset.
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*/
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#define MEM_CFG_RAM_CORE0_RUN_OFFSET (0x00000000)
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#define MEM_CFG_RAM_CORE1_RUN_OFFSET (0x005C0000)
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/*
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* RAM space for bbcpu run offset.
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*/
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#define MEM_CFG_RAM_BBCPU_RUN_ADDR (0x10000800)
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/*
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* ROM space from 0x0002_0000 ~ 0x0005_FFFF, 256KB
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* Rom CODE : 0x00000000 ~ 0x00007FFF, 32KB.
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* Rom LIB : 0x00008000 ~ 0x0005FFFF, 224KB.
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*/
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/* Rom code in ROM space. */
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#define MEM_CFG_ROM_ROM_CODE_OFFSET (0x00000000)
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#define MEM_CFG_ROM_ROM_CODE_LENGTH (0x4000)
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/* Rom lib code in ROM space. */
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#define MEM_CFG_ROM_ROM_LIB_OFFSET (0x00004000)
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#define MEM_CFG_ROM_ROM_LIB_LENGTH (0x3C000)
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/*
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* RAM space from 0x1000_0000 ~ 0x1006_FFFF, 448KB
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* Rom DATA : 0x0006BC00 ~ 0x0006FFFF, 17KB
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* ...
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* SBL/RAM/DTEST DATA : 0x00010800 ~ 0x000207FF, 64KB
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* SBL/RAM/DTEST CODE : 0x00000800 ~ 0x000107FF, 64KB
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*/
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/* Rom data in RAM space. */
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#define MEM_CFG_RAM_ROM_DATA_OFFSET (0x0006BC00)
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#define MEM_CFG_RAM_ROM_DATA_LENGTH (0x4400)
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/* SBL code in RAM space. */
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#define MEM_CFG_RAM_SBL_DATA_OFFSET 0x00010800
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#define MEM_CFG_RAM_SBL_DATA_LENGTH 0x10000
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/* SBL data in RAM space. */
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#define MEM_CFG_RAM_SBL_CODE_OFFSET 0x00000800
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#define MEM_CFG_RAM_SBL_CODE_LENGTH 0x10000
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/* RAM code in RAM space. */
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#define MEM_CFG_RAM_RAM_DATA_OFFSET (0x00010800)
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#define MEM_CFG_RAM_RAM_DATA_LENGTH (0x10000)
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/* RAM data in RAM space. */
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#define MEM_CFG_RAM_RAM_CODE_OFFSET (0x00000800)
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#define MEM_CFG_RAM_RAM_CODE_LENGTH (0x10000)
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//AUTHORITY RELATED
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#define MEM_CFG_AUTH_READ (0x4)
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#define MEM_CFG_AUTH_WRITE (0x2)
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#define MEM_CFG_AUTH_NONE (0x0)
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#define MEM_CFG_AUTH_RW (MEM_CFG_AUTH_READ | MEM_CFG_AUTH_WRITE)
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#define MEM_CFG_SET_CORE_AUTHORITY(authority, core) \
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(((authority) & 0xFF) << (core * 8))
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#define MEM_CFG_GET_CORE_AUTHORITY(authority, core) \
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(((authority) >> (core * 8)) & 0xFF)
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#define MEM_CFG_R_ONLY(core) MEM_CFG_SET_CORE_AUTHORITY(MEM_CFG_AUTH_READ, core)
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#define MEM_CFG_W_ONLY(core) MEM_CFG_SET_CORE_AUTHORITY(MEM_CFG_AUTH_WRITE, core)
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#define MEM_CFG_RW(core) MEM_CFG_SET_CORE_AUTHORITY(MEM_CFG_AUTH_RW, core)
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#define MEM_CFG_NONE(core) MEM_CFG_SET_CORE_AUTHORITY(MEM_CFG_AUTH_NONE, core)
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/* fixed 带psram和不带psram相同的分<E79A84><E58886>?*/
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#define MEM_CFG_PART_NUM_MIN 0
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#define MEM_CFG_PART_NUM_SBL 0
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#define MEM_CFG_PART_NUM_DD1 1
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#define MEM_CFG_PART_NUM_DD2 2
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#define MEM_CFG_PART_NUM_PARAM 3
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#define MEM_CFG_PART_NUM_OEM 4
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#define MEM_CFG_PART_NUM_PIB1 5
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#define MEM_CFG_PART_NUM_PIB2 6
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/* volatile 带psram和不带psram不相同的分区 */
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#define MEM_CFG_PART_NUM_RUN_CUS 7
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#define MEM_CFG_PART_NUM_RUN_PLC 8
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#define MEM_CFG_PART_NUM_FW1_CUS 9
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#define MEM_CFG_PART_NUM_FW1_PLC 10
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#define MEM_CFG_PART_NUM_FW2_CUS 11
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#define MEM_CFG_PART_NUM_FW2_PLC 12
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#define MEM_CFG_PART_NUM_LOG1 13
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#define MEM_CFG_PART_NUM_LOG2 14
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/* fixed 带psram和不带psram相同的分<E79A84><E58886>?*/
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#define MEM_CFG_PART_NUM_CUS 15
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#define MEM_CFG_PART_NUM_PLC 16
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#define MEM_CFG_PART_NUM_CALI_CUS 17
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#define MEM_CFG_PART_NUM_CALI_PLC 18
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#define MEM_CFG_PART_NUM_MAX 18 // keep this as the last one
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/* 代码中用到的硬地址 */
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#define MEM_CFG_DECOMPRESS_RAM 0x10058000
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#define MEM_CFG_DECOMPRESS_RAM_SIZE (96 * 1024)
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#endif
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