82 lines
2.4 KiB
C
82 lines
2.4 KiB
C
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//-----------------------------------
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#define CFG_ADA_RVER_ADDR 0x0000
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#define ADA_RF_VER_OFFSET 0
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#define ADA_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_ADC_CFG0_ADDR 0x0004
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#define ADA_DUMP_32B_MODE_OFFSET 16
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#define ADA_DUMP_32B_MODE_MASK 0x00010000
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#define ADC_OEA_OFFSET 15
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#define ADC_OEA_MASK 0x00008000
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#define ADC_DMSB_INV_OFFSET 5
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#define ADC_DMSB_INV_MASK 0x00000020
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#define ADC_MEM_CLK_SW_OFFSET 4
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#define ADC_MEM_CLK_SW_MASK 0x00000010
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#define ADA_POWER_ON_OFFSET 3
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#define ADA_POWER_ON_MASK 0x00000008
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#define ADC_SAMPLE_DONE_OFFSET 2
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#define ADC_SAMPLE_DONE_MASK 0x00000004
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#define ADC_TRIG_OFFSET 1
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#define ADC_TRIG_MASK 0x00000002
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#define ADC_EN_OFFSET 0
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#define ADC_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_ADC_CFG1_ADDR 0x0008
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#define ADC_BUF_SIZE_OFFSET 0
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#define ADC_BUF_SIZE_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DAC_CFG0_ADDR 0x000c
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#define DAC_MEM_CLK_SW_OFFSET 31
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#define DAC_MEM_CLK_SW_MASK 0x80000000
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#define DAC_BUF_SIZE_OFFSET 16
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#define DAC_BUF_SIZE_MASK 0x7FFF0000
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#define DAC_EN_OFFSET 0
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#define DAC_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_DAC_CFG1_ADDR 0x0010
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#define DAC_MUX_OFFSET 17
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#define DAC_MUX_MASK 0x00020000
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#define TONE_MODE_OFFSET 16
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#define TONE_MODE_MASK 0x00010000
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#define TONE_NUMBER_OFFSET 0
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#define TONE_NUMBER_MASK 0x000007FF
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//-----------------------------------
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#define CFG_ADC_CFG2_ADDR 0x0014
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#define DAC_CLK_INV_OFFSET 25
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#define DAC_CLK_INV_MASK 0x02000000
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#define ADC_CLK_INV_OFFSET 24
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#define ADC_CLK_INV_MASK 0x01000000
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#define ADC_FORCE_MODE_OFFSET 17
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#define ADC_FORCE_MODE_MASK 0x00020000
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#define ADC_AUTO_MODE_OFFSET 16
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#define ADC_AUTO_MODE_MASK 0x00010000
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#define ADC_THR_VAL_OFFSET 0
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#define ADC_THR_VAL_MASK 0x00003FFF
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//-----------------------------------
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#define CFG_ADC_CFG3_ADDR 0x0018
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#define ADC_SAMPLE_SIZE_OFFSET 0
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#define ADC_SAMPLE_SIZE_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_ADC_STS0_ADDR 0x001c
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#define ADC_TRIG_ADDR_OFFSET 0
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#define ADC_TRIG_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_ADC_DUMP_CTRL_ADDR 0x0020
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#define SW_ADC_DUMP_SPEED_OFFSET 2
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#define SW_ADC_DUMP_SPEED_MASK 0x0000000C
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#define SW_ADC_BYTES_SELECT_OFFSET 0
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#define SW_ADC_BYTES_SELECT_MASK 0x00000003
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//HW module read/write macro
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#define ADA_READ_REG(addr) SOC_READ_REG(ADA_BASEADDR + addr)
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#define ADA_WRITE_REG(addr,value) SOC_WRITE_REG(ADA_BASEADDR + addr,value)
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