kunlun/inc/hw/reg/cm3/11/phy_dfe_reg.h

//-----------------------------------
#define CFG_BB_SW_ADJUST_GAIN_ADDR 0x0100
#define SW_TX_GAIN_LEFT_SHIFT_OFFSET 12
#define SW_TX_GAIN_LEFT_SHIFT_MASK 0x00001000
#define SW_TX_GAIN_SHIFT_BITS_OFFSET 8
#define SW_TX_GAIN_SHIFT_BITS_MASK 0x00000F00
#define SW_RX_GAIN_LEFT_SHIFT_OFFSET 4
#define SW_RX_GAIN_LEFT_SHIFT_MASK 0x00000010
#define SW_RX_GAIN_SHIFT_BITS_OFFSET 0
#define SW_RX_GAIN_SHIFT_BITS_MASK 0x0000000F

//-----------------------------------
#define CFG_GAIN_SERIAL_CFG0_ADDR 0x0104
#define SW_GAIN_CFG0_DATA_OFFSET 0
#define SW_GAIN_CFG0_DATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GAIN_SERIAL_CFG0_START_ADDR 0x0108
#define SW_GAIN_CFG0_START_OFFSET 0
#define SW_GAIN_CFG0_START_MASK 0x00000001

//-----------------------------------
#define CFG_GAIN_SERIAL_CFG1_ADDR 0x010c
#define SW_GAIN_CFG1_DATA_OFFSET 0
#define SW_GAIN_CFG1_DATA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GAIN_SERIAL_CFG1_START_ADDR 0x0110
#define SW_GAIN_CFG1_START_OFFSET 0
#define SW_GAIN_CFG1_START_MASK 0x00000001

//-----------------------------------
#define CFG_BB_TX_PA_ON_DLY_ADDR 0x0114
#define SW_PA_ON_DLY_OFFSET 0
#define SW_PA_ON_DLY_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_STDY_RX_DLY_ADDR 0x0118
#define SW_STDY_RX_DLY_OFFSET 0
#define SW_STDY_RX_DLY_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_STDY_TX_DLY_ADDR 0x011c
#define SW_STDY_TX_DLY_OFFSET 0
#define SW_STDY_TX_DLY_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_GAIN_ADJ_TIME_ADDR 0x0120
#define SW_GAIN_ADJ_TIME_OFFSET 0
#define SW_GAIN_ADJ_TIME_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_INI_CFG_ANA_ADDR 0x0124
#define SW_RX_INI_CFG_LOOP_OFFSET 2
#define SW_RX_INI_CFG_LOOP_MASK 0x0000000C
#define SW_TX_INI_CFG_LOOP_OFFSET 0
#define SW_TX_INI_CFG_LOOP_MASK 0x00000003

//-----------------------------------
#define CFG_BB_AGC_SWCFG_EN_ADDR 0x0128
#define AGC_BYPASS_MODE_OFFSET 31
#define AGC_BYPASS_MODE_MASK 0x80000000
#define SW_AR1540_EN_OFFSET 1
#define SW_AR1540_EN_MASK 0x00000002
#define SW_GAIN_CFG_EN_OFFSET 0
#define SW_GAIN_CFG_EN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_DC_BLK_STEP_ADDR 0x0300
#define SW_DC_BLK_ALPHA_STEP3_OFFSET 16
#define SW_DC_BLK_ALPHA_STEP3_MASK 0x00FF0000
#define SW_DC_BLK_ALPHA_STEP2_OFFSET 8
#define SW_DC_BLK_ALPHA_STEP2_MASK 0x0000FF00
#define SW_DC_BLK_ALPHA_STEP1_OFFSET 0
#define SW_DC_BLK_ALPHA_STEP1_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_DC_BLK_STAGE_DLY_ADDR 0x0304
#define SW_DC_BLK_STAGE2_DLY_OFFSET 8
#define SW_DC_BLK_STAGE2_DLY_MASK 0x0000FF00
#define SW_DC_BLK_STAGE1_DLY_OFFSET 0
#define SW_DC_BLK_STAGE1_DLY_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_TX_TONE_CFG_ADDR 0x0400
#define SW_TONE_CFG_EN_OFFSET 19
#define SW_TONE_CFG_EN_MASK 0x00080000
#define SW_TONE_CFG_NUM_OFFSET 8
#define SW_TONE_CFG_NUM_MASK 0x0007FF00
#define SW_DIG_GAIN_OFFSET 0
#define SW_DIG_GAIN_MASK 0x000000FF

//-----------------------------------
#define CFG_PHY_DFE_VERSION_ADDR 0x0ffc
#define SW_DFE_VERSION_OFFSET 0
#define SW_DFE_VERSION_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SS_ADDR 

//HW module read/write macro
#define PHY_DFE_READ_REG(addr) SOC_READ_REG(PHY_DFE_BASEADDR + addr)
#define PHY_DFE_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_DFE_BASEADDR + addr,value)