kunlun/inc/hw/reg/riscv/15/rgf_mac_rx_desc.h

//-----------------------------------
#define CFG_RX_ATTEN_ADDR 0x0000
#define RX_RATE_MODE_OFFSET 30
#define RX_RATE_MODE_MASK 0xC0000000
#define ATTEN_RX_PROTO_OFFSET 28
#define ATTEN_RX_PROTO_MASK 0x30000000
#define ATTEN_RX_ABORT_OFFSET 27
#define ATTEN_RX_ABORT_MASK 0x08000000
#define ATTEN_RX_BAND_SEL_OFFSET 25
#define ATTEN_RX_BAND_SEL_MASK 0x06000000
#define ATTEN_RX_PHASE_OFFSET 23
#define ATTEN_RX_PHASE_MASK 0x01800000
#define ATTEN_RX_PORT_OFFSET 21
#define ATTEN_RX_PORT_MASK 0x00600000
#define ATTEN_PB_NUM_OFFSET 17
#define ATTEN_PB_NUM_MASK 0x001E0000
#define ATTEN_RING_ID_OFFSET 14
#define ATTEN_RING_ID_MASK 0x0001C000
#define ATTEN_DIRECTED_OFFSET 13
#define ATTEN_DIRECTED_MASK 0x00002000
#define ATTEN_RX_BUF_NUM_OFFSET 9
#define ATTEN_RX_BUF_NUM_MASK 0x00001E00
#define ATTEN_IS_FCSERR_OFFSET 8
#define ATTEN_IS_FCSERR_MASK 0x00000100
#define ATTEN_IS_OVERFLOW_OFFSET 7
#define ATTEN_IS_OVERFLOW_MASK 0x00000080
#define ATTEN_IS_PHYERR_OFFSET 6
#define ATTEN_IS_PHYERR_MASK 0x00000040
#define ATTEN_ENCRYPTED_OFFSET 5
#define ATTEN_ENCRYPTED_MASK 0x00000020
#define ATTEN_PB_BITMAP_OFFSET 1
#define ATTEN_PB_BITMAP_MASK 0x0000001E
#define ATTEN_RX_MPDU_DONE_OFFSET 0
#define ATTEN_RX_MPDU_DONE_MASK 0x00000001

//-----------------------------------
#define CFG_RX_MPDU_START_0_ADDR 0x0004
#define FC0_OFFSET 0
#define FC0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_MPDU_START_1_ADDR 0x0008
#define FC1_OFFSET 0
#define FC1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_MPDU_START_2_ADDR 0x000c
#define FC2_OFFSET 0
#define FC2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_MPDU_START_3_ADDR 0x0010
#define FC3_OFFSET 0
#define FC3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_MPDU_START_4_ADDR 0x0014
#define ESTIMATED_PPM_OFFSET 24
#define ESTIMATED_PPM_MASK 0xFF000000
#define ESTIMATED_DC_OFFSET 16
#define ESTIMATED_DC_MASK 0x00FF0000
#define AGC_GAIN_ENTRY_OFFSET 8
#define AGC_GAIN_ENTRY_MASK 0x0000FF00
#define ADC_POWER_OFFSET 0
#define ADC_POWER_MASK 0x000000FF

//-----------------------------------
#define CFG_RX_MPDU_START_5_ADDR 0x0018
#define MAX_SPUR_ID_OFFSET 24
#define MAX_SPUR_ID_MASK 0xFF000000
#define REMAINED_PHASE_FRAC_OFFSET 16
#define REMAINED_PHASE_FRAC_MASK 0x00FF0000
#define PREAMBLE_SYMB_FOR_DETECT_OFFSET 8
#define PREAMBLE_SYMB_FOR_DETECT_MASK 0x0000FF00
#define AVG_SNR_OFFSET 0
#define AVG_SNR_MASK 0x000000FF

//-----------------------------------
#define CFG_RX_MPDU_START_6_ADDR 0x001c
#define RX_RATE_MODE_OFFSET 30
#define RX_RATE_MODE_MASK 0xC0000000
#define AES_KEY_IDX_OFFSET 21
#define AES_KEY_IDX_MASK 0x3FE00000
#define RX_BAND_SEL_OFFSET 19
#define RX_BAND_SEL_MASK 0x00180000
#define RX_PHASE_OFFSET 17
#define RX_PHASE_MASK 0x00060000
#define RX_PORT_OFFSET 15
#define RX_PORT_MASK 0x00018000
#define RX_PROTO_OFFSET 13
#define RX_PROTO_MASK 0x00006000
#define HP10FC_OFFSET 12
#define HP10FC_MASK 0x00001000
#define RX_PB_NUM_OFFSET 9
#define RX_PB_NUM_MASK 0x00000E00
#define RING_ID_OFFSET 6
#define RING_ID_MASK 0x000001C0
#define DIRECTED_OFFSET 5
#define DIRECTED_MASK 0x00000020
#define START_RESV2_OFFSET 0
#define START_RESV2_MASK 0x0000001F

//-----------------------------------
#define CFG_RX_MPDU_END_0_ADDR 0x0020
#define END_RESV1_OFFSET 30
#define END_RESV1_MASK 0xC0000000
#define RX_ERR_FD_OVERFLOW_OFFSET 29
#define RX_ERR_FD_OVERFLOW_MASK 0x20000000
#define RX_ERR_FC_PARSER_TIMEOUT_OFFSET 28
#define RX_ERR_FC_PARSER_TIMEOUT_MASK 0x10000000
#define RX_ERR_POWER_UP_OFFSET 27
#define RX_ERR_POWER_UP_MASK 0x08000000
#define RX_ERR_POWER_SAT_OFFSET 26
#define RX_ERR_POWER_SAT_MASK 0x04000000
#define RX_ERR_POWER_DROP_OFFSET 25
#define RX_ERR_POWER_DROP_MASK 0x02000000
#define IS_FCSERR_OFFSET 24
#define IS_FCSERR_MASK 0x01000000
#define IS_OVERFLOW_OFFSET 23
#define IS_OVERFLOW_MASK 0x00800000
#define RX_PHYERR_ID_OFFSET 18
#define RX_PHYERR_ID_MASK 0x007C0000
#define RX_IS_PHYERR_OFFSET 17
#define RX_IS_PHYERR_MASK 0x00020000
#define ENCRYPTED_OFFSET 16
#define ENCRYPTED_MASK 0x00010000
#define SNR_OFFSET 8
#define SNR_MASK 0x0000FF00
#define PB_BITMAP_OFFSET 4
#define PB_BITMAP_MASK 0x000000F0
#define RX_ABNORMAL_ID_OFFSET 1
#define RX_ABNORMAL_ID_MASK 0x0000000E
#define RX_MPDU_DONE_OFFSET 0
#define RX_MPDU_DONE_MASK 0x00000001

//-----------------------------------
#define CFG_RX_MPDU_END_1_ADDR 0x0024
#define NTB_TIMESTAMP_OFFSET 0
#define NTB_TIMESTAMP_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_MPDU_END_2_ADDR 0x0028
#define LOCAL_TIMESTAMP_OFFSET 0
#define LOCAL_TIMESTAMP_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_MPDU_END_3_ADDR 0x002c
#define RX_BB_LEN_OFFSET 23
#define RX_BB_LEN_MASK 0xFF800000
#define RX_ABORT_OFFSET 22
#define RX_ABORT_MASK 0x00400000
#define DESC_RX_ZC_OFFSET_OFFSET 6
#define DESC_RX_ZC_OFFSET_MASK 0x003FFFC0
#define RX_NTB_TIMESTAMP_CYCLE_OFFSET 4
#define RX_NTB_TIMESTAMP_CYCLE_MASK 0x00000030
#define RX_BUF_NUM_OFFSET 0
#define RX_BUF_NUM_MASK 0x0000000F

//-----------------------------------
#define CFG_RX_PB_START_0_ADDR 0x0030
#define PB_START_RESV0_OFFSET 8
#define PB_START_RESV0_MASK 0xFFFFFF00
#define FIRST_PB_OFFSET 7
#define FIRST_PB_MASK 0x00000080
#define LAST_PB_OFFSET 6
#define LAST_PB_MASK 0x00000040
#define PB_START_RESV1_OFFSET 0
#define PB_START_RESV1_MASK 0x0000003F

//-----------------------------------
#define CFG_RX_PB_START_1_ADDR 0x0034
#define PB_START_RESV2_OFFSET 31
#define PB_START_RESV2_MASK 0x80000000
#define VPBF_OFFSET 30
#define VPBF_MASK 0x40000000
#define OPSF_OFFSET 29
#define OPSF_MASK 0x20000000
#define IS_MGMT_OFFSET 28
#define IS_MGMT_MASK 0x10000000
#define BOUNDARY_OFFSET_OFFSET 19
#define BOUNDARY_OFFSET_MASK 0x0FF80000
#define BOUNDARY_FLAG_OFFSET 18
#define BOUNDARY_FLAG_MASK 0x00040000
#define MSDU_END_OFFSET 17
#define MSDU_END_MASK 0x00020000
#define MSDU_START_OFFSET 16
#define MSDU_START_MASK 0x00010000
#define SSN_OFFSET 0
#define SSN_MASK 0x0000FFFF

//-----------------------------------
#define CFG_RX_PB_END_0_ADDR 0x0038
#define PB_END_RESV0_OFFSET 5
#define PB_END_RESV0_MASK 0xFFFFFFE0
#define RX_PB_CRC_ERR_OFFSET 4
#define RX_PB_CRC_ERR_MASK 0x00000010
#define RX_PB_DONE_OFFSET 3
#define RX_PB_DONE_MASK 0x00000008
#define RX_BEACON_PLD_CRC_ERR_OFFSET 2
#define RX_BEACON_PLD_CRC_ERR_MASK 0x00000004
#define PB_END_RESV1_OFFSET 0
#define PB_END_RESV1_MASK 0x00000003

//-----------------------------------
#define CFG_RX_PB_END_1_ADDR 0x003c
#define PB_CRC_OFFSET 0
#define PB_CRC_MASK 0xFFFFFFFF

//HW module read/write macro
#define RGF_MAC_RX_DESC_READ_REG(addr) SOC_READ_REG(RGF_MAC_RX_DESC_BASEADDR + addr)
#define RGF_MAC_RX_DESC_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_MAC_RX_DESC_BASEADDR + addr,value)