kunlun/inc/hw/reg/riscv2/15/rgf_fisheye.h

//-----------------------------------
#define CFG_FISHEYE_SRC_CTRL0_ADDR 0x0000
#define FISHEYE_SRC_WIDTH_OFFSET 16
#define FISHEYE_SRC_WIDTH_MASK 0x07FF0000
#define FISHEYE_SRC_HEIGHT_OFFSET 0
#define FISHEYE_SRC_HEIGHT_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_SRC_CTRL1_ADDR 0x0004
#define FISHEYE_SRC_VIRTUAL_ROW_OFFSET_OFFSET 16
#define FISHEYE_SRC_VIRTUAL_ROW_OFFSET_MASK 0x00FF0000
#define FISHEYE_SRC_VIRTUAL_WIDTH_OFFSET 0
#define FISHEYE_SRC_VIRTUAL_WIDTH_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_SRC_CTRL2_ADDR 0x0008
#define FISHEYE_SRC_BASE_ADDRESS_OFFSET 0
#define FISHEYE_SRC_BASE_ADDRESS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_FISHEYE_SRC_CTRL3_ADDR 0x000C
#define FISHEYE_SRC_CROP_Y0_OFFSET 16
#define FISHEYE_SRC_CROP_Y0_MASK 0x07FF0000
#define FISHEYE_SRC_CROP_X0_OFFSET 3
#define FISHEYE_SRC_CROP_X0_MASK 0x000007F8

//-----------------------------------
#define CFG_FISHEYE_SRC_CTRL4_ADDR 0x0010
#define FISHEYE_SRC_CROP_Y1_OFFSET 16
#define FISHEYE_SRC_CROP_Y1_MASK 0x07FF0000
#define FISHEYE_SRC_CROP_X1_OFFSET 3
#define FISHEYE_SRC_CROP_X1_MASK 0x000007F8

//-----------------------------------
#define CFG_FISHEYE_DST_CTRL0_ADDR 0x0014
#define FISHEYE_DST_WIDTH_OFFSET 16
#define FISHEYE_DST_WIDTH_MASK 0x07FF0000
#define FISHEYE_DST_HEIGHT_OFFSET 0
#define FISHEYE_DST_HEIGHT_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_DST_CTRL1_ADDR 0x0018
#define FISHEYE_DST_VIRTUAL_ROW_OFFSET_OFFSET 16
#define FISHEYE_DST_VIRTUAL_ROW_OFFSET_MASK 0x00FF0000
#define FISHEYE_DST_VIRTUAL_WIDTH_OFFSET 0
#define FISHEYE_DST_VIRTUAL_WIDTH_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_DST_CTRL2_ADDR 0x001C
#define FISHEYE_DST_BASE_ADDRESS_OFFSET 0
#define FISHEYE_DST_BASE_ADDRESS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_FISHEYE_DST_CTRL3_ADDR 0x0020
#define FISHEYE_DST_CROP_Y0_OFFSET 16
#define FISHEYE_DST_CROP_Y0_MASK 0x07FF0000
#define FISHEYE_DST_CROP_X0_OFFSET 0
#define FISHEYE_DST_CROP_X0_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_DST_CTRL4_ADDR 0x0024
#define FISHEYE_DST_CROP_Y1_OFFSET 16
#define FISHEYE_DST_CROP_Y1_MASK 0x07FF0000
#define FISHEYE_DST_CROP_X1_OFFSET 0
#define FISHEYE_DST_CROP_X1_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_CAM_PARAM0_ADDR 0x0028
#define FISHEYE_ALPHA_OFFSET 24
#define FISHEYE_ALPHA_MASK 0x3F000000
#define FISHEYE_CAM_FY_FX_OFFSET 0
#define FISHEYE_CAM_FY_FX_MASK 0x0001FFFF

//-----------------------------------
#define CFG_FISHEYE_CAM_PARAM1_ADDR 0x002C
#define FISHEYE_CAM_U0_OFFSET 16
#define FISHEYE_CAM_U0_MASK 0x7FFF0000
#define FISHEYE_CAM_V0_OFFSET 0
#define FISHEYE_CAM_V0_MASK 0x00007FFF

//-----------------------------------
#define CFG_FISHEYE_NEW_CAM_PARAM0_ADDR 0x0030
#define FISHEYE_RECIP_NEW_CAM_FX_OFFSET 0
#define FISHEYE_RECIP_NEW_CAM_FX_MASK 0x0003FFFF

//-----------------------------------
#define CFG_FISHEYE_NEW_CAM_PARAM1_ADDR 0x0034
#define FISHEYE_RECIP_NEW_CAM_FY_OFFSET 0
#define FISHEYE_RECIP_NEW_CAM_FY_MASK 0x0003FFFF

//-----------------------------------
#define CFG_FISHEYE_NEW_CAM_PARAM2_ADDR 0x0038
#define FISHEYE_NEW_CAM_V0_OFFSET 16
#define FISHEYE_NEW_CAM_V0_MASK 0x3FFF0000
#define FISHEYE_NEW_CAM_U0_OFFSET 0
#define FISHEYE_NEW_CAM_U0_MASK 0x00003FFF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_CTRL_ADDR 0x003C
#define FISHEYE_LUT_SCALE_OFFSET 16
#define FISHEYE_LUT_SCALE_MASK 0x007F0000
#define FISHEYE_NUM_VSCAN_OFFSET 0
#define FISHEYE_NUM_VSCAN_MASK 0x0000001F

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG0_ADDR 0x0040
#define FISHEYE_SRC_UPPER_ROW0_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW0_MASK 0x07FF0000
#define FISHEYE_WIDTH0_OFFSET 11
#define FISHEYE_WIDTH0_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW0_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW0_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG0_ADDR 0x0044
#define FISHEYE_DST_UPPER_ROW0_OFFSET 16
#define FISHEYE_DST_UPPER_ROW0_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW0_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW0_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG1_ADDR 0x0048
#define FISHEYE_SRC_UPPER_ROW1_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW1_MASK 0x07FF0000
#define FISHEYE_WIDTH1_OFFSET 11
#define FISHEYE_WIDTH1_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW1_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW1_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG1_ADDR 0x004C
#define FISHEYE_DST_UPPER_ROW1_OFFSET 16
#define FISHEYE_DST_UPPER_ROW1_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW1_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW1_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG2_ADDR 0x0050
#define FISHEYE_SRC_UPPER_ROW2_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW2_MASK 0x07FF0000
#define FISHEYE_WIDTH2_OFFSET 11
#define FISHEYE_WIDTH2_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW2_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW2_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG2_ADDR 0x0054
#define FISHEYE_DST_UPPER_ROW2_OFFSET 16
#define FISHEYE_DST_UPPER_ROW2_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW2_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW2_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG3_ADDR 0x0058
#define FISHEYE_SRC_UPPER_ROW3_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW3_MASK 0x07FF0000
#define FISHEYE_WIDTH3_OFFSET 11
#define FISHEYE_WIDTH3_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW3_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW3_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG3_ADDR 0x005C
#define FISHEYE_DST_UPPER_ROW3_OFFSET 16
#define FISHEYE_DST_UPPER_ROW3_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW3_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW3_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG4_ADDR 0x0060
#define FISHEYE_SRC_UPPER_ROW4_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW4_MASK 0x07FF0000
#define FISHEYE_WIDTH4_OFFSET 11
#define FISHEYE_WIDTH4_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW4_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW4_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG4_ADDR 0x0064
#define FISHEYE_DST_UPPER_ROW4_OFFSET 16
#define FISHEYE_DST_UPPER_ROW4_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW4_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW4_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG5_ADDR 0x0068
#define FISHEYE_SRC_UPPER_ROW5_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW5_MASK 0x07FF0000
#define FISHEYE_WIDTH5_OFFSET 11
#define FISHEYE_WIDTH5_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW5_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW5_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG5_ADDR 0x006C
#define FISHEYE_DST_UPPER_ROW5_OFFSET 16
#define FISHEYE_DST_UPPER_ROW5_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW5_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW5_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG6_ADDR 0x0070
#define FISHEYE_SRC_UPPER_ROW6_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW6_MASK 0x07FF0000
#define FISHEYE_WIDTH6_OFFSET 11
#define FISHEYE_WIDTH6_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW6_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW6_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG6_ADDR 0x0074
#define FISHEYE_DST_UPPER_ROW6_OFFSET 16
#define FISHEYE_DST_UPPER_ROW6_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW6_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW6_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG7_ADDR 0x0078
#define FISHEYE_SRC_UPPER_ROW7_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW7_MASK 0x07FF0000
#define FISHEYE_WIDTH7_OFFSET 11
#define FISHEYE_WIDTH7_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW7_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW7_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG7_ADDR 0x007C
#define FISHEYE_DST_UPPER_ROW7_OFFSET 16
#define FISHEYE_DST_UPPER_ROW7_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW7_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW7_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG8_ADDR 0x0080
#define FISHEYE_SRC_UPPER_ROW8_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW8_MASK 0x07FF0000
#define FISHEYE_WIDTH8_OFFSET 11
#define FISHEYE_WIDTH8_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW8_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW8_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG8_ADDR 0x0084
#define FISHEYE_DST_UPPER_ROW8_OFFSET 16
#define FISHEYE_DST_UPPER_ROW8_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW8_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW8_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG9_ADDR 0x0088
#define FISHEYE_SRC_UPPER_ROW9_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW9_MASK 0x07FF0000
#define FISHEYE_WIDTH9_OFFSET 11
#define FISHEYE_WIDTH9_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW9_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW9_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG9_ADDR 0x008C
#define FISHEYE_DST_UPPER_ROW9_OFFSET 16
#define FISHEYE_DST_UPPER_ROW9_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW9_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW9_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG10_ADDR 0x0090
#define FISHEYE_SRC_UPPER_ROW10_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW10_MASK 0x07FF0000
#define FISHEYE_WIDTH10_OFFSET 11
#define FISHEYE_WIDTH10_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW10_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW10_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG10_ADDR 0x0094
#define FISHEYE_DST_UPPER_ROW10_OFFSET 16
#define FISHEYE_DST_UPPER_ROW10_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW10_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW10_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG11_ADDR 0x0098
#define FISHEYE_SRC_UPPER_ROW11_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW11_MASK 0x07FF0000
#define FISHEYE_WIDTH11_OFFSET 11
#define FISHEYE_WIDTH11_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW11_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW11_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG11_ADDR 0x009C
#define FISHEYE_DST_UPPER_ROW11_OFFSET 16
#define FISHEYE_DST_UPPER_ROW11_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW11_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW11_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG12_ADDR 0x00A0
#define FISHEYE_SRC_UPPER_ROW12_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW12_MASK 0x07FF0000
#define FISHEYE_WIDTH12_OFFSET 11
#define FISHEYE_WIDTH12_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW12_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW12_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG12_ADDR 0x00A4
#define FISHEYE_DST_UPPER_ROW12_OFFSET 16
#define FISHEYE_DST_UPPER_ROW12_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW12_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW12_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG13_ADDR 0x00A8
#define FISHEYE_SRC_UPPER_ROW13_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW13_MASK 0x07FF0000
#define FISHEYE_WIDTH13_OFFSET 11
#define FISHEYE_WIDTH13_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW13_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW13_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG13_ADDR 0x00AC
#define FISHEYE_DST_UPPER_ROW13_OFFSET 16
#define FISHEYE_DST_UPPER_ROW13_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW13_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW13_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG14_ADDR 0x00B0
#define FISHEYE_SRC_UPPER_ROW14_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW14_MASK 0x07FF0000
#define FISHEYE_WIDTH14_OFFSET 11
#define FISHEYE_WIDTH14_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW14_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW14_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG14_ADDR 0x00B4
#define FISHEYE_DST_UPPER_ROW14_OFFSET 16
#define FISHEYE_DST_UPPER_ROW14_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW14_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW14_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_SRC_CFG15_ADDR 0x00B8
#define FISHEYE_SRC_UPPER_ROW15_OFFSET 16
#define FISHEYE_SRC_UPPER_ROW15_MASK 0x07FF0000
#define FISHEYE_WIDTH15_OFFSET 11
#define FISHEYE_WIDTH15_MASK 0x0000F800
#define FISHEYE_SRC_BOTTOM_ROW15_OFFSET 0
#define FISHEYE_SRC_BOTTOM_ROW15_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_FISHEYE_VSCAN_DST_CFG15_ADDR 0x00BC
#define FISHEYE_DST_UPPER_ROW15_OFFSET 16
#define FISHEYE_DST_UPPER_ROW15_MASK 0x07FF0000
#define FISHEYE_DST_BOTTOM_ROW15_OFFSET 0
#define FISHEYE_DST_BOTTOM_ROW15_MASK 0x000007FF

//-----------------------------------
#define CFG_FISHEYE_RESIZE_CTRL0_ADDR 0x00C0
#define FISHEYE_RESIZE_EN_OFFSET 0
#define FISHEYE_RESIZE_EN_MASK 0x00000001

//-----------------------------------
#define CFG_FISHEYE_RESIZE_CTRL1_ADDR 0x00C4
#define FISHEYE_H_RATIO_OFFSET 0
#define FISHEYE_H_RATIO_MASK 0x07FFFFFF

//-----------------------------------
#define CFG_FISHEYE_RESIZE_CTRL2_ADDR 0x00C8
#define FISHEYE_V_RATIO_OFFSET 0
#define FISHEYE_V_RATIO_MASK 0x07FFFFFF

//-----------------------------------
#define CFG_FISHEYE_GLB_CTRL_ADDR 0x00CC
#define FISHEYE_STATUS_OFFSET 31
#define FISHEYE_STATUS_MASK 0x80000000
#define FISHEYE_FORCE_ON_OFFSET 8
#define FISHEYE_FORCE_ON_MASK 0x00000100
#define FISHEYE_START_OFFSET 0
#define FISHEYE_START_MASK 0x00000001

//-----------------------------------
#define CFG_FISHEYE_INT_CLR_ADDR 0x00D0
#define FISHEYE_INT_CLR_OFFSET 0
#define FISHEYE_INT_CLR_MASK 0x00000001

//HW module read/write macro
#define RGF_FISHEYE_READ_REG(addr) SOC_READ_REG(RGF_FISHEYE_BASEADDR + addr)
#define RGF_FISHEYE_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_FISHEYE_BASEADDR + addr,value)