82 lines
2.8 KiB
C
82 lines
2.8 KiB
C
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//-----------------------------------
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#define CFG_WDG_RVER_ADDR 0x0000
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#define WDG_RF_VER_OFFSET 0
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#define WDG_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_WDG_CTL0_ADDR 0x0004
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#define WDG_FULLRST_CNT_EN_OFFSET 24
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#define WDG_FULLRST_CNT_EN_MASK 0x01000000
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#define WDG_CPURST_CNT_EN_OFFSET 16
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#define WDG_CPURST_CNT_EN_MASK 0x00010000
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#define WDG_TIMEOUT_CNT_EN_OFFSET 8
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#define WDG_TIMEOUT_CNT_EN_MASK 0x00000100
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#define WDG_CNT_EN_OFFSET 0
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#define WDG_CNT_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_WDG_CTL1_ADDR 0x0008
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#define WDG_FULLRST_EN_OFFSET 24
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#define WDG_FULLRST_EN_MASK 0x01000000
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#define WDG_CPURST_EN_OFFSET 16
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#define WDG_CPURST_EN_MASK 0x00010000
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#define WDG_TIMEOUT_INTER_EN_OFFSET 8
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#define WDG_TIMEOUT_INTER_EN_MASK 0x00000100
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#define WDG_INTER_EN_OFFSET 0
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#define WDG_INTER_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_WDG_CTL2_ADDR 0x000c
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#define FEED_DOG_CODE_OFFSET 0
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#define FEED_DOG_CODE_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_WDG_CNT_ADDR 0x0010
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#define WDG_CNT_OFFSET 0
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#define WDG_CNT_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_WDG_CMP_ADDR 0x0014
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#define WDG_CMP_OFFSET 0
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#define WDG_CMP_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_WDG_INT_RST_CNT_ADDR 0x0018
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#define WDG_FULLRST_CNT_OFFSET 16
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#define WDG_FULLRST_CNT_MASK 0x00FF0000
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#define WDG_CPURST_CNT_OFFSET 8
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#define WDG_CPURST_CNT_MASK 0x0000FF00
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#define WDG_TIMEOUT_CNT_OFFSET 0
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#define WDG_TIMEOUT_CNT_MASK 0x000000FF
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//-----------------------------------
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#define CFG_WDG_INT_RST_CMP_ADDR 0x001c
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#define WDG_FULLRST_CMP_OFFSET 16
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#define WDG_FULLRST_CMP_MASK 0x00FF0000
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#define WDG_CPURST_CMP_OFFSET 8
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#define WDG_CPURST_CMP_MASK 0x0000FF00
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#define WDG_TIMEOUT_CMP_OFFSET 0
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#define WDG_TIMEOUT_CMP_MASK 0x000000FF
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//-----------------------------------
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#define CFG_WDG_CPURST_WIDTH_ADDR 0x0020
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#define WDG_CPURST_WIDTH_OFFSET 0
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#define WDG_CPURST_WIDTH_MASK 0x000000FF
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//-----------------------------------
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#define CFG_WDG_PROTECT_REG_ADDR 0x080
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#define WDG_PROTECT_CODE_OFFSET 0
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#define WDG_PROTECT_CODE_MASK 0xFFFFFFFF
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//HW module read/write macro
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#define WDG0_READ_REG(addr) SOC_READ_REG(WDG0_BASEADDR + addr)
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#define WDG0_WRITE_REG(addr,value) SOC_WRITE_REG(WDG0_BASEADDR + addr,value)
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#define WDG1_READ_REG(addr) SOC_READ_REG(WDG1_BASEADDR + addr)
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#define WDG1_WRITE_REG(addr,value) SOC_WRITE_REG(WDG1_BASEADDR + addr,value)
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#define WDG2_READ_REG(addr) SOC_READ_REG(WDG2_BASEADDR + addr)
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#define WDG2_WRITE_REG(addr,value) SOC_WRITE_REG(WDG2_BASEADDR + addr,value)
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#define WDG3_READ_REG(addr) SOC_READ_REG(WDG3_BASEADDR + addr)
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#define WDG3_WRITE_REG(addr,value) SOC_WRITE_REG(WDG3_BASEADDR + addr,value)
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#define WDG4_READ_REG(addr) SOC_READ_REG(WDG4_BASEADDR + addr)
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#define WDG4_WRITE_REG(addr,value) SOC_WRITE_REG(WDG4_BASEADDR + addr,value)
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