kunlun/plc/halmac/hw2/zc/mac_zc_hw.c

/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/
#include "mac_sys_reg.h"
#include "hw_reg_api.h"
#include "os_types.h"
#include "os_mem_api.h"
#include "plc_protocol.h"
#include "iot_config_api.h"

#include "iot_io_api.h"
#include "mac_zc_hw.h"
#include "gpio_mtx_reg.h"
#include "gpio_mtx.h"
#include "hw_zc_cmn.h"

/* config frequecy interfere filter */
static void mac_zc_hw_filter_cfg(uint32_t filter_low, uint32_t filter_high)
{
    uint32_t reg = RGF_MAC_READ_REG(CFG_ZC_SOLID_CNT_ADDR);
    REG_FIELD_SET(CFG_SOLID_LOW_CNT, reg, filter_low);
    REG_FIELD_SET(CFG_SOLID_HIGH_CNT, reg, filter_high);
    RGF_MAC_WRITE_REG(CFG_ZC_SOLID_CNT_ADDR, reg);
}

/* get current hw logic select */
static uint8_t mac_zc_get_hw_logic_sel(void)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp, sel_mac, zc_bypass;
    /* select zc hw logic */
    tmp = RGF_MAC_READ_REG(CFG_RX_PHASE_PROTECT_ADDR);
    sel_mac = REG_FIELD_GET(CFG_ZC_IN_SEL_MAC, tmp);
    zc_bypass = REG_FIELD_GET(CFG_ZC_EN_BYPASS_MAC, tmp);
    if ((sel_mac == MAC_ZC_HW_LOGIC_KL2) &&
        (zc_bypass == MAC_ZC_HW_LOGIC_KL2)) {
        return MAC_ZC_HW_LOGIC_KL2;
    } else {
        return MAC_ZC_HW_LOGIC_KL1;
    }
#else
    return 0;
#endif
}

void mac_zc_hw_logic_sel(uint8_t chip_hw_logic_id)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp;
    /* select zc hw logic */
    tmp = RGF_MAC_READ_REG(CFG_RX_PHASE_PROTECT_ADDR);
    REG_FIELD_SET(CFG_ZC_IN_SEL_MAC, tmp, !!chip_hw_logic_id);
    REG_FIELD_SET(CFG_ZC_EN_BYPASS_MAC, tmp, !!chip_hw_logic_id);
    RGF_MAC_WRITE_REG(CFG_RX_PHASE_PROTECT_ADDR, tmp);

    if (chip_hw_logic_id != MAC_ZC_HW_LOGIC_KL2) {
        return;
    }

    /* config frequecy interfere filter */
    mac_zc_hw_filter_cfg(MAC_ZC_HW_FILTER_LOW_CNT, MAC_ZC_HW_FILTER_HIGH_CNT);
#else
    (void)chip_hw_logic_id;
#endif
}

void mac_zc_hw_capx_reset_trig(uint8_t signal_id, uint8_t cap_edge)
{
#if (HW_PLATFORM >= HW_PLATFORM_FPGA) //gpio drive not check simulator
    uint32_t cap_depth;
    if (MAC_ZC_HW_LOGIC_KL2 == mac_zc_get_hw_logic_sel()) {
        return;
    }
    /* backup reg setting */
    cap_depth = mac_zc_hw_cap_get_watermark();
    /* set zc int num 0 for zc save ptr reset */
    mac_zc_hw_cap_set_watermark(0);

    uint32_t reg = CFG_SIG0_IN_CFG_ADDR + (signal_id << 2);
    if (MAC_ZC_HW_CAP_EDGE_RISE == cap_edge) {
        /* set signal input: low -> high to reset cap */
        gpio_mtx_sig_in_set_def(reg, MTX_HW_SIG_SEL_INPUT_LOW);
        gpio_mtx_sig_in_set_def(reg, MTX_HW_SIG_SEL_INPUT_HIGH);
    } else {
        /* set signal input: high -> low to reset cap */
        gpio_mtx_sig_in_set_def(reg, MTX_HW_SIG_SEL_INPUT_HIGH);
        gpio_mtx_sig_in_set_def(reg, MTX_HW_SIG_SEL_INPUT_LOW);
    }
    gpio_mtx_sig_in_set_def(reg, MTX_HW_SIG_SEL_INPUT_ZC);
    /* restore mac zc int num config */
    mac_zc_hw_cap_set_watermark((uint8_t)cap_depth);
#else
    (void)signal_id;
    (void)cap_edge;
#endif
}

uint32_t mac_zc_hw_get_cap_data(uint32_t *buf, uint8_t cap_id, uint32_t buf_sz)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t fifo_data_base_addr = CFG_ZC0_FIFO_DAT0_ADDR;
    uint32_t fifo_state_base_addr = CFG_ZC0_FIFO_DAT1_ADDR;
    uint32_t addr_shift = CFG_ZC1_FIFO_DAT0_ADDR - CFG_ZC0_FIFO_DAT0_ADDR;
    uint32_t reg, fifo_num = 0, i;

    IOT_ASSERT(buf && cap_id < MAC_ZC_HW_CAP_CNT && buf_sz > 0);
    /* current hw logic select kl1 */
    if (MAC_ZC_HW_LOGIC_KL2 != mac_zc_get_hw_logic_sel()) {
        os_mem_cpy(buf, mac_zc_hw_get_ts_base_addr(cap_id), buf_sz);
        return buf_sz;
    }
    /* get fifo valid number */
    reg = RGF_MAC_READ_REG(fifo_state_base_addr + addr_shift * cap_id);
    fifo_num = REG_FIELD_GET(ZC0_FIFO_DATA_NUM, reg);
    /* get fifo valid data */
    for (i = 0; i < fifo_num && i < buf_sz; i++) {
        buf[i] = RGF_MAC_READ_REG(fifo_data_base_addr + addr_shift * cap_id);
    }
    /* clear fifo data */
    reg = RGF_MAC_READ_REG(CFG_ZC_GEN_CTRL_ADDR);
    reg |= (1 << (CFG_ZC_CAP_CLR_0_OFFSET + cap_id));
    RGF_MAC_WRITE_REG(CFG_ZC_GEN_CTRL_ADDR, reg);
    return i;
#else
    (void)buf;
    (void)cap_id;
    return 0;
#endif
}

/* init zc hw */
void mac_zc_hw_init(uint8_t is_half_collect, uint8_t cap_edge)
{
    /* choose use KL2's zc block */
    mac_zc_hw_logic_sel(MAC_ZC_HW_LOGIC_KL2);
    /* set mac zc hw capture period: half or full period capture */
    mac_zc_hw_cap_set_period(is_half_collect);
    /* set mac zc hw capture edge: rise or fall edge capture */
    mac_zc_hw_cap_set_edge(cap_edge);
    /* set mac zc hw N+1 period interval capture zc timestamp */
    /* set 0 to let sample every period (0+1=1) */
    mac_zc_hw_cap_set_interval(0);
    /* set mac zc hw N+1 cnt capture generate interrupt */
    mac_zc_hw_cap_set_watermark(0);

    /* set mac zc hw gen offset. not offset */
    mac_zc_hw_gen_set_offset(0, MAC_ZC_HW_GEN_OFFSET_RIGHT);
    /* set mac zc hw ctrl vibrate protect duration ntb */
    mac_zc_hw_set_vibrate_protect_dur(MAC_ZC_HW_VIBRATE_PROTECT_NTB);
    /* set mac zc hw cap0 input select mtx: detect0 */
    mac_zc_hw_gen_set_phase_sel_mtx(MAC_ZC_HW_DETECT0);
    /* set mac zc hw gen period: half or full period */
    mac_zc_hw_gen_set_ctrl_period(is_half_collect);
}