105 lines
3.1 KiB
C
105 lines
3.1 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#ifndef _BB_CPU_MAC_ISR_H_
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#define _BB_CPU_MAC_ISR_H_
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/* os shim includes */
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#include "os_types.h"
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#include "mac_rf_isr.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* bb cpu to mac */
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/* the reason of cpu1 trigger mac is tx done */
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#define BB_CPU_TRIGGER_MAC_TX_DONE 0
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/* the reason of cpu1 trigger mac is rx done */
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#define BB_CPU_TRIGGER_MAC_RX_DONE 1
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/* the reason of bb cpu trigger mac is need rx sack */
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#define BB_CPU_TRIGGER_MAC_NEED_RX_SACK 2
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/* the reason of bb cpu trigger mac is reset complete */
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#define BB_CPU_TRIGGER_MAC_STOP_SCHE_COMPLETE 3
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/* the reason of bb cpu trigger mac is rx abort complete */
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#define BB_CPU_TRIGGER_MAC_RX_ABORT_COMPLETE 4
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/* the reason of bb cpu trigger mac is backoff timeout, bbcpu is ready */
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#define BB_CPU_TRIGGER_MAC_BBCPU_IS_READY 5
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/* the reason of bb cpu trigger mac is tx abort complete */
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#define BB_CPU_TRIGGER_MAC_TX_ABORT_COMPLETE 6
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/* the reason of bb cpu trigger mac is cmdlist done complete */
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#define BB_CPU_TRIGGER_MAC_CMSLIST_DONE 7
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/* the reason of bb cpu trigger mac rx sack done */
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#define BB_CPU_TRIGGER_MAC_RX_SACK_DONE 8
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/**
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* @brief bb_cpu_mac_isr_init() - initialize bb cpu mac isr interrupt.
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*
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* @param none
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*
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* @return none
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*/
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void bb_cpu_mac_isr_init(void);
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/**
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* @brief bb_cpu_mac_isr_start() - start bb cpu mac isr interrupt.
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*
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* @param none
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*
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* @return none
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*/
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void bb_cpu_mac_isr_start(void);
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/**
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* @brief bb_cpu_mac_isr_stop() - stop bb cpu mac isr interrupt.
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*
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* @param none
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*
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* @return none
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*/
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void bb_cpu_mac_isr_stop(void);
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/**
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* @brief bb_cpu_mac_isr_enable() - init enable isr.
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*
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* @param none
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*
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* @return none
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*/
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void bb_cpu_mac_isr_enable();
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/**
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* @brief bb_cpu_mac_set_sw_irq_to_maincpu() - set sw irq to maincpu.
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*
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* @param id - irq id.
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*
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* @return none
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*/
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void bb_cpu_mac_set_sw_irq_to_maincpu(uint8_t id);
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/**
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* @brief bb_cpu_mac_set_share_irq_to_maincpu() - set share irq to maincpu.
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*
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* @param id - irq id.
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*
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* @return none
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*/
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void bb_cpu_mac_set_share_irq_to_maincpu(uint8_t id);
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#ifdef __cplusplus
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}
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#endif
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#endif // _BB_CPU_MAC_ISR_H_
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