377 lines
11 KiB
C
377 lines
11 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "chip_reg_base.h"
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#include "hw_reg_api.h"
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#include "iot_errno_api.h"
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#include "phy_pm.h"
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#include "phy_bb.h"
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#include "granite_reg.h"
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#include "iot_io.h"
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#include "phy_reg.h"
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#include "iot_config.h"
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#include "phy_dfe_reg.h"
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#include "phy_ana.h"
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#include "hw_phy_api.h"
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#include "ahb.h"
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#include "phy_tx_reg.h"
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/**
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* don't case for now, when need do Low-power,
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* need analog co-workers check it.
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**/
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void phy_pm_bias_sel_set(phy_pm_bias_sel_id sel_ic)
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{
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(void)sel_ic;
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}
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void phy_pm_bias_adj_set( \
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phy_pm_bias_adj_id adj_id, \
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phy_pm_bias_adj_current_id current_id)
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{
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#if HW_PLATFORM == HW_PLATFORM_SILICON
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/* bias current */
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if(adj_id == PHY_PM_BIAS_ADJ_IR)
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{
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switch(current_id)
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{
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case PHY_PM_BIAS_ADJ_31P25UA:
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/* bit0 */
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phy_ana_bias_ir0_cfg(0);
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/* bit1 */
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phy_ana_bias_ir1_cfg(0);
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break;
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case PHY_PM_BIAS_ADJ_25UA:
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/* bit0 */
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phy_ana_bias_ir0_cfg(BIAS_ADJ_IR25U_BIT0_MASK);
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/* bit1 */
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phy_ana_bias_ir1_cfg(0);
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break;
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case PHY_PM_BIAS_ADJ_18P75UA:
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/* bit0 */
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phy_ana_bias_ir0_cfg(BIAS_ADJ_IR25U_BIT0_MASK);
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/* bit1 */
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phy_ana_bias_ir1_cfg(BIAS_ADJ_IR25U_BIT1_MASK);
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break;
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default:
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break;
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}
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}
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else if(adj_id == PHY_PM_BIAS_ADJ_IC)
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{
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switch(current_id)
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{
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case PHY_PM_BIAS_ADJ_31P25UA:
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/* bit0 */
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phy_ana_bias_ic0_cfg(0);
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/* bit1 */
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phy_ana_bias_ic1_cfg(0);
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break;
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case PHY_PM_BIAS_ADJ_25UA:
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/* bit0 */
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phy_ana_bias_ic0_cfg(BIAS_ADJ_IC25U_BIT0_MASK);
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/* bit1 */
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phy_ana_bias_ic1_cfg(0);
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break;
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case PHY_PM_BIAS_ADJ_18P75UA:
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/* bit0 */
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phy_ana_bias_ic0_cfg(BIAS_ADJ_IC25U_BIT0_MASK);
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/* bit1 */
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phy_ana_bias_ic1_cfg(BIAS_ADJ_IC25U_BIT1_MASK);
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break;
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default:
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break;
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}
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}
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#else
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(void)adj_id;
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(void)current_id;
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#endif
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}
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void phy_bias_init_lic_io()
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{
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}
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void phy_bias_txrx_set()
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{
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#if PHY_BIAS_ADJUST_AUTO_EN == 0
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/* config bias sel to 25uA*/
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phy_pm_bias_sel_set(PHY_PM_BIAS_SEL_25UA);
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/* config bias adj to 18.75uA */
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phy_pm_bias_adj_set(PHY_PM_BIAS_ADJ_IR, PHY_PM_BIAS_ADJ_18P75UA);
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phy_pm_bias_adj_set(PHY_PM_BIAS_ADJ_IC, PHY_PM_BIAS_ADJ_18P75UA);
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#else
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/* config bias sel to 50uA*/
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phy_pm_bias_sel_set(PHY_PM_BIAS_SEL_50UA);
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/* config bias adj to 25uA */
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phy_pm_bias_adj_set(PHY_PM_BIAS_ADJ_IR, PHY_PM_BIAS_ADJ_25UA);
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phy_pm_bias_adj_set(PHY_PM_BIAS_ADJ_IC, PHY_PM_BIAS_ADJ_25UA);
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#endif
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}
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void phy_bias_rx_set()
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{
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/* config bias sel to 25uA*/
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phy_pm_bias_sel_set(PHY_PM_BIAS_SEL_25UA);
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/* config bias adj to 18.75uA */
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phy_pm_bias_adj_set(PHY_PM_BIAS_ADJ_IR, PHY_PM_BIAS_ADJ_18P75UA);
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phy_pm_bias_adj_set(PHY_PM_BIAS_ADJ_IC, PHY_PM_BIAS_ADJ_18P75UA);
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}
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uint32_t phy_pm_pwr_update(phy_pm_pwr_sts_id id)
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{
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uint32_t ret = ERR_FAIL;
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switch(id)
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{
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case PHY_PM_PWR_STS_TX:
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break;
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case PHY_PM_PWR_STS_RX:
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if(g_phy_ctxt.indep.pm_sts != PHY_PM_PWR_STS_RX) {
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phy_bias_rx_set();
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/* update glb pwr status */
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g_phy_ctxt.indep.pm_sts = PHY_PM_PWR_STS_RX;
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}
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ret = ERR_OK;
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break;
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case PHY_PM_PWR_STS_TXRX:
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if(g_phy_ctxt.indep.pm_sts != PHY_PM_PWR_STS_TXRX) {
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phy_bias_txrx_set();
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/* update glb pwr status */
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g_phy_ctxt.indep.pm_sts = PHY_PM_PWR_STS_TXRX;
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}
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ret = ERR_OK;
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break;
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default:
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break;
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}
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return ret;
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}
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void phy_pm_clk_auto_gate_en(bool_t en)
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{
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#if HW_PLATFORM == HW_PLATFORM_SILICON
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uint32_t tmp = 0;
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/* enable clk auto gate */
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tmp = PHY_READ_REG(CFG_BB_CLOCK_CTRL_ADDR);
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if(en) {
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//REG_FIELD_SET(SW_CLK_EN_FC_PARSE, tmp, 0);
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REG_FIELD_SET(SW_CLK_EN_DFE_RX, tmp, 0);
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REG_FIELD_SET(SW_CLK_EN_DFE_TX, tmp, 0);
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REG_FIELD_SET(SW_MEM_FORCE_ON, tmp, 0);
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REG_FIELD_SET(SW_CLK_EN_TD_TX, tmp, 0);
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REG_FIELD_SET(SW_CLK_EN_FFT, tmp, 0);
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REG_FIELD_SET(SW_CLK_EN_TX_FEC, tmp, 0);
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REG_FIELD_SET(SW_CLK_EN_TURBO_ENC, tmp, 0);
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} else {
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//REG_FIELD_SET(SW_CLK_EN_FC_PARSE, tmp, 1);
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REG_FIELD_SET(SW_CLK_EN_DFE_RX, tmp, 1);
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REG_FIELD_SET(SW_CLK_EN_DFE_TX, tmp, 1);
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REG_FIELD_SET(SW_MEM_FORCE_ON, tmp, 1);
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REG_FIELD_SET(SW_CLK_EN_TD_TX, tmp, 1);
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REG_FIELD_SET(SW_CLK_EN_FFT, tmp, 1);
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REG_FIELD_SET(SW_CLK_EN_TX_FEC, tmp, 1);
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REG_FIELD_SET(SW_CLK_EN_TURBO_ENC, tmp, 1);
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}
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PHY_WRITE_REG(CFG_BB_CLOCK_CTRL_ADDR, tmp);
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#else
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(void)en;
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#endif
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}
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void phy_pm_start()
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{
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//TODO:will be finished after ana low power
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#if 0
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#if HW_PLATFORM == HW_PLATFORM_SILICON
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uint32_t tmp = 0;
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uint8_t reg_id = 0;
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uint8_t rodata = 0;
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uint32_t rdata = 0;
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/* rx start */
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tmp = PHY_DFE_READ_REG(CFG_BB_ANA_RX_START_EXT_CFG_ADDR);
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REG_FIELD_SET(SW_RX_START_EXT_CFG_DATA,tmp,0xFFFFFFFF);
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PHY_DFE_WRITE_REG(CFG_BB_ANA_RX_START_EXT_CFG_ADDR, tmp);
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/* rx end */
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tmp = PHY_DFE_READ_REG(CFG_BB_ANA_RX_END_EXT_CFG_ADDR);
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REG_FIELD_SET(SW_RX_END_EXT_CFG_DATA,tmp,0);
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PHY_DFE_WRITE_REG(CFG_BB_ANA_RX_END_EXT_CFG_ADDR, tmp);
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/* read bit30~0 */
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reg_id = CFG_ANA_BIAS_REG_2_ADDR;
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phy_ana_i2c_read(reg_id, &rdata, &rodata);
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/* tx start */
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tmp = PHY_DFE_READ_REG(CFG_BB_ANA_TX_START_EXT_CFG_ADDR);
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REG_FIELD_SET(SW_TX_START_EXT_CFG_DATA,tmp,(1 << 31) | rdata);
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PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_START_EXT_CFG_ADDR, tmp);
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/* tx end */
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tmp = PHY_DFE_READ_REG(CFG_BB_ANA_TX_END_EXT_CFG_ADDR);
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REG_FIELD_SET(SW_TX_END_EXT_CFG_DATA,tmp,~(1 << 31) & rdata);
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PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_END_EXT_CFG_ADDR, tmp);
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/* EXT ADDR */
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tmp = PHY_DFE_READ_REG(CFG_BB_ANA_EXT_ADDR_CFG_ADDR);
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REG_FIELD_SET(SW_TX_START_EXT_CFG_ADDR, tmp, 9);
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REG_FIELD_SET(SW_TX_END_EXT_CFG_ADDR, tmp, 9);
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REG_FIELD_SET(SW_RX_START_EXT_CFG_ADDR, tmp, 8);
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REG_FIELD_SET(SW_RX_END_EXT_CFG_ADDR, tmp, 8);
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PHY_DFE_WRITE_REG(CFG_BB_ANA_EXT_ADDR_CFG_ADDR, tmp);
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/* init glb sts */
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g_phy_ctxt.indep.pm_sts = PHY_PM_PWR_STS_TXRX;
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/* turn down tx bias */
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phy_pm_pwr_update(PHY_PM_PWR_STS_RX);
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/* enable clk auto gate */
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phy_pm_clk_auto_gate_en(true);
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#endif
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#endif
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}
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void phy_idle_set()
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{
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#if HW_PLATFORM != HW_PLATFORM_SIMU && \
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IOT_ENERGE_METER_ENABLE != 1
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uint32_t tmp;
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/* disable HW control analog */
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PHY_DFE_WRITE_REG(CFG_BB_ANA_RX_START_CFG_ADDR, 0);
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PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_START_CFG_ADDR, 0);
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/* disable TX/RX of granite */
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phy_ana_tx_en(false);
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phy_ana_rx_en(false);
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phy_ana_enlic_en(false);
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phy_txrx_ovr_set(true,0);
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(void)tmp;
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#if 0
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/* if phy keep in reset state,
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* the sadc would be not working,
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* which result in problem of detecting
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* power charging of super capacity.
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* disable it currently
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*/
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/* warm reset PHY, delete clk */
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tmp = AHB_RF_READ_REG(CFG_AHB_REG0_ADDR);
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REG_FIELD_SET(PHY_SOFT_RST, tmp, 1);
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AHB_RF_WRITE_REG(CFG_AHB_REG0_ADDR, tmp);
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#endif
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#endif
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}
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void phy_idle_clr()
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{
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#if HW_PLATFORM != HW_PLATFORM_SIMU && \
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IOT_ENERGE_METER_ENABLE != 1
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/* enable RX disable TX */
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phy_ana_rx_en(true);
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phy_ana_tx_en(false);
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phy_ana_top_enlic_rx_set(true);
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phy_ana_top_enlic_tx_set(false);
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#if (HW_PLATFORM == HW_PLATFORM_FPGA)
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uint32_t wdata = 0;
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/* Enable sw control analog */
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wdata = 1 << TOP_EN_RX_OFFSET | \
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0 << TOP_EN_TX_OFFSET | \
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1 << TOP_ENLIC_OFFSET | \
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1 << TOP_EN_ADC_OFFSET | \
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0 << TOP_EN_DAC_OFFSET ;
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PHY_DFE_WRITE_REG(CFG_BB_ANA_RX_START_CFG_ADDR, wdata);
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wdata = 0 << TOP_EN_RX_OFFSET | \
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1 << TOP_EN_TX_OFFSET | \
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2 << TOP_ENLIC_OFFSET | \
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0 << TOP_EN_ADC_OFFSET | \
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1 << TOP_EN_DAC_OFFSET ;
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PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_START_CFG_ADDR, wdata);
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#else
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PHY_DFE_WRITE_REG(CFG_BB_ANA_RX_START_CFG_ADDR, 0x78);
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PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_START_CFG_ADDR, 0x7);
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#endif
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/* warm reset PHY, delete clk */
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ahb_phy_reset();
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phy_txrx_ovr_set(false,0);
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#endif
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#if IOT_DTEST_ONLY_SUPPORT == 0
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/* clear flag */
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g_phy_cpu_share_ctxt.pm_status.fc_ok_found = 0;
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#endif
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}
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uint32_t phy_force_ana_td_power(uint32_t value)
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{
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#if HW_PLATFORM != HW_PLATFORM_SIMU
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uint32_t tmp = PHY_TX_READ_REG(CFG_BB_TX_VECTOR_FORCE_1_ADDR);
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REG_FIELD_SET(SW_FORCE_TX_POWER_TD_EN, tmp, value);
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REG_FIELD_SET(SW_FORCE_TX_POWER_ANA_EN, tmp, value);
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REG_FIELD_SET(SW_FORCE_TX_POWER_FD_FRAC_EN, tmp, value);
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REG_FIELD_SET(SW_FORCE_TX_POWER_FD_INT_EN, tmp, value);
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PHY_TX_WRITE_REG(CFG_BB_TX_VECTOR_FORCE_1_ADDR, tmp);
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#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t phy_set_tx_pwr_td(uint32_t value)
|
||
|
|
{
|
||
|
|
#if HW_PLATFORM != HW_PLATFORM_SIMU
|
||
|
|
uint32_t tmp = PHY_TX_READ_REG(CFG_BB_TX_VECTOR_FORCE_1_ADDR);
|
||
|
|
REG_FIELD_SET(SW_FORCE_TX_POWER_TD, tmp, value);
|
||
|
|
PHY_TX_WRITE_REG(CFG_BB_TX_VECTOR_FORCE_1_ADDR, tmp);
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t phy_set_tx_pwr_ana(uint32_t value)
|
||
|
|
{
|
||
|
|
#if HW_PLATFORM != HW_PLATFORM_SIMU
|
||
|
|
uint32_t tmp = PHY_TX_READ_REG(CFG_BB_TX_VECTOR_FORCE_1_ADDR);
|
||
|
|
REG_FIELD_SET(SW_FORCE_TX_POWER_ANA, tmp, value);
|
||
|
|
PHY_TX_WRITE_REG(CFG_BB_TX_VECTOR_FORCE_1_ADDR, tmp);
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t phy_set_tx_pwr_fd_frac(uint32_t value)
|
||
|
|
{
|
||
|
|
#if HW_PLATFORM != HW_PLATFORM_SIMU
|
||
|
|
uint32_t tmp = PHY_TX_READ_REG(CFG_BB_TX_VECTOR_FORCE_1_ADDR);
|
||
|
|
REG_FIELD_SET(SW_FORCE_TX_POWER_FD_FRAC, tmp, value);
|
||
|
|
PHY_TX_WRITE_REG(CFG_BB_TX_VECTOR_FORCE_1_ADDR, tmp);
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t phy_set_tx_pwr_fd_int(uint32_t value)
|
||
|
|
{
|
||
|
|
#if HW_PLATFORM != HW_PLATFORM_SIMU
|
||
|
|
uint32_t tmp = PHY_TX_READ_REG(CFG_BB_TX_VECTOR_FORCE_1_ADDR);
|
||
|
|
REG_FIELD_SET(SW_FORCE_TX_POWER_FD_INT, tmp, value);
|
||
|
|
PHY_TX_WRITE_REG(CFG_BB_TX_VECTOR_FORCE_1_ADDR, tmp);
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|