kunlun/inc/hw/reg/riscv2/15/spinlock_top.h

//-----------------------------------
#define CFG_SPINLOCK_EN_ADDR 0x0
#define SPINLOCK_MAGIC_NUM_OFFSET 0
#define SPINLOCK_MAGIC_NUM_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK0_ADDR 0x100
#define SPINLOCK_LOCK0_OFFSET 0
#define SPINLOCK_LOCK0_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK1_ADDR 0x104
#define SPINLOCK_LOCK1_OFFSET 0
#define SPINLOCK_LOCK1_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK2_ADDR 0x108
#define SPINLOCK_LOCK2_OFFSET 0
#define SPINLOCK_LOCK2_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK3_ADDR 0x10C
#define SPINLOCK_LOCK3_OFFSET 0
#define SPINLOCK_LOCK3_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK4_ADDR 0x110
#define SPINLOCK_LOCK4_OFFSET 0
#define SPINLOCK_LOCK4_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK5_ADDR 0x114
#define SPINLOCK_LOCK5_OFFSET 0
#define SPINLOCK_LOCK5_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK6_ADDR 0x118
#define SPINLOCK_LOCK6_OFFSET 0
#define SPINLOCK_LOCK6_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK7_ADDR 0x11C
#define SPINLOCK_LOCK7_OFFSET 0
#define SPINLOCK_LOCK7_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK8_ADDR 0x120
#define SPINLOCK_LOCK8_OFFSET 0
#define SPINLOCK_LOCK8_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK9_ADDR 0x124
#define SPINLOCK_LOCK9_OFFSET 0
#define SPINLOCK_LOCK9_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK10_ADDR 0x128
#define SPINLOCK_LOCK10_OFFSET 0
#define SPINLOCK_LOCK10_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK11_ADDR 0x12C
#define SPINLOCK_LOCK11_OFFSET 0
#define SPINLOCK_LOCK11_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK12_ADDR 0x130
#define SPINLOCK_LOCK12_OFFSET 0
#define SPINLOCK_LOCK12_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK13_ADDR 0x134
#define SPINLOCK_LOCK13_OFFSET 0
#define SPINLOCK_LOCK13_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK14_ADDR 0x138
#define SPINLOCK_LOCK14_OFFSET 0
#define SPINLOCK_LOCK14_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK15_ADDR 0x13C
#define SPINLOCK_LOCK15_OFFSET 0
#define SPINLOCK_LOCK15_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK0_CLR_ADDR 0x200
#define SPINLOCK0_LOCK_CLR_OFFSET 0
#define SPINLOCK0_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK1_CLR_ADDR 0x204
#define SPINLOCK1_LOCK_CLR_OFFSET 0
#define SPINLOCK1_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK2_CLR_ADDR 0x208
#define SPINLOCK2_LOCK_CLR_OFFSET 0
#define SPINLOCK2_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK3_CLR_ADDR 0x20C
#define SPINLOCK3_LOCK_CLR_OFFSET 0
#define SPINLOCK3_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK4_CLR_ADDR 0x210
#define SPINLOCK4_LOCK_CLR_OFFSET 0
#define SPINLOCK4_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK5_CLR_ADDR 0x214
#define SPINLOCK5_LOCK_CLR_OFFSET 0
#define SPINLOCK5_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK6_CLR_ADDR 0x218
#define SPINLOCK6_LOCK_CLR_OFFSET 0
#define SPINLOCK6_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK7_CLR_ADDR 0x21C
#define SPINLOCK7_LOCK_CLR_OFFSET 0
#define SPINLOCK7_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK8_CLR_ADDR 0x220
#define SPINLOCK8_LOCK_CLR_OFFSET 0
#define SPINLOCK8_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK9_CLR_ADDR 0x224
#define SPINLOCK9_LOCK_CLR_OFFSET 0
#define SPINLOCK9_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK10_CLR_ADDR 0x228
#define SPINLOCK10_LOCK_CLR_OFFSET 0
#define SPINLOCK10_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK11_CLR_ADDR 0x22C
#define SPINLOCK11_LOCK_CLR_OFFSET 0
#define SPINLOCK11_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK12_CLR_ADDR 0x230
#define SPINLOCK12_LOCK_CLR_OFFSET 0
#define SPINLOCK12_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK13_CLR_ADDR 0x234
#define SPINLOCK13_LOCK_CLR_OFFSET 0
#define SPINLOCK13_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK14_CLR_ADDR 0x238
#define SPINLOCK14_LOCK_CLR_OFFSET 0
#define SPINLOCK14_LOCK_CLR_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SPINLOCK15_CLR_ADDR 0x23C
#define SPINLOCK15_LOCK_CLR_OFFSET 0
#define SPINLOCK15_LOCK_CLR_MASK 0x0000FFFF

//HW module read/write macro
#define SPINLOCK_TOP_READ_REG(addr) SOC_READ_REG(SPINLOCK_TOP_BASEADDR + addr)
#define SPINLOCK_TOP_WRITE_REG(addr,value) SOC_WRITE_REG(SPINLOCK_TOP_BASEADDR + addr,value)