diff --git a/.gitignore b/.gitignore
index 7304cf9..09f4720 100644
--- a/.gitignore
+++ b/.gitignore
@@ -2,7 +2,7 @@
 .output/
 bin/
 lib/
-tools/
+# tools/
 # mfgtool/
 .vscode/
 make_flags.txt
diff --git a/app/smart_grid/protocol/tools/proto_crc16.c b/app/smart_grid/protocol/tools/proto_crc16.c
new file mode 100755
index 0000000..7f0632b
--- /dev/null
+++ b/app/smart_grid/protocol/tools/proto_crc16.c
@@ -0,0 +1,48 @@
+/****************************************************************************
+
+Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
+
+This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
+be copied by any method or incorporated into another program without
+the express written consent of Aerospace C.Power. This Information or any portion
+thereof remains the property of Aerospace C.Power. The Information contained herein
+is believed to be accurate and Aerospace C.Power assumes no responsibility or
+liability for its use in any way and conveys no license or title under
+any patent or copyright and makes no representation or warranty that this
+Information is free from patent or copyright infringement.
+
+****************************************************************************/
+
+/* common includes */
+#include "iot_config_api.h"
+#include "iot_sg_fr.h"
+#include "iot_errno_api.h"
+#include "iot_crc_api.h"
+
+/* protocol includes */
+#include "proto_crc16.h"
+
+#define PPPGOODFCS16 0xf0b8 /* Good final FCS value */
+
+uint16_t proto_fcs16_check_sum(uint8_t *data, uint16_t length)
+{
+    return (iot_getcrc16_update(0xffff, data, length, 0));
+}
+
+uint16_t proto_fcs16_get_check_sum(uint8_t *data, uint16_t length)
+{
+    uint16_t fcs;
+    fcs = proto_fcs16_check_sum(data, length);
+    fcs ^= 0xffff;
+    return (fcs);
+}
+
+uint32_t proto_fcs16_check(uint8_t* data, uint16_t len)
+{
+    if (PPPGOODFCS16 == proto_fcs16_check_sum(data, len)) {
+        /* crc16 check success */
+        return ERR_OK;
+    }
+    /* crc16 check fail */
+    return ERR_FAIL;
+}
diff --git a/tools/add_cpp_def.sh b/tools/add_cpp_def.sh
new file mode 100755
index 0000000..b452f9d
--- /dev/null
+++ b/tools/add_cpp_def.sh
@@ -0,0 +1,46 @@
+#!/bin/sh
+echo "add _cplusplus tools"
+
+_cpp_head="\n#ifdef __cplusplus\nextern \"C\" {\n#endif"
+_cpp_tail="\n#ifdef __cplusplus\n}\n#endif\n"
+
+FILES=`find ./ -name "*.h" | grep -v "dtest" | grep -v "rom" | \
+    grep -v "inc/hw/reg/" | grep -v "mfgtool" | grep -v "dbglogparser_tool" | \
+    grep -v "import" | grep -v "deprecated_definitions.h" | 
+    grep -v "iot_config.h" | grep -v "encoding.h"`
+for file in ${FILES}
+do
+    file_name=${file##*/}
+
+    # if define _cplusplus
+    is_cpp=`grep "_cplusplus" $file -r`
+    if [ "$is_cpp" != "" ]; then
+        echo "[INFO]"$file" is defined by _cplusplus"
+        continue
+    fi
+
+    # get cpp header insert line number
+    head_line=`grep -n "#include" ./$file | tail -1 | cut -d ":" -f 1`
+    if [ "$head_line" == "" ]; then
+        head_line=`grep -n "#ifndef\ .*_H" ./$file | tail -1 | cut -d ":" -f 1`
+        if [ "$head_line" == "" ]; then
+            echo "[ERROR]"$file" is unexpected head format"
+            continue
+        fi
+        head_line=`expr $((head_line)) + 1`
+    fi
+    # insert _cplusplus head
+    sed -i "${head_line}a\\$_cpp_head" ./$file
+
+    # get cpp tail insert line number
+    tail_line=`grep -n "#endif" ./$file | tail -1 | cut -d ":" -f 1`
+    tail_line=`expr $((tail_line)) - 1`
+    if [ "$tail_line" == "" ]; then
+        echo "[ERROR]"$file" is unexpected tail format"
+    fi
+    echo "file: "$file",head: "$head_line", tail: "$tail_line
+    # insert _cplusplus tail
+    sed -i "${tail_line}a\\$_cpp_tail" ./$file
+    #echo $file
+done
+
diff --git a/tools/bee_gdbinit b/tools/bee_gdbinit
new file mode 100644
index 0000000..818b75d
--- /dev/null
+++ b/tools/bee_gdbinit
@@ -0,0 +1,776 @@
+# These are some useful functions to add to your ~/.xt-gdbinit file
+# Standard gdb debug settings
+
+set history filename ~/.gdb_history
+set history save on
+set print pretty on
+set print object on
+set print vtbl on
+set pagination off
+set output-radix 16
+
+set $new=1
+
+define fpga_ver
+x 0xa6048
+end
+
+define dmem_usage
+end
+
+define ana_read_gain
+set *0x51c00180=1
+x/w 0x51c0017c
+set *0x51c00180=25
+x/w 0x51c0017c
+set *0x51c00180=41
+x/w 0x51c0017c
+end
+
+define ana_read
+set *0x51c00180=$arg0*4+1
+x/w 0x51c0017c
+x/b 0x51c00181
+end
+
+define ana_write
+set $addr = $arg0
+set $value = $arg1
+set $mask = $arg2
+set *0x51c00178=$mask
+set *0x51c00174=$value
+set *0x51c00180=$addr*4+3
+end
+
+define dump_all
+set $phy_reg=0x51800000
+set $phy_tx_reg=0x51900000
+set $phy_rxtd_reg=0x51a00000
+set $phy_rxfd_reg=0x51b00000
+set $phy_dfe_reg=0x51c00000
+set $mac_sys_reg=0x51000000
+set $rgf_rx_reg=0x51000c00
+set $ahb_reg=0x50000000
+set $apb_reg=0x44000000
+set $clk_reg=0x44009000
+set $start=0
+set $size=0x700/4
+set $end=$size
+set logging file phy_reg_dump.txt
+set logging on
+while $start < $end
+    x $phy_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file phy_tx_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $phy_tx_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file phy_rxtd_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $phy_rxtd_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file phy_rx_fd_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $phy_rxfd_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file phy_dfe_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $phy_dfe_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file mac_sys_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $mac_sys_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file rgf_rx_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $rgf_rx_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file ahb_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $ahb_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file apb_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $apb_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file clk_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $clk_reg+$start*4
+    set $start++
+end
+set logging off
+
+# reset fpga
+define resetfpga
+set *0x00100000=0x6f
+set *0x50000004=0xffffffff
+end
+
+# Run to appstart and load app
+define loadfw
+monitor soft_reset_halt
+disable_watchdog
+load
+set_cpu_freq_150
+set $sp = &__StackTop
+#set $pc = __Vectors[1]
+end
+
+#dump uart register
+define dump_uart
+p *(struct pl011_regs*)0x44001000
+p *(struct pl011_regs*)0x44005000
+end
+
+define uart_info
+p g_uart_info
+end
+
+#dump intc register
+define dump_intc
+p *(struct intc_regs*)0x44004000
+end
+
+#dump apb register
+define dump_apb
+p *(struct apb_regs*)0x44000000
+end
+
+#dump gptimer register
+define dump_gptmr
+p *(struct gpmtr_regs*)0x44003000
+end
+
+define cache_disable
+set *0x02000028 &= ~(0x1e0000)
+set *0x0200002c |= (0x1e0000)
+end
+
+define map_flash_core
+set *0x4400703c |= 0x30
+set *0x44007098 |= 0x30
+set *0x44007038 |= 0x30
+set *0x44007064 |= 0x30
+set *0x44007068 |= 0x30
+set *0x44007040 |= 0x30
+
+set *0x4400001c |= 0x4
+
+set *0x44020010 |= 0x1000
+set *0x44020014 |= 0x1000
+set *0x44020018 |= 0x1000
+set *0x4402001c |= 0x1000
+end
+
+define map_flash_gpio_ver14
+# config pin 23-28 select FUNCTION0
+set *0x44007080=0
+set *0x44007084=0
+set *0x44007088=0
+set *0x4400708c=0
+set *0x44007090=0
+set *0x44007094=0
+# enable gpio matrix
+set *0x4400001c=0x4
+# config gpio matrix in
+# SFC INID 4-7 => GPIO 25-28
+set *0x44020010=25
+set *0x44020014=26
+set *0x44020018=27
+set *0x4402001c=28
+#config gpio matrix out
+# SFC OUTID 6-11 => GPIO 25-28
+set *0x4402045c=0x6
+set *0x44020460=0x7
+set *0x44020464=0x8
+set *0x44020468=0x9
+set *0x4402046c=10
+set *0x44020470=11
+end
+
+define map_uart2_gpio_mtx
+set *0x44007040=0
+set *0x44007044=0
+set *0x4400001c=0x4
+set *0x44020024=0x1000
+set *0x4402002c=0x8
+set *0x440200f8=15
+end
+define map_uart2_gpio_ver14
+set *0x44007040=0
+set *0x44007044=0
+set *0x4400001c |= 0x4
+set *0x44020024 |= 0x1000
+set *0x4402002c=0x8
+set *0x44020464=15
+end
+
+define map_psram_core_def
+set *0x4400001c |= 0x4
+set *0x44020000 |= 0x1000
+set *0x44020004 |= 0x1000
+set *0x44020008 |= 0x1000
+set *0x4402000c |= 0x1000
+end
+
+define set_cache_buffer_mode
+set *0x5000000c=0x10000
+set *0x50000008=0x00090010
+set *0x50000004=0xe
+end
+
+define cache_qspi_enable
+set *0x50000004=0x2001A
+set *0x50000008=0x90004
+# modify
+set *0x52000188=0x03057a75
+set *0x5200018c=0x100
+set *0x52000190=0x08180000
+# dual
+#set *0x52000188=0x3b057a75
+#set *0x5200018c=0x102
+#set *0x52000190=0x08180008
+#quad
+#set *0x52000188=0xeb057a75
+#set *0x5200018c=0x115
+#set *0x52000190=0x08060204
+
+set *0x52000194=0x100
+set *0x52000198=0x08000000
+set *0x5200019c=0x100
+set *0x520001a0=0x08000000
+set *0x520001a4=0x100
+set *0x520001a8=0x08000000
+#set *0x52000130=0x3
+# set cache quad
+#set *0x5200020c=0x102
+set *0x5200020c=0x1102
+set *0x52000208=0x35000000
+set *0x52000204=0x80000000
+
+set *0x50000004=0x20002
+set *0x50000008=0x9001C
+end
+
+define enable_emc
+set *0x02000020 |= 0x20
+set *0x02000024 |= 0x20
+set *0x02000024 &= ~(0x20)
+set *0x02000028 |= 0x200
+set *0x0200002c |= 0x200
+set *0x0200002c &= ~(0x200)
+end
+
+define init_flash
+set *0x61000140=0x2000
+#set *0x61000188=0x03057a75
+#set *0x6100018c=0x100
+#set *0x61000190=0x08180000
+set *0x52000188=0xeb057a75
+set *0x5200018c=0x115
+set *0x52000190=0x08060204
+
+set *0x61000194=0x100
+set *0x61000198=0x08000000
+set *0x6100019c=0x100
+set *0x610001a0=0x08000000
+set *0x610001a4=0x100
+set *0x610001a8=0x08000000
+end
+
+define psram_qpi_mode
+set *0x0150020c=0x1102
+set *0x01500210=0x32
+set *0x01500208=0x35000000
+set *0x01500204=0x80000000
+end
+
+define psram_qpi_mode_low
+set *0x0150020c=0x1102
+set *0x01500210=0x10
+set *0x01500208=0x35000000
+set *0x01500204=0x80000000
+end
+
+define psram_spi_mode
+set *0x6100020c=0x1000
+set *0x61000208=0xf5000000
+set *0x61000204=0x80000000
+set *0x6100020c=0x0000
+end
+
+define space_cache
+set $val = $arg0
+set *0x04C00044 = $val
+set *0x04C10044 = $val
+set *0x04C20044 = $val
+set *0x04C30044 = $val
+end
+
+define enable_cache
+set *0x02000028 =  0x1e0000
+set *0x0200002c &= ~(0x1e0000)
+end
+
+define cache_cfg_qpi_ver14
+enable_emc
+#init_flash
+psram_qpi_mode
+enable_cache
+space_cache 0x44
+end
+
+define cache_cfg_qpi_ver14_low
+enable_emc
+#init_flash
+psram_qpi_mode_low
+enable_cache
+space_cache 0x44
+end
+
+
+define cache_cfg_spi_ver14
+enable_emc
+psram_spi_mode
+init_flash
+enable_cache
+space_cache 0x44
+end
+
+define loadfirmware
+monitor soft_reset_halt
+cache_disable
+map_flash_gpio_mtx
+map_psram_core_def
+map_uart2_gpio_mtx
+cache_qspi_enable
+load
+end
+
+define disable_watchdog
+set *0x02000010 |= 0x100
+set *0x04900010 |= 0x2
+set *0x05c0f080 = 0x57444750
+set *0x05c0f008 = 0
+set *0x05c0f080 = 0
+set *0x0240e080 = 0x57444750
+set *0x0240e008 = 0
+set *0x04980080 = 0x57444750
+set *0x04980008 = 0
+set *0x0240e080 = 0
+set *0x04980080 = 0
+end
+
+define set_cpu_freq_150
+set *0x44009004=0x100
+set *0x44009000=0x1
+end
+
+define set_sfc_clk_75
+set *0x61000134=0x10
+end
+
+define set_smc_clk_75
+set *0x61000210=0x10
+end
+
+define load_ver14_qpi
+monitor soft_reset_halt
+disable_watchdog
+cache_disable
+if $new == 1
+    map_flash_core
+else
+    map_flash_gpio_ver14
+end
+map_psram_core_def
+#map_uart2_gpio_ver14
+cache_cfg_qpi_ver14
+load
+set_cpu_freq_150
+#set_sfc_clk_75
+#set_smc_clk_75
+while $a0 != 0x0
+    set $a0=0x0
+end
+end
+
+define load_ver14_spi
+monitor soft_reset_halt
+disable_watchdog
+cache_disable
+if $new == 1
+    map_flash_core
+else
+    map_flash_gpio_ver14
+end
+map_psram_core_def
+#map_uart2_gpio_ver14
+cache_cfg_spi_ver14
+load
+set $a0=0x0
+end
+
+define snapshot
+set *0x52000004=0x10101
+set *0x52000008=0x1e007
+end
+
+define map_jtag_gpio_mtx
+# config pin 00 - 04 select FUCNTION0
+set *0x44007024=0
+set *0x44007028=0
+set *0x4400702c=0
+set *0x44007030=0
+set *0x44007034=0
+# enable gpio matrix
+set *0x4400001c=0x4
+#in 44 - 47 => 00 01 03 04
+set *0x440200b0=00
+set *0x440200b4=01
+set *0x440200b8=03
+set *0x440200bc=04
+#out 2 => 66
+set *0x44020408=62
+end
+
+define map_jtag0_gpio
+#config pin 12-15 45 select FUNCTION0
+set *0x44007054 = 0
+set *0x44007058 = 0
+set *0x4400705c = 0
+set *0x44007060 = 0
+set *0x440070a0 = 0
+# enable gpio matrix
+set *0x4400001c=0x4
+#in 44 TMS 12
+set *0x440200b0=12
+#in 45 TCK 13
+set *0x440200b4=13
+#in 46 TDI 15
+set *0x440200b8=15
+#in 47 RST 45
+set *0x440200bc=45
+#out 14 => 62
+set *0x44020438=62
+end
+
+define print_dump_info
+    set trace-commands off
+    set $i = 0
+    while($i < 10)
+        set $dump = g_exception_dump.ra[$i]
+        if ($dump != 0x0)
+            p/a $dump
+        end
+        set $i = $i + 1
+    end
+    set trace-commands on
+end
+
+define map_dmc_psram
+    set *0x5522a03c = 0x15501
+end
+
+define map_emc_flash_kl2
+# 48 - 53
+set *0x440070c4 &= ~0x30
+set *0x440070c8 &= ~0x30
+set *0x440070cc &= ~0x30
+set *0x440070d0 &= ~0x30
+set *0x440070d4 &= ~0x30
+set *0x440070d8 &= ~0x30
+set *0x440070c4 |= 0x10
+set *0x440070c8 |= 0x10
+set *0x440070cc |= 0x10
+set *0x440070d0 |= 0x10
+set *0x440070d4 |= 0x10
+set *0x440070d8 |= 0x10
+set *0x440070dc |= 0x10
+
+set *0x4400001c |= 0x4
+
+set *0x44020010 |= 0x1000
+set *0x44020014 |= 0x1000
+set *0x44020018 |= 0x1000
+set *0x4402001c |= 0x1000
+end
+
+# reg_write reg lowest_bit bit_num value
+define reg_write
+    set $reg = $arg0
+    set $low = $arg1
+    set $cnt = $arg2
+    set $value = $arg3
+    set $tmp = *(uint32_t *)$reg
+    set $mask = 0
+    while($cnt > 0)
+        set $cnt--
+        set $mask = (($mask << 1) + 1)
+    end
+    set $mask = $mask << $low
+    set $tmp &= ~$mask
+    set $tmp |= (($value << $low) & $mask)
+    set *(uint32_t *)$reg = $tmp
+end
+
+
+define load_bee_psram
+#monitor soft_reset_halt
+cache_disable
+cache_cfg_qpi_ver14
+space_cache 0x1004
+load
+while $a0 != 0x0
+    set $a0=0x0
+end
+end
+
+define load_bee_psram_low
+#monitor soft_reset_halt
+cache_disable
+cache_cfg_qpi_ver14_low
+space_cache 0x1004
+load
+while $a0 != 0x0
+    set $a0=0x0
+end
+end
+
+define dvp_enable
+set *0x50000008 |= 0x800
+set *0x50000004 |= 0x800
+set *0x50000004 &= ~0x800
+end
+
+define dvp_ram_mode
+set *0x52300000 = 0x21f21
+set *0x52300054 = 0x3
+set *0x52300004 = 0x1cc
+set *0x52300008 = 0x1
+set *0x52300024 = 720
+set *0x52300028 = 1280
+set *0x52300060 = 0x1
+set *0x52300058 = 0x72105
+set *0x523000b4 = 0x72ff
+set *0x52300100 = 0x1
+end
+
+define dvp_ram_mode_no_force
+set *0x52300000 = 0x0
+set *0x52300054 = 0x3
+set *0x52300004 = 0x1cc
+set *0x52300008 = 0x1
+set *0x52300024 = 720
+set *0x52300028 = 1280
+set *0x52300060 = 0x1
+set *0x52300058 = 0x72105
+set *0x523000b4 = 0x72ff
+set *0x52300100 = 0x1
+set *0x52300000 = 0x01f01
+end
+
+define dvp_ram_mode_crop
+# dvp data to psram address
+set *0x52300018 = 0x00000
+set *0x5230010c = 0x100000
+set *0x52300000 = 0x0
+set *0x52300054 = 0x0
+set *0x52300004 = 0x11cc
+
+#set *0x52300008 = 0x1
+#set *0x5230000c = 0xff
+#set *0x52300010 = 0x02cf04ff
+set *0x52300008 = 0x1
+set *0x5230000c = 0x1
+set *0x52300010 = 0x02cf0400
+
+set *0x52300014 = 0x04000000
+set *0x52300024 = 720
+set *0x52300028 = 1280
+set *0x52300000 = 0x01f33
+end
+
+define dvp_ram_mode_no_crop
+# dvp data to psram address
+set *0x52300018 = 0x00000
+set *0x5230010c = 0x1000000
+set *0x52300000 = 0x0
+set *0x52300054 = 0x0
+set *0x52300004 = 0x11cc
+set *0x52300008 = 0x1
+set *0x5230000c = 0x1
+set *0x52300010 = 0x02cf0400
+set *0x52300014 = 0x05000000
+set *0x52300024 = 720
+set *0x52300028 = 1280
+set *0x52300000 = 0x01f31
+end
+
+define dvp_bina_mode
+set *0x52300000 = 0x021f21
+set *0x52300054 = 0x5
+set *0x52300004 = 0x1cc
+set *0x52300008 = 0x1
+#set *0x52300024 = 720
+#set *0x52300028 = 1280
+set *0x52300024 = 720
+set *0x52300028 = 1024
+set *0x52300060 = 0x1
+set *0x52300058 = 0x72105
+set *0x523000b4 = 0x72ff
+end
+
+define dvp_bina_mode_no_force
+set *0x52300000 = 0x0
+set *0x52300054 = 0x5
+set *0x52300004 = 0x1cc
+set *0x52300008 = 0x1
+set *0x52300024 = 720
+set *0x52300028 = 1280
+set *0x52300060 = 0x1
+set *0x52300058 = 0x72105
+set *0x523000b4 = 0x72ff
+set *0x52300000 = 0x001f21
+end
+
+define dvp_bina_mode_auto
+set *0x52300000 = 0x0
+set *0x52300054 = 0x7
+set *0x52300004 = 0x11cc
+set *0x52300008 = 0x1
+set *0x52300024 = 720
+set *0x52300028 = 1280
+set *0x52300060 = 0x1
+set *0x52300058 = 0x72105
+set *0x523000b4 = 0x72ff
+set *0x52300000 = 0x001f21
+end
+# crop 1024 * 720
+define dvp_bina_mode_crop
+set *0x52300000 = 0x0
+# dvp data to psram address
+set *0x52300018 = 0x10000
+set *0x52300054 = 0x7
+set *0x52300004 = 0x11cc
+set *0x52300008 = 0x1
+set *0x5230000c = 0xff
+#set *0x5230000c = 0x0
+set *0x52300010 = 0x02d004ff
+#set *0x52300010 = 0x02d00400
+set *0x52300024 = 720
+#set *0x52300028 = 1280
+set *0x52300028 = 1024
+set *0x52300060 = 0x1
+set *0x52300058 = 0x72105
+set *0x523000b4 = 0x72ff
+set *0x52300000 = 0x001f23
+end
+
+define fake_data
+set $addr = $arg0
+set $size = $arg1
+set $offset = $arg2
+set $i = 0
+while $size > 0
+    set *$addr =  $i
+    set $i = $i + 0x11111111 + $offset
+    if ($i == 0xffffffff)
+        set $i = 0x0
+    end
+    set $addr = $addr + 4
+    set $size = $size - 1
+end
+end
+
+define clear_cache
+set *0x04c00000 |= 0x4
+set *0x04c10000 |= 0x4
+set *0x04c20000 |= 0x4
+set *0x04c30000 |= 0x4
+end
+
+define cpu1_enable
+set $start_pc = $arg0
+set *0x02000124 = $start_pc
+set *0x02000028 |= 0x2
+set *0x0200002c |= 0x2
+set *0x0200002c &= ~0x2
+set *0x0200012c |= 0x4
+end
+
+define nfc_vm
+target remote localhost:3333
+set *0x02000104 |= 0x1b
+disable_watchdog
+end
+
+define vm
+target remote localhost:3333
+disable_watchdog
+end
+
+
+define bee_vm
+vm
+monitor reset halt
+kill
+shell sleep 0.001
+vm
+end
+
+define bee_target_remote
+
+target remote $arg0
+monitor reset halt
+kill
+shell sleep 0.001
+target remote $arg0
+disable_watchdog
+end
+
diff --git a/tools/bin_tool/bin2hex.c b/tools/bin_tool/bin2hex.c
new file mode 100644
index 0000000..5218043
--- /dev/null
+++ b/tools/bin_tool/bin2hex.c
@@ -0,0 +1,97 @@
+#include <stdio.h>
+#include <stdint.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+#include <malloc.h>
+#include <stdlib.h>
+
+void print_binary(FILE *fp, uint32_t n)
+{
+    uint8_t arr[32] = {0};
+    int len = 0;
+    for(len = 0; len < 32; len++){
+        arr[len] = (n&1)+'0';
+        n = n>>1;
+
+    }
+
+    len--;
+    while (len >= 0 ){
+        fprintf(fp,"%c", arr[len]);
+        len--;
+    }
+    fprintf(fp,"\n");
+}
+
+int main( int argc, char *argv[] )
+{
+    uint8_t buf[128];
+    FILE *fin = NULL, *fout = NULL;
+    int i = 0;
+    uint8_t val;
+    off_t filesize, offset;
+    size_t st = 0;
+    uint32_t tmp = 0;
+
+    if( ( fin = fopen( argv[1], "rb" ) ) == NULL ){
+        printf("fopen(%s,r) failed\n", argv[1] );
+        goto exit;
+    }
+
+    if( ( fout = fopen( argv[2], "w+" ) ) == NULL ){
+        printf("fopen(%s,w+) failed\n", argv[2] );
+        goto exit;
+    }
+
+    if( argc > 3){
+        filesize = atoi(argv[3]);
+    } else{
+        if( ( filesize = lseek( fileno( fin ), 0, SEEK_END ) ) < 0 ){
+            perror( "lseek" );
+            goto exit;
+        }
+    }
+
+    if( fseek( fin, 0, SEEK_SET ) < 0 ){
+         printf( "fseek(0,SEEK_SET) failed\n" );
+         goto exit;
+    }
+    memset(buf, 0x0,128);
+    for( offset = 0; offset < filesize; offset += 1 ){
+        st = fread( buf, 1, 4, fin );
+        if ( st == 0) {
+            break;
+        }
+        #if 0
+        for(i = 0; i < 4; i++){
+            val = buf[3-i];
+            printf("%02x\n", val);
+            printf("%02x\n", val);
+            fprintf(fout, "%02x\n", val);
+        }
+        #else
+        if ( st == 4) {
+            tmp = (uint32_t)(((uint32_t)buf[3] <<24)|((uint32_t)buf[2]<<16) |(uint32_t)(buf[1]<<8)|(uint32_t)buf[0]);
+        } else if (st == 3) {
+            tmp = (uint32_t)(((uint32_t)buf[2]<<16) |(uint32_t)(buf[1]<<8)|(uint32_t)buf[0]);
+        } else if (st == 2) {
+            tmp = (uint32_t)((uint32_t)(buf[1]<<8)|(uint32_t)buf[0]);
+        } else if (st == 1) {
+            tmp = (uint32_t)((uint32_t)buf[0]);
+        }
+        //printf("%02x %02x %02x %02x\n", buf[3], buf[2], buf[1], buf[0]);
+        //printf("%08x\n", tmp);
+        fprintf(fout, "%08x\n", tmp);
+        #endif
+    }
+
+exit:
+    if(fin){
+        fclose(fin);
+    }
+
+    if(fout){
+        fclose(fout);
+    }
+}
diff --git a/tools/bin_tool/bin2hex_frame.c b/tools/bin_tool/bin2hex_frame.c
new file mode 100644
index 0000000..75f7180
--- /dev/null
+++ b/tools/bin_tool/bin2hex_frame.c
@@ -0,0 +1,116 @@
+#include <stdio.h>
+#include <stdint.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+#include <malloc.h>
+#include <stdlib.h>
+
+#define DATA_NUM_PER_ROW    16
+
+void print_binary(FILE *fp, uint32_t n)
+{
+    uint8_t arr[32] = {0};
+    int len = 0;
+    for(len = 0; len < 32; len++){
+        arr[len] = (n&1)+'0';
+        n = n>>1;
+
+    }
+
+    len--;
+    while (len >= 0 ){
+        fprintf(fp,"%c", arr[len]);
+        len--;
+    }
+    fprintf(fp,"\n");
+}
+
+int main( int argc, char *argv[] )
+{
+    char buf[128];
+    FILE *fin = NULL, *fout = NULL;
+    int i = 0;
+    uint8_t val;
+    off_t filesize, offset;
+    uint32_t data_counter = 0;
+    uint8_t fill_zero_num = 0;
+
+    printf("argc:%d, ", argc);
+    for (uint8_t i = 0; i < argc; i++) {
+        printf("argv[%d]:%s, ", i, argv[i]);
+    }
+    printf("\n");
+
+    if( ( fin = fopen( argv[1], "rb+" ) ) == NULL ){
+        printf("fopen(%s,r) failed\n", argv[1] );
+        goto exit;
+    }
+
+    if( ( fout = fopen( argv[2], "w+" ) ) == NULL ){
+        printf("fopen(%s,w+) failed\n", argv[2] );
+        goto exit;
+    }
+
+    if( argc > 3){
+        filesize = atoi(argv[3]);
+    } else{
+        if( ( filesize = lseek( fileno( fin ), 0, SEEK_END ) ) < 0 ){
+            perror( "lseek" );
+            goto exit;
+        }
+    }
+
+    // //4-byte alignment, fill in zeros if not enough
+    // fill_zero_num = filesize % 4;
+    // if (fill_zero_num != 0) {
+    //     if (fseek(fin, 0, SEEK_END) < 0) {
+    //         printf( "fseek(0,SEEK_END) failed\n" );
+    //         goto exit;
+    //     }
+    //     char temp = 0;
+    //     if (fwrite(&temp, 1, fill_zero_num, fin) != fill_zero_num) {
+    //         printf("fwrite(0,%d) failed\n", fill_zero_num);
+    //         goto exit;
+    //     }
+    //     filesize++;
+    // }
+
+    if( fseek( fin, 0, SEEK_SET ) < 0 ){
+         printf( "fseek(0,SEEK_SET) failed\n" );
+         goto exit;
+    }
+    memset(buf, 0x0,128);
+    for( offset = 0; offset < filesize; offset += 1 ){
+        if( fread( buf, 1, 4, fin ) != (size_t) 4 ){
+            goto exit;
+        }
+        for(i = 0; i < 4; i++){
+            // val = buf[3-i];
+            val = buf[i];
+            printf("0x%02x", val);
+            fprintf(fout, "0x%02x", val);
+            data_counter++;
+            if (data_counter == filesize) {
+                break;
+            }
+            if (data_counter % DATA_NUM_PER_ROW != 0) {
+                printf(", ");
+                fprintf(fout, ", ");
+            } else {
+                printf(",\n");
+                fprintf(fout, ",\n");
+            }
+        }
+    }
+
+exit:
+    if(fin){
+        fclose(fin);
+    }
+
+    if(fout){
+        fclose(fout);
+    }
+    return 0;
+}
diff --git a/tools/bin_tool/hex2bin.c b/tools/bin_tool/hex2bin.c
new file mode 100644
index 0000000..619635f
--- /dev/null
+++ b/tools/bin_tool/hex2bin.c
@@ -0,0 +1,117 @@
+#include <stdio.h>
+#include <stdint.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+#include <malloc.h>
+#include <stdlib.h>
+#include <ctype.h>
+
+#define strtoul(cp, endp, base)    simple_strtoul(cp, endp, base)
+
+void print_binary(FILE *fp, uint32_t n)
+{
+    uint8_t arr[32] = {0};
+    int len = 0;
+    for(len = 0; len < 32; len++){
+        arr[len] = (n&1)+'0';
+        n = n>>1;
+
+    }
+
+    len--;
+    while (len >= 0 ){
+        fprintf(fp,"%c", arr[len]);
+        len--;
+    }
+    fprintf(fp,"\n");
+}
+
+unsigned long simple_strtoul(const char *cp, char **endp,
+                unsigned int base)
+{
+    unsigned long result = 0;
+    unsigned long value;
+
+    if (*cp == '0') {
+        cp++;
+        if ((*cp == 'x') && isxdigit(cp[1])) {
+            base = 16;
+            cp++;
+        }
+
+        if (!base)
+            base = 8;
+    }
+
+    if (!base)
+        base = 10;
+
+    while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
+        ? toupper(*cp) : *cp)-'A'+10) < base) {
+        result = result*base + value;
+        cp++;
+    }
+
+    if (endp)
+        *endp = (char *)cp;
+
+    return result;
+}
+
+int main( int argc, char *argv[] )
+{
+    char buf[128];
+    FILE *fin = NULL, *fout = NULL;
+    int i = 0;
+    uint8_t val;
+    off_t filesize, offset;
+    uint32_t tmp = 0;
+
+    if( ( fin = fopen( argv[1], "rb" ) ) == NULL ){
+        printf("fopen(%s,r) failed\n", argv[1] );
+        goto exit;
+    }
+
+    if( ( fout = fopen( argv[2], "w+" ) ) == NULL ){
+        printf("fopen(%s,w+) failed\n", argv[2] );
+        goto exit;
+    }
+
+    if( argc > 3){
+        filesize = atoi(argv[3]);
+    } else{
+        if( ( filesize = lseek( fileno( fin ), 0, SEEK_END ) ) < 0 ){
+            perror( "lseek" );
+            goto exit;
+        }
+    }
+
+    if( fseek( fin, 0, SEEK_SET ) < 0 ){
+         printf( "fseek(0,SEEK_SET) failed\n" );
+         goto exit;
+    }
+
+    while(1) {
+        memset(buf, 0x0, 128);
+        char *st = fgets(buf,128, fin);
+        char **endp = NULL;
+
+        if (st == NULL) {
+            break;
+        }
+        tmp = strtoul(buf, endp, 16);
+        //printf("%s:%08x\n", buf, tmp);
+        //fprintf(fout, "%08x\n", tmp);
+        print_binary(fout, tmp);
+    }
+
+exit:
+    if(fin){
+        fclose(fin);
+    }
+
+    if(fout){
+        fclose(fout);
+    }
+}
diff --git a/tools/dumpRTOS.cmd b/tools/dumpRTOS.cmd
new file mode 100755
index 0000000..57284f1
--- /dev/null
+++ b/tools/dumpRTOS.cmd
@@ -0,0 +1,479 @@
+#
+#Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
+#This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
+#be copied by any method or incorporated into another program without
+#the express written consent of Aerospace C.Power. This Information or any portion
+#thereof remains the property of Aerospace C.Power. The Information contained herein
+#is believed to be accurate and Aerospace C.Power assumes no responsibility or
+#liability for its use in any way and conveys no license or title under
+#any patent or copyright and makes no representation or warranty that this
+#Information is free from patent or copyright infringement.
+#
+#
+
+#
+#  Preface:  GDB Script To Parser GDB Core or CoreDump
+#            Display Tasks and Their Stacks
+#            By Zhihua  v1.0.0 
+#
+
+#  History: 
+#  2017-06-07  Init version. Add dump OS global statistics variable and task TCB/Stacks
+#  2017-06-08  Dump Heap Usage
+#
+
+# turn on logging
+set logging off
+shell rm -f ./rtosdump.txt
+set logging file rtosdump.txt  
+set logging on
+
+
+# 1: dump full 512 DWORD stack space. (note: TIME SRV is 1024 DWORDs)
+# 0: only dump stack from current top to base.
+set $stack_dumpfull = 0 
+
+
+# TCB_t->pxStack
+set $stack_end=0
+
+# TCB_t->pxStack+512
+set $stack_top=0
+
+# TCB-_t>pxTopOfStack
+set $stack_cur=0
+
+# Default HT task size. currently, HT.out use same stack size
+set $stack_size=512
+
+# S0 register, used into reverse call stack
+set $stack_s0=0
+
+# unused stack size 
+set $stack_unused=0
+
+# flag to indicate current analysis TCB is TMR SRV
+set $istimersrv=0
+
+#
+#
+#  Format Marker
+#
+#
+
+define Make_FMTMarker
+    echo \n 
+    echo ---------------------------------------------------------------------------------------------\n
+    echo \n
+end 
+
+define Dump_HeapInfo
+    echo start to dump heap usage\n
+    echo heap start at:\n
+    p (int)&ucHeap
+    echo heap stop at:\n
+    p (int)xStart.pxNextFreeBlock
+    echo heap size(K):\n
+    p/d sizeof(ucHeap)/1024
+    
+    
+    echo \n
+    set $FreeList_Cur = xStart
+    while ($FreeList_Cur.pxNextFreeBlock != 0)
+        p $FreeList_Cur
+        set $FreeList_Cur = *$FreeList_Cur.pxNextFreeBlock
+    end
+
+    echo \n
+    
+    echo Full Stack Usage:\n
+    echo total_mem:(K)\n
+    p/d  total_mem/1024
+    echo cvg_total_mem:(K)\n
+    p/d cvg_total_mem/1024
+    echo mac_total_mem: (K)\n
+    p/d  mac_total_mem/1024
+    echo misc_total_mem: (K)\n
+    p/d misc_total_mem/1024
+    
+    
+    echo RTOS core Usage:(K)\n
+    p/d (sizeof(ucHeap) - xFreeBytesRemaining - total_mem)/1024
+    
+    echo heap free (K):\n
+    p/d xFreeBytesRemaining/1024
+    echo heap lowest free(K):\n
+    p/d xMinimumEverFreeBytesRemaining/1024
+    
+    echo \n
+    echo Detail Moudle useage\n
+    set $mem_idx = 0
+    while ($mem_idx != 0xFF)
+        if mid_mem[$mem_idx] > 0
+            printf "mid_mem[%d]=0x%x\n",$mem_idx, mid_mem[$mem_idx]
+        end
+        set $mem_idx = $mem_idx+1
+    end    
+
+end
+
+
+
+
+#
+#
+# Local Function to trave stacks from up to down
+# 
+#
+define travel_stack
+    set $is_pxCurTCB = 0
+    set $ptr_nextstack=0
+    set $ptr_ra=0
+    
+    
+   
+    #judge wheter current running TCB
+    if $stack_s0 > 0
+      set $is_pxCurTCB = 1
+    end
+    
+    echo \n
+    
+    
+    if $is_pxCurTCB > 0
+        x $pc
+        x $ra
+        set $ptr_nextstack= $s0
+
+        while( $ptr_nextstack < $stack_top )
+            set $ptr_ra = *($ptr_nextstack-4)
+            set $ptr_nextstack = *($ptr_nextstack-8)
+            if $ptr_ra == $ptr_nextstack
+               echo -----------------Interrupt context swith\n
+            else
+               x $ptr_ra
+            end
+            
+            if $ptr_nextstack == 0xa5a5a5a5
+               set $ptr_nextstack  = $stack_top
+            end 
+        end
+    else
+        set $task_pc = *($stack_cur+124) 
+        x $task_pc
+        
+        set $task_ra = *$stack_cur
+        x $task_ra
+
+        set $ptr_nextstack= *($stack_cur+28)
+        while( $ptr_nextstack < $stack_top )
+            set $ptr_ra = *($ptr_nextstack-4)
+            set $ptr_nextstack = *($ptr_nextstack-8)
+            
+            if $ptr_ra == $ptr_nextstack
+               #echo -----------------Interrupt context swith\n
+            else
+               x $ptr_ra
+            end
+            
+            if $ptr_nextstack == 0xa5a5a5a5
+               set $ptr_nextstack  = $stack_top
+            end 
+        end
+     
+    end
+end
+
+
+#   
+#
+#  Dump Stack
+#
+#
+
+define dump_stack
+
+    
+    set $stact_printcur = 0
+
+    if (unsigned int)$stack_cur > (unsigned int)$stack_top
+     set $istimersrv = 1
+     set $stack_top = $stack_top + 512
+     #echo TMR SRV\n  
+    end
+
+    echo stack_end:\n
+    p (unsigned int)$stack_end
+    echo stack_cur:\n
+    p (unsigned int)$stack_cur
+    echo stack_top:\n
+    p (unsigned int)$stack_top
+    echo stack_s0:\n
+    p $stack_s0
+    echo \n
+ 
+    echo stack_unused:\n
+    p $stack_unused = (int)$stack_cur - (int)$stack_end
+    echo stack_used:\n
+    p $stack_used = (int )$stack_top - (int)$stack_cur
+    
+    if $stack_dumpfull > 0
+       if $istimersrv > 0
+         x/1024xw (unsigned int)$stack_end
+       else
+         x/512xw (unsigned int)$stack_end
+       end
+    else
+       set $stact_printcur =  $stack_cur
+       while($stack_used > 0)
+          x/4xw (unsigned int)$stact_printcur
+          set $stact_printcur = $stact_printcur + 16
+          set $stack_used = $stack_used -16
+       end
+    end
+end
+
+
+Make_FMTMarker
+Dump_HeapInfo
+Make_FMTMarker
+
+
+
+#
+#
+#  Dump Global Task Variable
+#
+#
+Make_FMTMarker
+echo p uxCurrentNumberOfTasks\n
+p uxCurrentNumberOfTasks
+echo p uxTaskNumber\n
+p uxTaskNumber
+echo p xTickCount\n
+p xTickCount
+echo p uxPendedTicks\n
+p uxPendedTicks
+echo p xSchedulerRunning\n
+p xSchedulerRunning
+echo p xNextTaskUnblockTime\n
+p xNextTaskUnblockTime
+echo p uxSchedulerSuspended\n
+p uxSchedulerSuspended
+
+
+
+#
+#
+#  Analysis pxCurrentTCB
+#
+#
+
+Make_FMTMarker
+#p *pxCurrentTCB
+p (*pxCurrentTCB)->pcTaskName
+p (*pxCurrentTCB)->pxStack
+p (*pxCurrentTCB)->pxTopOfStack
+set $stack_end= (*pxCurrentTCB)->pxStack
+set $stack_cur = $sp
+set $stack_top = $stack_end + $stack_size
+set $stack_s0 = $s0
+#dump_stack
+travel_stack
+Make_FMTMarker
+
+#
+#
+#  Analysis xSuspendedTaskList
+#
+#
+if xSuspendedTaskList.uxNumberOfItems >0
+   echo xSuspendedTaskList.uxNumberOfItems\n
+   p xSuspendedTaskList.uxNumberOfItems
+
+   set $list_end = xSuspendedTaskList->pxIndex
+   set $list_start = xSuspendedTaskList->xListEnd.pxNext
+   
+  
+   while ($list_start != $list_end)
+       Make_FMTMarker
+       #p $list_start
+
+       set $tcb = (char*)$list_start - 4
+       #p (TCB_t)*$tcb
+       p ((TCB_t)*$tcb)->pcTaskName
+       p ((TCB_t)*$tcb)->pxStack
+       p ((TCB_t)*$tcb)->pxTopOfStack
+
+       set $stack_end= ((TCB_t)*$tcb)->pxStack
+       set $stack_cur = (unsigned int)((TCB_t)*$tcb)->pxTopOfStack
+       set $stack_top = $stack_end+$stack_size
+       set $stack_s0 = 0
+       #dump_stack
+       travel_stack
+
+       set $list_start = $list_start.pxNext
+       Make_FMTMarker
+   end
+end
+
+#
+#
+#  Analysis pxReadyTasksLists
+#
+#
+
+set $readyTaskList_index = 0
+set $readyTaskList_Max = 7
+while ($readyTaskList_index < $readyTaskList_Max)
+       if pxReadyTasksLists[$readyTaskList_index].uxNumberOfItems >0
+          echo ready task array index:\n
+          p $readyTaskList_index
+          echo num\n
+          p pxReadyTasksLists[$readyTaskList_index].uxNumberOfItems
+          
+          set $list_end = pxReadyTasksLists[$readyTaskList_index]->pxIndex
+          set $list_start = pxReadyTasksLists[$readyTaskList_index]->xListEnd.pxNext
+
+          while ($list_start != $list_end)
+             Make_FMTMarker
+             set $tcb = (char*)$list_start - 4
+             #p (TCB_t)*$tcb
+             p ((TCB_t)*$tcb)->pcTaskName
+             p ((TCB_t)*$tcb)->pxStack
+             p ((TCB_t)*$tcb)->pxTopOfStack
+             
+             set $stack_end= ((TCB_t)*$tcb)->pxStack
+             set $stack_cur = (unsigned int)((TCB_t)*$tcb)->pxTopOfStack
+             set $stack_top = $stack_end+$stack_size
+             set $stack_s0 = 0
+             #dump_stack
+             travel_stack
+             set $list_start = $list_start.pxNext
+             Make_FMTMarker
+          end
+      
+       end
+       set $readyTaskList_index = $readyTaskList_index+1
+end
+
+
+if xDelayedTaskList1.uxNumberOfItems >0
+   Make_FMTMarker
+   echo xDelayedTaskList1.uxNumberOfItems\n
+   p xDelayedTaskList1.uxNumberOfItems
+
+   set $list_end = xDelayedTaskList1->pxIndex
+   set $list_start = xDelayedTaskList1->xListEnd.pxNext
+   
+  
+   while ($list_start != $list_end)
+       set $tcb = (char*)$list_start - 4
+       #p (TCB_t)*$tcb
+       p ((TCB_t)*$tcb)->pcTaskName
+       p ((TCB_t)*$tcb)->pxStack
+       p ((TCB_t)*$tcb)->pxTopOfStack
+       set $stack_end= ((TCB_t)*$tcb)->pxStack
+       set $stack_cur = (unsigned int)((TCB_t)*$tcb)->pxTopOfStack
+       set $stack_top = $stack_end+$stack_size
+       set $stack_s0 = 0
+       #dump_stack
+       travel_stack
+       set $list_start = $list_start.pxNext
+   end
+   
+end
+
+
+
+if xDelayedTaskList2.uxNumberOfItems >0
+   Make_FMTMarker
+
+   echo xDelayedTaskList2.uxNumberOfItems\n
+   p xDelayedTaskList2.uxNumberOfItems
+   set $list_end = xDelayedTaskList2->pxIndex
+   set $list_start = xDelayedTaskList2->xListEnd.pxNext
+   
+  
+   while ($list_start != $list_end)
+       set $tcb = (char*)$list_start - 4
+       #p (TCB_t)*$tcb
+       p ((TCB_t)*$tcb)->pcTaskName
+       p ((TCB_t)*$tcb)->pxStack
+       p ((TCB_t)*$tcb)->pxTopOfStack
+       set $stack_end= ((TCB_t)*$tcb)->pxStack
+       set $stack_cur = (unsigned int)((TCB_t)*$tcb)->pxTopOfStack
+       set $stack_top = $stack_end+$stack_size
+       set $stack_s0 = 0
+       #dump_stack
+       travel_stack
+       set $list_start = $list_start.pxNext
+   end
+   
+end
+
+
+
+if xPendingReadyList.uxNumberOfItems >0
+   Make_FMTMarker
+   echo xPendingReadyList.uxNumberOfItems\n
+   p xPendingReadyList.uxNumberOfItems
+   set $list_end = xPendingReadyList->pxIndex
+   set $list_start = xPendingReadyList->xListEnd.pxNext
+   
+  
+   while ($list_start != $list_end)
+       p $list_start
+       set $tcb = (char*)$list_start - 4
+       #p (TCB_t)*$tcb
+       p ((TCB_t)*$tcb)->pcTaskName
+       p ((TCB_t)*$tcb)->pxStack
+       p ((TCB_t)*$tcb)->pxTopOfStack
+       set $stack_end= ((TCB_t)*$tcb)->pxStack
+       set $stack_cur = (unsigned int)((TCB_t)*$tcb)->pxTopOfStack
+       set $stack_top = $stack_end+$stack_size
+       set $stack_s0 = 0
+       #dump_stack
+       travel_stack
+       set $list_start = $list_start.pxNext
+   end
+   
+end
+
+if xTasksWaitingTermination.uxNumberOfItems >0
+   Make_FMTMarker
+   echo xTasksWaitingTermination.uxNumberOfItems\n
+   p xTasksWaitingTermination.uxNumberOfItems
+   set $list_end = xTasksWaitingTermination->pxIndex
+   set $list_start = xTasksWaitingTermination->xListEnd.pxNext
+   
+  
+   while ($list_start != $list_end)
+       set $tcb = (char*)$list_start - 4
+       #p (TCB_t)*$tcb
+       p ((TCB_t)*$tcb)->pcTaskName
+       p ((TCB_t)*$tcb)->pxStack
+       p ((TCB_t)*$tcb)->pxTopOfStack
+       set $stack_end= ((TCB_t)*$tcb)->pxStack
+       set $stack_cur = (unsigned int)((TCB_t)*$tcb)->pxTopOfStack
+       set $stack_top = $stack_end+$stack_size
+       set $stack_s0 = 0
+       #dump_stack
+       travel_stack
+       set $list_start = $list_start.pxNext
+   end
+   
+end
+
+
+
+
+
+
+
+
+
+#
+# Turn off log
+#
+set logging off
\ No newline at end of file
diff --git a/tools/dump_tools/backtrace.sh b/tools/dump_tools/backtrace.sh
new file mode 100755
index 0000000..5516850
--- /dev/null
+++ b/tools/dump_tools/backtrace.sh
@@ -0,0 +1,28 @@
+#!/bin/bash
+
+usage() {
+    echo -e "Usage :"
+    echo -e "   $0 [log file] [out file]"
+    echo -e "   log file: error dump log file"
+    echo -e "   out file: .out execute file"
+    echo -e ""
+    echo -e "example:"
+    echo -e "   $0 stack.txt ht_cco.out"
+    echo -e ""
+}
+
+if [ ! -n "$1" ]; then
+    usage
+    exit
+fi
+
+if [ ! -n "$2" ]; then
+    usage
+    exit
+fi
+
+STACK_FILE=$1
+OUT_NAME=$2
+
+tail -n 1000 $STACK_FILE | awk '{print $2}' | grep "0x[0-9A-Fa-f]*" | \
+xargs riscv64-unknown-elf-addr2line -f -e $OUT_NAME
diff --git a/tools/ftdi_openocd.cfg b/tools/ftdi_openocd.cfg
new file mode 100644
index 0000000..4c6be3b
--- /dev/null
+++ b/tools/ftdi_openocd.cfg
@@ -0,0 +1,34 @@
+adapter_khz     10000
+
+interface ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x001b
+ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
+
+#Reset Stretcher logic on FE310 is ~1 second long
+#This doesn't apply if you use
+# ftdi_set_signal, but still good to document
+#adapter_nsrst_delay 1500
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+#flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+#reset -- This type of reset is not implemented yet
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+  #Wait for the reset stretcher
+  #It will work without this, but
+  #will incur lots of delays for later commands.
+  sleep 1500
+}	
+halt
+#flash protect 0 64 last off
diff --git a/tools/gen_ai_sdk.sh b/tools/gen_ai_sdk.sh
new file mode 100755
index 0000000..686a9c3
--- /dev/null
+++ b/tools/gen_ai_sdk.sh
@@ -0,0 +1,69 @@
+#!/bin/sh
+
+cd build/
+./build_kl2_flash_ai.sh
+cd -
+source build/env_flash_ai_kl2.sh
+make dtest
+
+OUTPUT_SDK=./output_sdk
+
+mkdir ${OUTPUT_SDK}
+
+mkdir ${OUTPUT_SDK}/bin
+mkdir ${OUTPUT_SDK}/bin/ai
+mkdir ${OUTPUT_SDK}/cmake
+mkdir ${OUTPUT_SDK}/examples
+mkdir ${OUTPUT_SDK}/ld
+mkdir ${OUTPUT_SDK}/tools
+
+# cp xxx.bin
+cp ./tools/gen_img/customer/2M/kl2/ai/out/KL2AI01_OEM.bin ${OUTPUT_SDK}/bin/ai/oem.bin
+cp ./tools/gen_img/customer/2M/kl2/ai/out/KL2AI01_PIB.bin ${OUTPUT_SDK}/bin/ai/pib.bin
+cp ./tools/gen_img/customer/2M/kl2/ai/out/kl_ram.bin ${OUTPUT_SDK}/bin/ai/ram.bin
+cp ./tools/gen_img/customer/2M/kl2/ai/out/kunlun_sbl.bin ${OUTPUT_SDK}/bin/ai/sbl.bin
+cp ./tools/gen_img/customer/2M/kl2/ai/out/sp_fw.bin ${OUTPUT_SDK}/bin/ai/sp.bin
+
+# cp lib inc tool
+cp ./export/* ${OUTPUT_SDK}/ -r
+cp ./tools/gen_img/ah ${OUTPUT_SDK}/tools/
+cp ./tools/gen_img/elzma ${OUTPUT_SDK}/tools/
+cp ./tools/kl2_gdbinit ${OUTPUT_SDK}/tools/
+cp ./tools/ftdi_openocd.cfg ${OUTPUT_SDK}/tools/
+cp ./dtest/download_file_test/.output/lib/download_file_test.out ${OUTPUT_SDK}/tools/
+cp ./dtest/ddr_training_test/.output/lib/ddr_training_test.out ${OUTPUT_SDK}/tools/
+
+# cp fatfs include file
+mkdir ${OUTPUT_SDK}/inc/fatfs
+cp ./import/fatfs/inc/ff.h ${OUTPUT_SDK}/inc/fatfs/
+cp ./import/fatfs/inc/ffconf.h ${OUTPUT_SDK}/inc/fatfs/
+cp ./import/fatfs/inc/integer.h ${OUTPUT_SDK}/inc/fatfs/
+
+rm ${OUTPUT_SDK}/lib/*
+cp ./export/lib/libht_ai.a ./export/lib/README ${OUTPUT_SDK}/lib/
+
+# cp ld
+cp ./startup/ldscripts/riscv2/link_ai_32m.lds ${OUTPUT_SDK}/ld/link.lds
+cp ./startup/ldscripts/riscv2/link_cpu0.lds ${OUTPUT_SDK}/ld/
+cp ./startup/ldscripts/riscv2/link_cpu2.lds ${OUTPUT_SDK}/ld/
+
+# cp sdk
+cp ../SDKCmake/cmake/riscv64.toolchain.cmake  ${OUTPUT_SDK}/cmake/
+cp ../SDKCmake/iot_kl2_sample_app/iot_cpp_app  ${OUTPUT_SDK}/examples/ -r
+cp ./app/cpp_demo ${OUTPUT_SDK}/examples/iot_cpp_app/ -r
+
+# cp app
+# cpp app
+cp ../SDKCmake/iot_kl2_sample_app/iot_cpp_app  ${OUTPUT_SDK}/examples/ -r
+# c app
+cp ../SDKCmake/iot_kl2_sample_app/iot_test_app  ${OUTPUT_SDK}/examples/ -r
+# amp app
+cp ../SDKCmake/iot_kl2_sample_app/iot_test_app_amp  ${OUTPUT_SDK}/examples/ -r
+# uart demo app
+cp ../SDKCmake/iot_kl2_sample_app/iot_uart_app  ${OUTPUT_SDK}/examples/ -r
+
+# add exe
+chmod +x ${OUTPUT_SDK}/examples/iot_cpp_app/scripts/build-ai.sh
+chmod +x ${OUTPUT_SDK}/examples/iot_test_app/scripts/build-ai.sh
+chmod +x ${OUTPUT_SDK}/examples/iot_test_app_amp/scripts/build-ai.sh
+
diff --git a/tools/gen_ate.sh b/tools/gen_ate.sh
new file mode 100755
index 0000000..87fdfb9
--- /dev/null
+++ b/tools/gen_ate.sh
@@ -0,0 +1,47 @@
+#!/bin/sh
+
+source build/env_flash_ai_kl2.sh
+make clobber
+make
+
+DATA=`date '+%m%d'`
+ATE_CASE='ate_ddr_flash_test'
+
+echo ""
+echo "[ATE TEST CASE]"${ATE_CASE}
+
+OUTPUT_DIR=${ATE_CASE}_${DATA}
+ATE_HEADFILE=./dtest/${ATE_CASE}/${ATE_CASE}.c
+
+OUTPUT_FOLDER=./dtest/${ATE_CASE}/${OUTPUT_DIR}
+mkdir ${OUTPUT_FOLDER}
+
+# debug version
+sed -i "s,^#define LOG_ENABLE .*$,#define LOG_ENABLE 1,g"  $ATE_HEADFILE
+make dtest
+OUTPUT_FOLDER=./dtest/${ATE_CASE}/${OUTPUT_DIR}/debug
+mkdir ${OUTPUT_FOLDER}
+cp ./dtest/${ATE_CASE}/.output/lib/* ${OUTPUT_FOLDER}
+cd ${OUTPUT_FOLDER}
+riscv64-unknown-elf-objdump  -D -S ${ATE_CASE}.out > ${ATE_CASE}.asm
+elf2hex 268275712 4 32768 ${ATE_CASE}.out > ${ATE_CASE}.hex
+cd -
+
+# release version
+sed -i "s,^#define LOG_ENABLE .*$,#define LOG_ENABLE 0,g"  $ATE_HEADFILE
+make dtest
+OUTPUT_FOLDER=./dtest/${ATE_CASE}/${OUTPUT_DIR}/release
+mkdir ${OUTPUT_FOLDER}
+cp ./dtest/${ATE_CASE}/.output/lib/* ${OUTPUT_FOLDER}
+cd ${OUTPUT_FOLDER}
+riscv64-unknown-elf-objdump  -D -S ${ATE_CASE}.out > ${ATE_CASE}.asm
+elf2hex 268275712 4 32768 ${ATE_CASE}.out > ${ATE_CASE}.hex
+cd -
+
+# recover to debug set
+sed -i "s,^#define LOG_ENABLE .*$,#define LOG_ENABLE 1,g"  $ATE_HEADFILE
+
+echo ""
+echo "[ATE TEST CASE]"${ATE_CASE}" finish"
+echo ""
+
diff --git a/tools/gen_img/gen_img.sh b/tools/gen_img/gen_img.sh
new file mode 100755
index 0000000..d3417f3
--- /dev/null
+++ b/tools/gen_img/gen_img.sh
@@ -0,0 +1,1103 @@
+#!/bin/bash
+
+CUR_DIR=$(cd `dirname $0`; pwd)
+TOP_DIR=$CUR_DIR/../..
+PSRAM_ENABLE_GEN=$(echo $psram_enable)
+FLASH_LAYOUT_INDEX=$(echo $layout_index)
+PROTO_TYPE=$(echo ${PROTO_TYPE} | tr '[a-z]' '[A-Z]')
+RF_ENABLE=$(echo ${rf_enable})
+DUAL_ENABLE=$(echo ${dual_enable})
+NEW_TYPE_CCO=$(echo ${new_type_cco})
+SEC_CPU_ENABLE=$(echo ${sec_cpu_enable})
+while getopts "d:c:i:r:m:s:a:b:v:h:p:t:f:" arg
+do
+    case $arg in
+        c)
+            echo "c's arg: $OPTARG"
+            BOARD_LOWER=$OPTARG
+            ;;
+        d)
+            echo "d's arg: $OPTARG"
+            CHIP_ID=$OPTARG
+            ;;
+        i)
+            echo "i's arg: $OPTARG"
+            IMG_LOWER=$OPTARG
+            ;;
+        r)
+            echo "r's arg: $OPTARG"
+            RUN_LOWER=$OPTARG
+            ;;
+        m)
+            echo "m's arg: $OPTARG"
+            MODE_LOWER=$OPTARG
+            ;;
+        s)
+            echo "s's arg: $OPTARG"
+            SIZE_LOWER=$OPTARG
+            ;;
+        a)
+            echo "a's arg: $OPTARG"
+            APP_LOWER=$OPTARG
+            ;;
+        b)
+            echo "b's arg: $OPTARG"
+            CHIP_VER_LOWER=$OPTARG
+            ;;
+        v)
+            echo "v's arg: $OPTARG"
+            DB_LOWER=$OPTARG
+            ;;
+        p)
+            echo "p's arg: $OPTARG"
+            PSRAM_SIZE=$OPTARG
+            ;;
+        t)
+            echo "t's arg: $OPTARG"
+            CORE_TYPE_LOWER=$OPTARG
+            ;;
+        f)
+            echo "f's arg: $OPTARG"
+            FAST_BOOT=$OPTARG
+            ;;
+        h)
+            echo "[Usage]"
+            echo "$0 -d (hw chip id) -c (custom name) -i (image type) -r (run environment) -m (mode type) -s (flash size) -a (app_name)"
+            exit 1
+            ;;
+        ?)
+            echo "unsupport argument"
+            echo "[Usage]"
+            echo "$0 -d (hw chip id) -c (custom name) -i (image type) -r (run environment) -s (flash size) -a (app_name)"
+            exit 1
+            ;;
+    esac
+done
+
+if [ "$BOARD_LOWER" == "" ] || [ "$CHIP_ID" == "" ] || [ "$IMG_LOWER" == "" ] || [ "$RUN_LOWER" == "" ]; then
+    echo "input argument error"
+    echo "[Usage]"
+    echo "$0 -d (hw chip id) -c (custom name) -i (image type) -r (run environment)"
+    exit 1
+fi
+
+#get iot_ver from iot_version.h.
+IOT_VER_FILE="${TOP_DIR}/inc/iot_version.h"
+get_iot_ver() {
+    ver_file=$1
+    major_ver=`cat ${ver_file} |grep " AP_FIRMWARE_VERSION_MAJOR"|awk '{print $3}'`
+    mionor_ver=`cat ${ver_file} |grep " AP_FIRMWARE_VERSION_MINOR"|awk '{print $3}'`
+    micro_ver=`cat ${ver_file} |grep " AP_FIRMWARE_VERSION_MICRO"|awk '{print $3}'`
+    build_ver=`cat ${ver_file} |grep " AP_FIRMWARE_VERSION_BUILD"|awk '{print $3}'`
+
+    major_ver=${major_ver//(/}
+    major_ver=${major_ver//)/}
+    mionor_ver=${mionor_ver//(/}
+    mionor_ver=${mionor_ver//)/}
+    micro_ver=${micro_ver//(/}
+    micro_ver=${micro_ver//)/}
+    build_ver=${build_ver//(/}
+    build_ver=${build_ver//)/}
+
+    IOT_VER="${major_ver}.${mionor_ver}.${micro_ver}.${build_ver}"
+    return
+}
+
+if [ "$PSRAM_ENABLE_GEN" == "1" ]; then
+    if [ "$PSRAM_SIZE" == "" ] || [ "$PSRAM_SIZE" == "4" ]; then
+    #   the default psram size is 4m
+        PSRAM_SIZE_STR="F"
+        PSRAM_SIZE_PARAM="P4"
+    elif [ "$PSRAM_SIZE" == "8" ]; then
+        PSRAM_SIZE_STR="E"
+        PSRAM_SIZE_PARAM="P8"
+    else
+        PSRAM_SIZE_STR="T"
+        PSRAM_SIZE_PARAM="P2"
+    fi
+else
+    PSRAM_SIZE="0"
+    PSRAM_SIZE_PARAM="P0"
+fi
+
+#distinguish iot or sg app.
+if [ "$APP_LOWER" == "plc_uart" ] || [ "$APP_LOWER" == "demo" ] || [ "$APP_LOWER" == "ge" ] || [ "$APP_LOWER" == "ge_ckq" ] \
+    || [ "$APP_LOWER" == "ge_lwip" ] || [ "$APP_LOWER" == "ge_ext" ] || [ "$APP_LOWER" == "cus_at" ] \
+    || [ "$APP_LOWER" == "demo_lwip" ] || [ "$APP_LOWER" == "iot_sniffer" ] \
+    || [ "$APP_LOWER" == "ge_micro" ] || [ "$APP_LOWER" == "sila" ] || [ "$APP_LOWER" == "at_micro" ] || [ "$APP_LOWER" == "iot_dl645" ]; then
+    IOT_SMART_BUILD=1
+    APP_UPPER=$(echo $APP_LOWER | tr '[a-z]' '[A-Z]')
+else
+    IOT_SMART_BUILD=0
+    if [ "$APP_LOWER" == "brm" ] || [ "$APP_LOWER" == "brk" ] || [ "$APP_LOWER" == "tfm" ] || [ "$APP_LOWER" == "bsrm" ] \
+        || [ "$APP_LOWER" == "bsrm_cus" ] || [ "$APP_LOWER" == "solr" ] || [ "$APP_LOWER" == "sg_ext" ] \
+        || [ "$APP_LOWER" == "sg_meter" ] || [ "$APP_LOWER" == "sniffer" ]; then
+        APP_UPPER=$(echo $APP_LOWER | tr '[a-z]' '[A-Z]')
+    else
+        APP_UPPER="SG"
+    fi
+fi
+
+if [ "$DB_LOWER" == "release" ]; then
+    DB_RLS_FLAG="R"
+else
+    DB_LOWER="debug"
+    DB_RLS_FLAG="D"
+fi
+
+BOARD_UPPER=$(echo $BOARD_LOWER | tr '[a-z]' '[A-Z]')
+IMG_UPPER=$(echo $IMG_LOWER | tr '[a-z]' '[A-Z]')
+RUN_UPPER=$(echo $RUN_LOWER | tr '[a-z]' '[A-Z]')
+MODE_UPPER=$(echo $MODE_LOWER | tr '[a-z]' '[A-Z]')
+SIZE_UPPER=$(echo $SIZE_LOWER | tr '[a-z]' '[A-Z]')
+CHIP_VER_UPPER=$(echo $CHIP_VER_LOWER | tr '[a-z]' '[A-Z]')
+CORE_TYPE_UPPER=$(echo $CORE_TYPE_LOWER | tr '[a-z]' '[A-Z]')
+
+# cleanup old file.
+rm -f $CUR_DIR/sbl.bin
+rm -f $CUR_DIR/pib.bin
+rm -f $CUR_DIR/sp.bin
+rm -f $CUR_DIR/oem.bin
+rm -f $CUR_DIR/ht.bin
+rm -f $CUR_DIR/ht_1p.bin
+rm -f $CUR_DIR/ht*.fw
+
+if [ "x${CHIP_VER_UPPER}" == "x3" ]; then
+    # clear files and generate folders
+    if [ "x${CORE_TYPE_UPPER}" == "xAMPPLC" ]; then
+        rm -f $CUR_DIR/ht_cus.bin
+        rm -f $CUR_DIR/ht_cus.bin.fw
+        rm -f $CUR_DIR/ht_cus_ori.bin
+    fi
+    rm -f $CUR_DIR/ht_ori.bin
+
+    if [[ "${BOARD_LOWER}" == "fpga"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/fpga/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/fpga/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "evb32"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/hz_evb/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/hz_evb/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "evb558"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/qj_evb/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/qj_evb/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "evb671"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/flx_evb/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/flx_evb/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "htzd3211pt03" ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/pt/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/pt/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "htzd"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/htzd/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/htzd/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "qj"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/qj/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/qj/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "flx"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/flx/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/flx/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "spe"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/spe/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/spe/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "gx"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/gx/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/gx/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "dt"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/dt/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/dt/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "evb5202"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/evb5202/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/evb5202/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "goldfinger_17p"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/goldfinger_17p/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/goldfinger_17p/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "stamp"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/stamp/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/stamp/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "ledc"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/ledc/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/ledc/${IMG_LOWER}/out/
+    elif [[ "${BOARD_LOWER}" == "yp"* ]]; then
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/yp/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/yp/${IMG_LOWER}/out/
+    else
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/${BOARD_LOWER}/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/${BOARD_LOWER}/${IMG_LOWER}/out/
+    fi
+
+    mkdir -p $BIN_PATH
+    mkdir -p $OUT_PATH
+
+    if [ "x${CORE_TYPE_UPPER}" == "xAMPPLC" ]; then
+        CFG_DIR=${TOP_DIR}"/build/cfg3"
+    else
+        CFG_DIR=${TOP_DIR}"/build/cfg3_plc"
+    fi
+    LDS_DIR=${TOP_DIR}"/startup/ldscripts/riscv3"
+
+    if [ "${RUN_UPPER}" == "UPGRADE" ]; then
+        if [ "${SIZE_UPPER}" != "" ]; then
+            if [ "$PSRAM_ENABLE_GEN" == "1" ]; then
+                CFG_NAME=${CFG_DIR}"/"${SIZE_LOWER}"_"${IMG_LOWER}"_upgrade_psram.cfg"
+            else
+                CFG_NAME=${CFG_DIR}"/"${SIZE_LOWER}"_"${IMG_LOWER}"_upgrade.cfg"
+            fi
+        else
+            CFG_NAME=${CFG_DIR}"/"${IMG_LOWER}"_upgrade.cfg"
+        fi
+    else
+        if [ ${IOT_SMART_BUILD} == 1 ]; then
+            if [ "${SIZE_UPPER}" == "2M" ] || [ "${SIZE_UPPER}" == "4M" ]; then
+                if [ "${RUN_UPPER}" == "PSRAM" ]; then
+                    CFG_NAME=${CFG_DIR}"/smart_"${SIZE_LOWER}"_"${IMG_LOWER}_psram.cfg
+                else
+                    CFG_NAME=${CFG_DIR}"/smart_"${SIZE_LOWER}"_"${IMG_LOWER}.cfg
+                fi
+            else
+                CFG_NAME=${CFG_DIR}"/smart_"${IMG_LOWER}.cfg
+            fi
+        else
+            if [ "${SIZE_UPPER}" != "" ]; then
+                 if [ "${RUN_UPPER}" == "PSRAM" ]; then
+                     CFG_NAME=${CFG_DIR}"/"${SIZE_LOWER}"_"${IMG_LOWER}_psram.cfg
+                 else
+                     CFG_NAME=${CFG_DIR}"/"${SIZE_LOWER}"_"${IMG_LOWER}.cfg
+                 fi
+            else
+                 if [ "${RUN_UPPER}" == "PSRAM" ]; then
+                     CFG_NAME=${CFG_DIR}"/"${IMG_LOWER}_psram.cfg
+                 else
+                     CFG_NAME=${CFG_DIR}"/"${IMG_LOWER}.cfg
+                 fi
+            fi
+        fi
+    fi
+
+    TMP_CFG_NAME=${CFG_DIR}"/"${BOARD_LOWER}_${IMG_LOWER}_tmp.cfg
+    cp  ${CFG_NAME} ${TMP_CFG_NAME}
+
+    if [ "x${FAST_BOOT}" == "x1" ]; then
+        OPT_KEYWORD="FB-"
+    else
+        OPT_KEYWORD=""
+    fi
+
+    if [ "x${DUAL_ENABLE}" == "x1" ]; then
+        OPT_KEYWORD=DUAL-${OPT_KEYWORD}
+    fi
+
+    if [ "x${RF_ENABLE}" == "x1" ]; then
+        OPT_KEYWORD=RF-${OPT_KEYWORD}
+    fi
+
+    #set option keyword to fw name for kl3.
+    OPT_KEYWORD=${PROTO_TYPE}-${OPT_KEYWORD}
+    if [ "x${CORE_TYPE_UPPER}" == "xAMPPLC" ]; then
+        OPT_KEYWORD="AMPPLC-${OPT_KEYWORD}"
+    fi
+
+    # prepare ht.bin
+    if [ "${IMG_UPPER}" == "CKB" ]; then
+        HT_FILE="ht_sta.bin"
+    else
+        HT_FILE="ht_"${IMG_LOWER}".bin"
+    fi
+    if [ "x${CORE_TYPE_UPPER}" == "xAMPPLC" ]; then
+        cp ${TOP_DIR}/ap/.output/cus/lib/${HT_FILE} $CUR_DIR/ht_cus.bin
+    fi
+
+    if [[ "${BOARD_LOWER}" == "*3201*" ]]; then
+        chip_ver=3201
+    fi
+
+    if [[ "${BOARD_LOWER}" == "*3211*" ]]; then
+        chip_ver=3211
+    fi
+
+    if [[ "${BOARD_LOWER}" == "*3031*" ]]; then
+        chip_ver=3031
+    fi
+
+    if [ "${IMG_UPPER}" == "CCO" ]; then
+        if [ ${IOT_SMART_BUILD} == 1 ]; then
+            if [ "${chip_ver}" == "3201" ]; then
+                cp $CUR_DIR/iot_ht_3p.bin $CUR_DIR/ht.bin
+            fi
+            cp $CUR_DIR/iot_ht_1p.bin $CUR_DIR/ht_1p.bin
+        else
+            cp $CUR_DIR/iot_ht_3p.bin $CUR_DIR/ht.bin
+        fi
+    else
+        cp ${TOP_DIR}/ap/.output/plc/lib/${HT_FILE} $CUR_DIR/ht.bin
+    fi
+
+    sed -i "/img_type=./a layout_index=${FLASH_LAYOUT_INDEX}" ${TMP_CFG_NAME}
+
+    #config run address and little header of img.
+    sbl_lds_file="${LDS_DIR}/link_sbl.lds"
+    sbl_run_addr=`grep -ri "iram\ (rxai\!w)" ${sbl_lds_file}|awk '{print $6}'|awk -F, '{print $1}'`
+    sed -i "/path=\.\/sbl.bin/a run_addr=${sbl_run_addr}" ${TMP_CFG_NAME}
+
+    if [ "x${FAST_BOOT}" == "x1" ]; then
+        sed -i "s/fastboot=./fastboot=1/g" ${TMP_CFG_NAME}
+    fi
+
+    if [ "x${CORE_TYPE_UPPER}" == "xAMPPLC" ]; then
+        # add run addr
+        cus_lds_file=$CUR_DIR/tmp_cus.lds
+        lds_file=$CUR_DIR/tmp_plc.lds
+
+        sed -i "/flash_size=./a psram_size=${PSRAM_SIZE}" ${TMP_CFG_NAME}
+        plc_run_addr=`grep -ri "flash\ (rxai\!w)" ${lds_file}|awk '{print $6}'|awk -F, '{print $1}'`
+        cus_run_addr=`grep -ri "flash\ (rxai\!w)" ${cus_lds_file} |awk '{print $6}'|awk -F, '{print $1}'`
+        sed -i "/path=\.\/ht.bin/a run_addr=${plc_run_addr}" ${TMP_CFG_NAME}
+        sed -i "/path=\.\/ht_cus.bin/a run_addr=${cus_run_addr}" ${TMP_CFG_NAME}
+
+        # add iot version
+        get_iot_ver ${IOT_VER_FILE}
+        sed -i "s/version=.*/version=${IOT_VER}/g" ${TMP_CFG_NAME}
+
+        if [ "${IMG_UPPER}" == "CCO" ] && [ ${IOT_SMART_BUILD} == 1 ]; then
+            sed -i "s/ht.bin/ht_1p.bin/g" ${TMP_CFG_NAME}
+            # add header
+            ./ah -a ${TMP_CFG_NAME}
+            sed -i "s/ht_1p.bin/ht.bin/g" ${TMP_CFG_NAME}
+            if [ "${chip_ver}" == "3201" ]; then
+                #avoid ht_cus.bin add head twice
+                sed -i "s/ht_cus.bin/ht_cus_tmp.bin/g" ${TMP_CFG_NAME}
+                # add header
+                ./ah -a ${TMP_CFG_NAME}
+                sed -i "s/ht_cus_tmp.bin/ht_cus.bin/g" ${TMP_CFG_NAME}
+            fi
+        else
+            # add header
+            ./ah -a ${TMP_CFG_NAME}
+        fi
+    else
+        # add run addr
+        lds_file=$CUR_DIR/tmp_plc.lds
+
+        sed -i "/flash_size=./a psram_size=${PSRAM_SIZE}" ${TMP_CFG_NAME}
+        plc_run_addr=`grep -ri "flash\ (rxai\!w)" ${lds_file}|awk '{print $6}'|awk -F, '{print $1}'`
+        sed -i "/path=\.\/ht.bin/a run_addr=${plc_run_addr}" ${TMP_CFG_NAME}
+
+        # add iot version
+        get_iot_ver ${IOT_VER_FILE}
+        sed -i "s/version=.*/version=${IOT_VER}/g" ${TMP_CFG_NAME}
+
+        if [ "${IMG_UPPER}" == "CCO" ] && [ ${IOT_SMART_BUILD} == 1 ]; then
+            sed -i "s/ht.bin/ht_1p.bin/g" ${TMP_CFG_NAME}
+            # add header
+            ./ah -a ${TMP_CFG_NAME}
+            sed -i "s/ht_1p.bin/ht.bin/g" ${TMP_CFG_NAME}
+            if [ "${chip_ver}" == "3201" ]; then
+                # add header
+                ./ah -a ${TMP_CFG_NAME}
+            fi
+        else
+            # add header
+            ./ah -a ${TMP_CFG_NAME}
+        fi
+    fi
+
+    #config lzma.
+    if [ "${MODE_UPPER}" == "LZMA" ]; then
+        if [ "x${CORE_TYPE_UPPER}" == "xAMPPLC" ] && [ "x${FAST_BOOT}" != "x1" ]; then
+            ./elzma e $CUR_DIR/ht_cus.bin $CUR_DIR/ht_cus.bin.lzma
+            cp $CUR_DIR/ht_cus.bin  $CUR_DIR/ht_cus.bin.fw
+            mv $CUR_DIR/ht_cus.bin.lzma $CUR_DIR/ht_cus.bin
+        fi
+
+        if [ "${IMG_UPPER}" == "CCO" ] && [ ${IOT_SMART_BUILD} == 1 ]; then
+            ./elzma e $CUR_DIR/ht_1p.bin $CUR_DIR/ht_1p.bin.lzma
+            cp $CUR_DIR/ht_1p.bin  $CUR_DIR/ht_1p.bin.fw
+            mv  $CUR_DIR/ht_1p.bin.lzma $CUR_DIR/ht_1p.bin
+            if [ "${chip_ver}" == "3201" ]; then
+                ./elzma e $CUR_DIR/ht.bin $CUR_DIR/ht.bin.lzma
+                cp $CUR_DIR/ht.bin  $CUR_DIR/ht.bin.fw
+                mv  $CUR_DIR/ht.bin.lzma $CUR_DIR/ht.bin
+            fi
+        else
+            ./elzma e $CUR_DIR/ht.bin $CUR_DIR/ht.bin.lzma
+            cp $CUR_DIR/ht.bin  $CUR_DIR/ht.bin.fw
+            mv  $CUR_DIR/ht.bin.lzma $CUR_DIR/ht.bin
+        fi
+    fi
+
+    cp $TOP_DIR/sbl/.output/plc/lib/kunlun_sbl.bin $CUR_DIR/sbl.bin
+    # Kl3 compiles ram.bin separately to improve compilation speed, so do not need process ram.bin here.
+
+    if [ "${BOARD_UPPER}" == "QJ5580DCCO03" ] || [ "${BOARD_UPPER}" == "QJ5580DCKB03" ] || [ "${BOARD_UPPER}" == "QJ5582DSTA03" ] || [ "${BOARD_UPPER}" == "QJ5582DIIC03" ] ||
+       [ "${BOARD_UPPER}" == "QJ5582D3PS03" ] || [ "${BOARD_UPPER}" == "EVB5580DCCO03" ] || [ "${BOARD_UPPER}" == "EVB5582DSTA03" ] || [ "${BOARD_UPPER}" == "EVB5582D3PS03" ]; then
+        sed -i "s,encrypt_mode=0x0,encrypt_mode=0x3,g" ${TMP_CFG_NAME}
+        sed -i "s,encrypt_pattern=0x55,encrypt_pattern=0x66,g" ${TMP_CFG_NAME}
+        sed -i "s,vendor_id=18516,vendor_id=20810,g" ${TMP_CFG_NAME}
+    fi
+
+    if [ "${BOARD_UPPER}" == "FLX6710CCO03" ] || [ "${BOARD_UPPER}" == "FLX6710CKB03" ] || [ "${BOARD_UPPER}" == "FLX6711STA03" ] || [ "${BOARD_UPPER}" == "FLX6711IIC03" ] ||
+       [ "${BOARD_UPPER}" == "FLX67113PS03" ] || [ "${BOARD_UPPER}" == "EVB6710CCO03" ] || [ "${BOARD_UPPER}" == "EVB6711STA03" ] || [ "${BOARD_UPPER}" == "EVB67113PS03" ]; then
+        sed -i "s,encrypt_mode=0x0,encrypt_mode=0x3,g" ${TMP_CFG_NAME}
+        sed -i "s,encrypt_pattern=0x55,encrypt_pattern=0x99,g" ${TMP_CFG_NAME}
+        sed -i "s,vendor_id=18516,vendor_id=20552,g" ${TMP_CFG_NAME}
+    fi
+
+    if [ "${BOARD_UPPER}" == "SPE7303CCO03" ] || [ "${BOARD_UPPER}" == "SPE7303CKB03" ] || [ "${BOARD_UPPER}" == "SPE7301STA03" ] || [ "${BOARD_UPPER}" == "SPE7301IIC03" ] ||
+       [ "${BOARD_UPPER}" == "SPE73013PS03" ]; then
+        sed -i "s,encrypt_mode=0x0,encrypt_mode=0x3,g" ${TMP_CFG_NAME}
+        sed -i "s,encrypt_pattern=0x55,encrypt_pattern=0xcc,g" ${TMP_CFG_NAME}
+        sed -i "s,vendor_id=18516,vendor_id=20549,g" ${TMP_CFG_NAME}
+    fi
+
+    if [ "${BOARD_UPPER}" == "GX2001CCO03" ] || [ "${BOARD_UPPER}" == "GX2001CKB03" ] || [ "${BOARD_UPPER}" == "GX2011STA03" ] || [ "${BOARD_UPPER}" == "GX2011IIC03" ] ||
+       [ "${BOARD_UPPER}" == "GX20113PS03" ]; then
+        sed -i "s,encrypt_mode=0x0,encrypt_mode=0x3,g" ${TMP_CFG_NAME}
+        sed -i "s,encrypt_pattern=0x55,encrypt_pattern=0x33,g" ${TMP_CFG_NAME}
+        sed -i "s,vendor_id=18516,vendor_id=18264,g" ${TMP_CFG_NAME}
+    fi
+
+    if [ "${BOARD_UPPER}" == "DT0530CCO03" ] || [ "${BOARD_UPPER}" == "DT0531STA03" ] || [ "${BOARD_UPPER}" == "DT0531IIC03" ] || [ "${BOARD_UPPER}" == "DT05313PS03" ] ||
+       [ "${BOARD_UPPER}" == "DT0530CKB03" ]; then
+        sed -i "s,encrypt_mode=0x0,encrypt_mode=0x3,g" ${TMP_CFG_NAME}
+        sed -i "s,encrypt_pattern=0x55,encrypt_pattern=0xdd,g" ${TMP_CFG_NAME}
+        sed -i "s,vendor_id=18516,vendor_id=17492,g" ${TMP_CFG_NAME}
+    fi
+
+    if [ "${BOARD_UPPER}" == "YP8801CCO03" ] || [ "${BOARD_UPPER}" == "YP8811STA03" ] || [ "${BOARD_UPPER}" == "YP88113PS03" ] || [ "${BOARD_UPPER}" == "YP8801CKB03" ] ||
+       [ "${BOARD_UPPER}" == "YP8811IIC03" ]; then
+        sed -i "s,encrypt_mode=0x0,encrypt_mode=0x3,g" ${TMP_CFG_NAME}
+        sed -i "s,encrypt_pattern=0x55,encrypt_pattern=0xa9,g" ${TMP_CFG_NAME}
+        sed -i "s,vendor_id=18516,vendor_id=22864,g" ${TMP_CFG_NAME}
+    fi
+
+    # prepare oem.bin
+    if [ "x${CORE_TYPE_UPPER}" == "xAMPPLC" ]; then
+        if [ ${IOT_SMART_BUILD} == 1 ]; then
+            OEM_CFG=${BOARD_UPPER}"_AMPIOT_OEM.ini"
+            OEM_FILE=${BOARD_UPPER}"_AMPIOT_OEM.bin"
+        else
+            OEM_CFG=${BOARD_UPPER}"_AMPSG_OEM.ini"
+            OEM_FILE=${BOARD_UPPER}"_AMPSG_OEM.bin"
+        fi
+    else
+        OEM_CFG=${BOARD_UPPER}"_OEM.ini"
+        OEM_FILE=${BOARD_UPPER}"_OEM.bin"
+    fi
+    cp $TOP_DIR/tools/oem/$OEM_CFG ./tmp_oem.ini
+    #set mid for iot board(cco and sta use same oem.ini)
+    if [ ${IOT_SMART_BUILD} == 1 ]; then
+        if [ "${IMG_UPPER}" == "CCO" ]; then
+            sed -i "s/mid.*/mid 1/g" ./tmp_oem.ini
+        elif [ "${IMG_UPPER}" == "STA" ]; then
+            sed -i "s/mid.*/mid 0/g" ./tmp_oem.ini
+        fi
+    fi
+    if [ "${RUN_UPPER}" != "UPGRADE" ]; then
+        ./oem_tool --input=./tmp_oem.ini --output=$TOP_DIR/tools/oem/$OEM_FILE
+    fi
+    rm ./tmp_oem.ini
+    cp $TOP_DIR/tools/oem/$OEM_FILE  $CUR_DIR/oem.bin
+
+    # prepare pib file
+    PIB_IMG=${BOARD_UPPER}
+
+    #BRM BSRM BSRM_CUS BRMT.
+    if [ "${BOARD_UPPER}" == "HTZD3201BSRM03" ] || [ "${BOARD_UPPER}" == "HTZD3201BRMT03" ]; then
+        PIB_IMG="EVB5202STA03"
+    fi
+
+    # HTZD + EVB.
+    if [ "${BOARD_UPPER}" == "HTZD3201CCO03" ] || [ "${BOARD_UPPER}" == "EVB3201CCO03" ] || [ "${BOARD_UPPER}" == "EVB3201CCO03_RFIN" ]; then
+        PIB_IMG=HTZDCCO
+    elif [ "${BOARD_UPPER}" == "HTZD3211IIC03" ] || [ "${BOARD_UPPER}" == "EVB3211IIC03" ]; then
+        PIB_IMG=HTZDIIC
+    elif [ "${BOARD_UPPER}" == "HTZD32113PS03" ] || [ "${BOARD_UPPER}" == "EVB32113PS03" ] ||
+         [ "${BOARD_UPPER}" == "HTZD3211STA03" ] || [ "${BOARD_UPPER}" == "EVB3211STA03" ] ||
+         [ "${BOARD_UPPER}" == "EVB3211STA03_RFIN" ] || [ "${BOARD_UPPER}" == "HTZD3211PT03" ]; then
+        PIB_IMG=HTZDSTA
+    fi
+
+    if [[ "${BOARD_UPPER}" == *"CKB03" ]]; then
+        # CKB.
+        PIB_IMG=HTZDSTA01_PIB
+    fi
+
+    if [[ "${BOARD_UPPER}" == "EVB32"* ]]; then
+        BOARD_UPPER=${BOARD_UPPER/EVB/HZEVB}
+    fi
+    BOARD_UPPER=${BOARD_UPPER/3201/}
+    BOARD_UPPER=${BOARD_UPPER/3211/}
+    BOARD_UPPER=${BOARD_UPPER/3031/}
+
+    # QJ + EVB.
+    if [ "${BOARD_UPPER}" == "QJ5580DCCO03" ] || [ "${BOARD_UPPER}" == "EVB5580DCCO03" ]; then
+        PIB_IMG=HTZDCCO
+    elif [ "${BOARD_UPPER}" == "QJ5582D3PS03" ] || [ "${BOARD_UPPER}" == "EVB5582D3PS03" ] || \
+         [ "${BOARD_UPPER}" == "QJ5582DSTA03" ] || [ "${BOARD_UPPER}" == "EVB5582DSTA03" ] || \
+         [ "${BOARD_UPPER}" == "QJ5582DIIC03" ]; then
+        PIB_IMG=HTZDSTA
+    fi
+    if [[ "${BOARD_UPPER}" == "EVB558"* ]]; then
+        BOARD_UPPER=${BOARD_UPPER/EVB/QJEVB}
+    fi
+    BOARD_UPPER=${BOARD_UPPER/5580D/}
+    BOARD_UPPER=${BOARD_UPPER/5582D/}
+
+    # FLX + EVB.
+    if [ "${BOARD_UPPER}" == "FLX6710CCO03" ] || [ "${BOARD_UPPER}" == "EVB6710CCO03" ]; then
+        PIB_IMG=HTZDCCO
+    elif [ "${BOARD_UPPER}" == "FLX67113PS03" ] || [ "${BOARD_UPPER}" == "EVB67113PS03" ] || \
+         [ "${BOARD_UPPER}" == "FLX6711IIC03" ] || \
+         [ "${BOARD_UPPER}" == "FLX6711STA03" ] || [ "${BOARD_UPPER}" == "EVB6711STA03" ]; then
+        PIB_IMG=HTZDSTA
+    fi
+    if [[ "${BOARD_UPPER}" == "EVB671"* ]]; then
+        BOARD_UPPER=${BOARD_UPPER/EVB/FLXEVB}
+    fi
+    BOARD_UPPER=${BOARD_UPPER/6710/}
+    BOARD_UPPER=${BOARD_UPPER/6711/}
+
+    # SPE.
+    if [ "${BOARD_UPPER}" == "SPE7303CCO03" ]; then
+        PIB_IMG=HTZDCCO
+    elif [ "${BOARD_UPPER}" == "SPE73013PS03" ] || [ "${BOARD_UPPER}" == "SPE7301IIC03" ] || \
+         [ "${BOARD_UPPER}" == "SPE7301STA03" ] ; then
+        PIB_IMG=HTZDSTA
+    fi
+    BOARD_UPPER=${BOARD_UPPER/7303/}
+    BOARD_UPPER=${BOARD_UPPER/7301/}
+
+    # GX.
+    if [ "${BOARD_UPPER}" == "GX2001CCO03" ]; then
+        PIB_IMG=HTZDCCO
+    elif [ "${BOARD_UPPER}" == "GX20113PS03" ] || [ "${BOARD_UPPER}" == "GX2011IIC03" ] || \
+         [ "${BOARD_UPPER}" == "GX2011STA03" ] ; then
+        PIB_IMG=HTZDSTA
+    fi
+    BOARD_UPPER=${BOARD_UPPER/2001/}
+    BOARD_UPPER=${BOARD_UPPER/2011/}
+
+    # DT.
+    if [ "${BOARD_UPPER}" == "DT0530CCO03" ]; then
+        PIB_IMG=HTZDCCO
+    elif [ "${BOARD_UPPER}" == "DT05313PS03" ] || [ "${BOARD_UPPER}" == "DT0531STA03" ] || \
+         [ "${BOARD_UPPER}" == "DT0531IIC03" ] ; then
+        PIB_IMG=HTZDSTA
+    fi
+    BOARD_UPPER=${BOARD_UPPER/0530/}
+    BOARD_UPPER=${BOARD_UPPER/0531/}
+
+    # YP.
+    if [ "${BOARD_UPPER}" == "YP8801CCO03" ]; then
+        PIB_IMG=HTZDCCO
+    elif [ "${BOARD_UPPER}" == "YP88113PS03" ] || [ "${BOARD_UPPER}" == "YP8811STA03" ] || \
+         [ "${BOARD_UPPER}" == "YP8811IIC03" ] ; then
+        PIB_IMG=HTZDSTA
+    fi
+    BOARD_UPPER=${BOARD_UPPER/8801/}
+    BOARD_UPPER=${BOARD_UPPER/8811/}
+
+    # GOLDFINGER.
+    if [ "${BOARD_UPPER}" == "GOLDFINGER_17P03" ]; then
+        if [ "${IMG_UPPER}" == "CCO" ]; then
+            PIB_IMG=${BOARD_UPPER/GOLDFINGER_17P/HTZD3201CCO}
+            BOARD_UPPER=${BOARD_UPPER/GOLDFINGER_17P/GOLDFINGER_17PCCO}
+        else
+            PIB_IMG=${BOARD_UPPER/GOLDFINGER_17P/HTZD3211STA}
+            BOARD_UPPER=${BOARD_UPPER/GOLDFINGER_17P/GOLDFINGER_17PSTA}
+        fi
+    fi
+
+    # STAMP.
+    if [ "${BOARD_UPPER}" == "STAMP03" ]; then
+        if [ "${IMG_UPPER}" == "CCO" ]; then
+            PIB_IMG=${BOARD_UPPER/STAMP/HTZD3201CCO}
+            BOARD_UPPER=${BOARD_UPPER/STAMP/STAMPCCO}
+        else
+            PIB_IMG=${BOARD_UPPER/STAMP/HTZD3211STA}
+            BOARD_UPPER=${BOARD_UPPER/STAMP/STAMPSTA}
+        fi
+    fi
+
+    # LEDC.
+    if [ "${BOARD_UPPER}" == "LEDC03" ]; then
+        if [ "${IMG_UPPER}" == "CCO" ]; then
+            PIB_IMG=${BOARD_UPPER/LEDC/HTZD3201CCO}
+            BOARD_UPPER=${BOARD_UPPER/LEDC/LEDCCCO}
+        else
+            PIB_IMG=${BOARD_UPPER/LEDC/HTZD3211STA}
+            BOARD_UPPER=${BOARD_UPPER/LEDC/LEDCSTA}
+        fi
+    fi
+
+    PIB_SRC_PATH=${TOP_DIR}/tools/pib/
+    cd ${PIB_SRC_PATH}
+
+    #kl3 pt board only need two general pib files
+    if [ "${BOARD_UPPER}" == "HTZDPT03" ]; then
+        PIB_FILE=HTZDSTA01_PIB.bin
+        LP_PIB_FILE=HTZDSTA01_LP_PIB.bin
+    else
+        PIB_FILE=`ls ${PIB_SRC_PATH} | grep "${PIB_IMG}" | grep "PIB"`
+        if [ "${IOT_SMART_BUILD}" == "0" ]; then
+            LP_PIB_FILE=`ls ${PIB_SRC_PATH} | grep "${PIB_IMG}" | grep "LP_PIB"`
+        fi
+    fi
+
+    cd -
+
+    #kl3 need to modify the FTM firmware name.
+    if [ "${IMG_UPPER}" == "FTM" ]; then
+        APP_UPPER="FTM"
+    fi
+
+    if [ ${IOT_SMART_BUILD} == 1 ]; then
+        if [ "${RUN_UPPER}" == "PSRAM" ]; then
+            sed -i "s,key_word=IOT-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-${RUN_UPPER}-${PSRAM_SIZE_STR}-${OPT_KEYWORD}${DB_RLS_FLAG}-,g" ${TMP_CFG_NAME}
+        else
+            sed -i "s,key_word=IOT-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-${OPT_KEYWORD}${DB_RLS_FLAG}-,g" ${TMP_CFG_NAME}
+        fi
+    else
+        if [ "${RUN_UPPER}" == "PSRAM" ]; then
+            sed -i "s,key_word=SG-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-${RUN_UPPER}-${PSRAM_SIZE_STR}-${OPT_KEYWORD},g" ${TMP_CFG_NAME}
+        elif [ "${RUN_UPPER}" == "UPGRADE" ]; then
+            if [ "$PSRAM_ENABLE_GEN" == "1" ]; then
+                sed -i "s,key_word=SG-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-${RUN_UPPER}-PSRAM-${PSRAM_SIZE_STR}-${OPT_KEYWORD},g" ${TMP_CFG_NAME}
+            else
+                sed -i "s,key_word=SG-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-${RUN_UPPER}-${OPT_KEYWORD},g" ${TMP_CFG_NAME}
+            fi
+        else
+            sed -i "s,key_word=SG-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-${OPT_KEYWORD},g" ${TMP_CFG_NAME}
+        fi
+    fi
+
+    if [  "${SIZE_UPPER}" == "4M" ]; then
+        sed -i "s,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-F-,g" ${TMP_CFG_NAME}
+    else
+        sed -i "s,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-T-,g" ${TMP_CFG_NAME}
+    fi
+
+    #define img_type
+    if [ "x${DUAL_ENABLE}" == "x1" ]; then
+        if [ "${APP_UPPER}" == "BRM" ]; then
+            sed -i "s/img_type=./img_type=7/" ${TMP_CFG_NAME}
+        elif [ "${APP_UPPER}" == "BSRM_CUS" ]; then
+            sed -i "s/img_type=./img_type=8/" ${TMP_CFG_NAME}
+        else
+            sed -i "s/img_type=./img_type=2/" ${TMP_CFG_NAME}
+        fi
+
+        if [ "${IMG_UPPER}" == "CKB" ]; then
+            sed -i "s/img_type=./img_type=6/" ${TMP_CFG_NAME}
+        fi
+
+        if [ "x${NEW_TYPE_CCO}" == "x1" ]; then
+            sed -i "s/img_type=./img_type=10/" ${TMP_CFG_NAME}
+        fi
+    else
+        if [ "${APP_UPPER}" == "BRM" ]; then
+            sed -i "s/img_type=./img_type=12/" ${TMP_CFG_NAME}
+        elif [ "${APP_UPPER}" == "BSRM_CUS" ]; then
+            sed -i "s/img_type=./img_type=13/" ${TMP_CFG_NAME}
+        else
+            sed -i "s/img_type=./img_type=11/" ${TMP_CFG_NAME}
+        fi
+
+        if [ "${IMG_UPPER}" == "CKB" ] || [ "x${NEW_TYPE_CCO}" == "x1" ]; then
+            echo "Something wrong!!!, stop generate firmware."
+            exit 1
+        fi
+    fi
+
+    set -o errexit
+    array=("${PIB_FILE// / }" "${LP_PIB_FILE// / }")
+    for var in ${array[@]}
+    do
+        echo "pib:${var}"
+        cp ${TOP_DIR}/tools/pib/$var $CUR_DIR/pib.bin
+        cp ${TOP_DIR}/tools/pib/$var ${OUT_PATH}
+
+        left=${var#*_}
+        append=""
+        while [ "$left"x != "PIB.bin"x ]; do
+            val=`echo $left | awk -F '_' '{print $1}'`
+            left=${left#*_}
+            append=$append$val"-"
+        done
+
+        cp ${TMP_CFG_NAME} ./tmp.cfg
+        if [ "${IMG_UPPER}" == "CCO" ]; then
+            if [ ${IOT_SMART_BUILD} == 1 ]; then
+                sed -i "s,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-1P-${append},g" ./tmp.cfg
+                sed -i "s/ht.bin/ht_1p.bin/g" ./tmp.cfg
+                ./ah -c ./tmp.cfg
+                #board-3201 need extra 3p-cco.
+                if [ "${chip_ver}" == "3201" ]; then
+                    sed -i "s/ht_1p.bin/ht.bin/g" ./tmp.cfg
+                    sed -i "s/-${BOARD_UPPER}-1P-/-${BOARD_UPPER}-3P-/" ./tmp.cfg
+                    ./ah -c ./tmp.cfg
+                fi
+            else
+                sed -i "s,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-${append},g" ./tmp.cfg
+                if [ "x${NEW_TYPE_CCO}" == "x1" ]; then
+                    sed -i "/key_word/s/CCO/NEW_TYPE_CCO/g" ./tmp.cfg
+                fi
+                ./ah -c ./tmp.cfg
+            fi
+        else
+            sed -i "s,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}-${append},g" ./tmp.cfg
+            ./ah -c ./tmp.cfg
+            #extra lp only pib upgrade file.
+            if [ "${BOARD_UPPER}X" == "HTZDSTA03X" ] || [ "${BOARD_UPPER}X" == "FPGASTA03X" ] || [ "${BOARD_UPPER}X" == "QJSTA03X" ] \
+            || [ "${BOARD_UPPER}X" == "FLXSTA03X" ] || [ "${BOARD_UPPER}X" == "SPESTA03X" ] || [ "${BOARD_UPPER}X" == "GXSTA03X" ] \
+            || [ "${BOARD_UPPER}X" == "DTSTA03X" ] || [ "${BOARD_UPPER}X" == "YPSTA03X" ]; then
+                left=${var#*_}
+                if [ "$left"x == "LP_PIB.bin"x ] && [ "${RUN_UPPER}X" == "UPGRADEX" ]; then
+                    sed -i "s/image_num=.*/image_num=0x1/g" ./tmp.cfg
+                    sed -i "s/${BOARD_UPPER}/${BOARD_UPPER}-ONLYPIB/g" ./tmp.cfg
+                    ./ah -c ./tmp.cfg
+                fi
+            fi
+        fi
+
+        rm ./tmp.cfg
+    done
+
+    rm ${TMP_CFG_NAME}
+
+    #prepare .out file.
+    if [ "x${CORE_TYPE_UPPER}" == "xAMPPLC" ]; then
+        if [ ! -d ${OUT_PATH}/amp_plc ]; then
+            mkdir -p ${OUT_PATH}/amp_plc
+        fi
+        cp ${TOP_DIR}/ap/.output/plc/lib/* ${OUT_PATH}/amp_plc
+        cp ${TOP_DIR}/sbl/.output/plc/lib/* ${OUT_PATH}/amp_plc
+        if [ "x${DUAL_ENABLE}" == "x1" ]; then
+            cp -f ${TOP_DIR}/bb_cpu/.output/plc/lib/* ${OUT_PATH}/amp_plc
+        fi
+
+        if [ -d "${TOP_DIR}/ap/.output/cus/lib" ]; then
+            if [ ! -d ${OUT_PATH}/amp_cus ]; then
+                mkdir -p ${OUT_PATH}/amp_cus
+            fi
+            cp ${TOP_DIR}/ap/.output/cus/lib/* ${OUT_PATH}/amp_cus
+        fi
+    else
+        if [ ! -d ${OUT_PATH}/plc_only ]; then
+            mkdir -p ${OUT_PATH}/plc_only
+        fi
+        cp ${TOP_DIR}/ap/.output/plc/lib/* ${OUT_PATH}/plc_only
+        cp ${TOP_DIR}/sbl/.output/plc/lib/* ${OUT_PATH}/plc_only
+        if [ "x${DUAL_ENABLE}" == "x1" ]; then
+            cp -f ${TOP_DIR}/bb_cpu/.output/plc/lib/* ${OUT_PATH}/plc_only
+        fi
+        if [ "x${SEC_CPU_ENABLE}" == "x1" ]; then
+            cp -f ${TOP_DIR}/sec_cpu/.output/plc/lib/* ${OUT_PATH}/plc_only
+        fi
+    fi
+
+    cp ${TOP_DIR}/tools/oem/${OEM_FILE} ${OUT_PATH}
+    mv ./${CHIP_ID}-${APP_UPPER}-* $BIN_PATH
+
+else
+
+    if [ "$SIZE_LOWER" == "" ]; then
+        BIN_PATH=${CUR_DIR}/customer/1M/${BOARD_LOWER}/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/1M/${BOARD_LOWER}/${IMG_LOWER}/out/
+    else
+        BIN_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/${BOARD_LOWER}/${IMG_LOWER}/bin/
+        OUT_PATH=${CUR_DIR}/customer/${SIZE_UPPER}/${BOARD_LOWER}/${IMG_LOWER}/out/
+    fi
+
+    mkdir -p $BIN_PATH
+    mkdir -p $OUT_PATH
+
+    if [ "${IMG_UPPER}" == "3PS" ] || [ "${IMG_UPPER}" == "CKB" ]; then
+        IMG_LOWER="sta"
+    fi
+
+    if [ "${product_line}" == "PLC" ] && [ "${target}" == "kunlun2" ]; then
+        CFG_DIR=${TOP_DIR}"/build/cfg2_plc"
+    else
+        CFG_DIR=${TOP_DIR}"/build/cfg"
+    fi
+
+    if [ "${RUN_UPPER}" == "UPGRADE" ]; then
+        if [ "${SIZE_UPPER}" != "" ]; then
+            if [ "$PSRAM_ENABLE_GEN" == "1" ] && [[ "${IMG_LOWER}" == "sta" || "${IMG_LOWER}" == "iic" ]]; then
+                CFG_NAME=${CFG_DIR}"/"${SIZE_LOWER}"_"${IMG_LOWER}"_upgrade_psram.cfg"
+            else
+                CFG_NAME=${CFG_DIR}"/"${SIZE_LOWER}"_"${IMG_LOWER}"_upgrade.cfg"
+            fi
+        else
+            CFG_NAME=${CFG_DIR}"/"${IMG_LOWER}"_upgrade.cfg"
+        fi
+    else
+        if [ ${IOT_SMART_BUILD} == 1 ]; then
+            if [ "${SIZE_UPPER}" == "2M" ] || [ "${SIZE_UPPER}" == "4M" ]; then
+                if [ "${RUN_UPPER}" == "PSRAM" ]; then
+                    CFG_NAME=${CFG_DIR}"/smart_"${SIZE_LOWER}"_"${IMG_LOWER}_psram.cfg
+                else
+                    CFG_NAME=${CFG_DIR}"/smart_"${SIZE_LOWER}"_"${IMG_LOWER}.cfg
+                fi
+            else
+                CFG_NAME=${CFG_DIR}"/smart_"${IMG_LOWER}.cfg
+            fi
+        else
+            if [ "${SIZE_UPPER}" != "" ]; then
+                 if [ "${RUN_UPPER}" == "PSRAM" ] && [[ "${IMG_LOWER}" == "sta" || "${IMG_LOWER}" == "iic" || "${IMG_LOWER}" == "ftm" ]]; then
+                     CFG_NAME=${CFG_DIR}"/"${SIZE_LOWER}"_"${IMG_LOWER}_psram.cfg
+                 else
+                     CFG_NAME=${CFG_DIR}"/"${SIZE_LOWER}"_"${IMG_LOWER}.cfg
+                 fi
+            else
+                 if [ "${RUN_UPPER}" == "PSRAM" ] && [ "${IMG_LOWER}" == "sta" ]; then
+                     CFG_NAME=${CFG_DIR}"/"${IMG_LOWER}_psram.cfg
+                 else
+                     CFG_NAME=${CFG_DIR}"/"${IMG_LOWER}.cfg
+                 fi
+            fi
+        fi
+    fi
+
+    if [ "${CHIP_VER_UPPER}" == "" ]; then
+        CHIP_VER_UPPER="1"
+    fi
+
+    TMP_CFG_NAME=${CFG_DIR}"/"${BOARD_LOWER}_${IMG_LOWER}_tmp.cfg
+    cp  ${CFG_NAME} ${TMP_CFG_NAME}
+
+    if [ ${IOT_SMART_BUILD} == 1 ]; then
+        if [ "${RUN_UPPER}" == "PSRAM" ]; then
+            sed -i "s,key_word=IOT-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-${RUN_UPPER}-${PSRAM_SIZE_STR}-${DB_RLS_FLAG}-,g" ${TMP_CFG_NAME}
+        else
+            sed -i "s,key_word=IOT-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-${DB_RLS_FLAG}-,g" ${TMP_CFG_NAME}
+        fi
+    else
+        if [ "${RUN_UPPER}" == "PSRAM" ]; then
+            sed -i "s,key_word=SG-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-${RUN_UPPER}-${PSRAM_SIZE_STR}-,g" ${TMP_CFG_NAME}
+        elif [ "${RUN_UPPER}" == "UPGRADE" ]; then
+            if [ "$PSRAM_ENABLE_GEN" == "1" ]; then
+                sed -i "s,key_word=SG-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-${RUN_UPPER}-PSRAM-${PSRAM_SIZE_STR}-,g" ${TMP_CFG_NAME}
+            else
+                sed -i "s,key_word=SG-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-${RUN_UPPER}-,g" ${TMP_CFG_NAME}
+            fi
+        else
+            if [ "$IMG_UPPER" == "CCO" ]; then
+                sed -i "s,key_word=SG-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-PSRAM-${PSRAM_SIZE_STR}-,g" ${TMP_CFG_NAME}
+            else
+                sed -i "s,key_word=SG-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-,g" ${TMP_CFG_NAME}
+            fi
+        fi
+    fi
+
+    #config scramble.
+    if [ "${BOARD_UPPER}" == "JSMT" ]; then
+        sed -i "s,encrypt_mode=0x0,encrypt_mode=0x3,g" ${TMP_CFG_NAME}
+        sed -i "s,encrypt_pattern=0x55,encrypt_pattern=0xaa,g" ${TMP_CFG_NAME}
+        sed -i "s,vendor_id=18516,vendor_id=19796,g" ${TMP_CFG_NAME}
+    fi
+
+    if [ "${BOARD_UPPER}" == "FLX" ]; then
+        sed -i "s,encrypt_mode=0x0,encrypt_mode=0x3,g" ${TMP_CFG_NAME}
+        sed -i "s,encrypt_pattern=0x55,encrypt_pattern=0x99,g" ${TMP_CFG_NAME}
+        sed -i "s,vendor_id=18516,vendor_id=20552,g" ${TMP_CFG_NAME}
+    fi
+
+    # prepare ht.bin
+    if [ "${IMG_UPPER}" == "IIC" ]  || [ "${IMG_UPPER}" == "3PS" ] || [ "${IMG_UPPER}" == "I3C" ]; then
+        HT_FILE="ht_sta.bin"
+    else
+        HT_FILE="ht_"${IMG_LOWER}".bin"
+    fi
+
+    if [ ${IOT_SMART_BUILD} == 1 ] && [ "${IMG_UPPER}" == "CCO" ]; then
+        cp $CUR_DIR/iot_ht_3p.bin $CUR_DIR/ht.bin
+        cp $CUR_DIR/iot_ht_1p.bin $CUR_DIR/ht_1p.bin
+    fi
+    if [ ! -f $CUR_DIR/ht.bin ]; then
+        cp ${TOP_DIR}/ap/.output/lib/${HT_FILE} $CUR_DIR/ht.bin
+    fi
+
+    sed -i "/img_type=./a layout_index=${FLASH_LAYOUT_INDEX}" ${TMP_CFG_NAME}
+
+    if [ "x${NEW_TYPE_CCO}" == "x1" ]; then
+        sed -i "s/img_type=./img_type=9/" ${TMP_CFG_NAME}
+    fi
+
+    #config lzma.
+    if [ "${MODE_UPPER}" == "LZMA" ]; then
+        ./elzma e $CUR_DIR/ht.bin $CUR_DIR/ht.bin.lzma
+        cp $CUR_DIR/ht.bin  $CUR_DIR/ht.bin.fw
+        mv  $CUR_DIR/ht.bin.lzma $CUR_DIR/ht.bin
+
+        if [ -f $CUR_DIR/ht_1p.bin ]; then
+            ./elzma e $CUR_DIR/ht_1p.bin $CUR_DIR/ht_1p.bin.lzma
+            cp $CUR_DIR/ht_1p.bin  $CUR_DIR/ht_1p.bin.fw
+            mv  $CUR_DIR/ht_1p.bin.lzma $CUR_DIR/ht_1p.bin
+        fi
+    fi
+
+    # prepare oem.bin
+    cp $TOP_DIR/sbl/.output/lib/kunlun_sbl.bin $CUR_DIR/sbl.bin
+    cp $TOP_DIR/mfgtool/ram/.output/lib/kl_ram.bin $CUR_DIR/ram.bin
+    cp $TOP_DIR/mfgtool/ram/.output/lib/kl_ram*.bin $CUR_DIR
+    cp $TOP_DIR/sp/boot/.output/lib/sp_fw.bin $CUR_DIR/sp.bin
+
+    if [ "${IMG_UPPER}" == "FTM" ] || [ "${IMG_UPPER}" == "CKB" ]; then
+        OEM_CFG=${BOARD_UPPER}"STA01_OEM.ini"
+        OEM_FILE=${BOARD_UPPER}"STA01_OEM.bin"
+    elif [ "${BOARD_UPPER}" == "STAMP_22P" ] || [ "${BOARD_UPPER}" == "SI301X_30P" ] \
+        || [ "${BOARD_UPPER}" == "GOLDFINGER_17P" ] \
+        || [ "${BOARD_UPPER}" == "MPPT" ] || [ "${BOARD_UPPER}" == "HTR" ]; then
+        #cco and sta share one oem for STAMP_22P  SI301X_30P  GOLDFINGER_17P MPPT HTR.
+        OEM_CFG=${BOARD_UPPER}"_OEM.ini"
+        OEM_FILE=${BOARD_UPPER}"_OEM.bin"
+    else
+        OEM_CFG=${BOARD_UPPER}${IMG_UPPER}"0"${CHIP_VER_UPPER}"_OEM.ini"
+        OEM_FILE=${BOARD_UPPER}${IMG_UPPER}"0"${CHIP_VER_UPPER}"_OEM.bin"
+    fi
+
+    cp $TOP_DIR/tools/oem/$OEM_CFG ./tmp_oem.ini
+    #set mid for iot board(cco and sta use same oem.ini)
+    if [ ${IOT_SMART_BUILD} == 1 ]; then
+        if [ "${IMG_UPPER}" == "CCO" ]; then
+            sed -i "s/mid.*/mid 1/g" ./tmp_oem.ini
+        elif [ "${IMG_UPPER}" == "STA" ]; then
+            sed -i "s/mid.*/mid 0/g" ./tmp_oem.ini
+        fi
+    fi
+    if [ "${RUN_UPPER}" != "UPGRADE" ]; then
+        ./oem_tool --input=./tmp_oem.ini --output=$TOP_DIR/tools/oem/$OEM_FILE
+    fi
+    rm ./tmp_oem.ini
+    cp $TOP_DIR/tools/oem/$OEM_FILE  $CUR_DIR/oem.bin
+
+    # prepare pib file
+    PIB_SRC_PATH=${TOP_DIR}/tools/pib/
+
+    if [ "${BOARD_UPPER}" == "FLX" ] || [ "${BOARD_UPPER}" == "STAMP_22P" ] \
+        || [ "${BOARD_UPPER}" == "SI301X_30P" ] || [ "${BOARD_UPPER}" == "LEDC_3P0" ] \
+        || [ "${BOARD_UPPER}" == "GOLDFINGER_17P" ] || [ "${BOARD_UPPER}" == "D2D" ] \
+        || [ "${BOARD_UPPER}" == "CCTT" ] || [ "${BOARD_UPPER}" == "MPPT" ] \
+        || [ "${BOARD_UPPER}" == "HTR" ]; then
+        BOARD_UPPER_PIB="HTZD"
+    else
+        BOARD_UPPER_PIB=${BOARD_UPPER}
+    fi
+
+    if [ "${IMG_UPPER}" == "FTM" ] || [ "${IMG_UPPER}" == "CKB" ]; then
+        PIB_IMG="STA"
+    else
+        PIB_IMG=${IMG_UPPER}
+        PIB_FILE=${BOARD_UPPER_PIB}${IMG_UPPER}"01_PIB.bin"
+    fi
+
+    if [ "${IMG_UPPER}" == "3PS" ]; then
+        PIB_IMG="STA"
+        PIB_FILE=${BOARD_UPPER_PIB}"STA01_PIB.bin"
+    fi
+
+    cd ${PIB_SRC_PATH}
+        if [ ${IOT_SMART_BUILD} == 1 ]; then
+            PIB_FILE=`ls ${PIB_SRC_PATH} | grep "${BOARD_UPPER_PIB}" | grep "${PIB_IMG}0${CHIP_VER_UPPER}_PIB"`
+            LP_PIB_FILE=`ls ${PIB_SRC_PATH} | grep "${BOARD_UPPER_PIB}" | grep "${PIB_IMG}0${CHIP_VER_UPPER}_LP_PIB"`
+        else
+            PIB_FILE=`ls ${PIB_SRC_PATH} | grep "${BOARD_UPPER_PIB}" | grep "${PIB_IMG}" | grep "PIB"`
+        fi
+    cd -
+
+    set -o errexit
+    array=("${PIB_FILE// / }" "${LP_PIB_FILE// / }")
+    for var in ${array[@]}
+    do
+        echo "pib:${var}"
+        cp ${TOP_DIR}/tools/pib/$var $CUR_DIR/pib.bin
+        cp ${TOP_DIR}/tools/pib/$var ${OUT_PATH}
+
+        left=${var#*_}
+        append=""
+        while [ "$left"x != "PIB.bin"x ]; do
+            val=`echo $left | awk -F '_' '{print $1}'`
+            left=${left#*_}
+            append=$append$val"-"
+        done
+
+        cp ${TMP_CFG_NAME} ./tmp.cfg
+
+        if [ "${IMG_UPPER}" == "CCO" ] && [ ${IOT_SMART_BUILD} == 1 ]; then
+            if [ "${SIZE_UPPER}" == "COMBO" ]; then
+                    sed -i "s,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-3P-${append},g" ./tmp.cfg
+            elif [  "${SIZE_UPPER}" == "4M" ]; then
+                    sed -i "s,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-3P-${append}F-,g" ./tmp.cfg
+            elif [  "${SIZE_UPPER}" == "2M" ]; then
+                    sed -i "s,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-3P-${append}T-,g" ./tmp.cfg
+            else
+                    sed -i "s,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-3P-${append}O-,g" ./tmp.cfg
+            fi
+        else
+            if [ "${SIZE_UPPER}" == "COMBO" ]; then
+                    sed -i "s,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-${append},g" ./tmp.cfg
+            elif [  "${SIZE_UPPER}" == "4M" ]; then
+                    sed -i "s,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-${append}F-,g" ./tmp.cfg
+            elif [  "${SIZE_UPPER}" == "2M" ]; then
+                    sed -i "s,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-${append}T-,g" ./tmp.cfg
+            else
+                    sed -i "s,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-,key_word=${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-${append}O-,g" ./tmp.cfg
+            fi
+        fi
+
+        if [ "${APP_UPPER}" == "BSRM" ]; then
+            sed -i "s/img_type=./img_type=3/" ./tmp.cfg
+        elif [ "${APP_UPPER}" == "BSRM_CUS" ]; then
+            sed -i "s/img_type=./img_type=4/" ./tmp.cfg
+        fi
+
+        if [ "x${NEW_TYPE_CCO}" == "x1" ]; then
+            sed -i "/key_word/s/CCO/NEW_TYPE_CCO/g" ./tmp.cfg
+        fi
+
+        #structure fw package.
+        ./ah -c ./tmp.cfg ${PSRAM_SIZE_PARAM}
+        if [ ${IOT_SMART_BUILD} == 1 ] && [ "${IMG_UPPER}" == "CCO" ]; then
+            sed -i "s/ht.bin/ht_1p.bin/g" ./tmp.cfg
+            sed -i "s/-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-3P-/-${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-1P-/" ./tmp.cfg
+            ./ah -c ./tmp.cfg ${PSRAM_SIZE_PARAM}
+        fi
+
+        #extra lp only pib upgrade file for kl1 htzd sta and kl3 fpga sta.
+        if [ "${BOARD_UPPER}${IMG_UPPER}X" == "HTZDSTAX" ] || [ "${BOARD_UPPER}${IMG_UPPER}X" == "FPGASTAX" ]; then
+            left=${var#*_}
+            if [ "$left"x == "LP_PIB.bin"x ] && [ "${RUN_UPPER}X" == "UPGRADEX" ]; then
+                sed -i "s/image_num=.*/image_num=0x1/g" ./tmp.cfg
+                sed -i "s/${BOARD_UPPER}${IMG_UPPER}../${BOARD_UPPER}${IMG_UPPER}0${CHIP_VER_UPPER}-ONLYPIB/g" ./tmp.cfg
+                ./ah -c ./tmp.cfg ${PSRAM_SIZE_PARAM}
+            fi
+        fi
+        rm ./tmp.cfg
+    done
+
+    rm ${TMP_CFG_NAME}
+    rm -f *.lds
+
+    #prepare .out file.
+    cp ${TOP_DIR}/sbl/.output/lib/* ${OUT_PATH}
+    cp ${TOP_DIR}/mfgtool/ram/.output/lib/* ${OUT_PATH}
+    cp ${TOP_DIR}/ap/.output/lib/* ${OUT_PATH}
+    cp ${TOP_DIR}/sp/boot/.output/lib/* ${OUT_PATH}
+    cp ${TOP_DIR}/tools/oem/${OEM_FILE} ${OUT_PATH}
+    mv ./${CHIP_ID}-${APP_UPPER}-${BOARD_UPPER}* $BIN_PATH
+
+    if [ ${IOT_SMART_BUILD} == 1 ]; then
+        if [ "${SIZE_LOWER}" == "" ]; then
+            SPECIAL_OUT_FD="${OUT_PATH}/../out_${CHIP_ID}_${APP_LOWER}_${BOARD_LOWER}_${IMG_LOWER}_${RUN_LOWER}_1m_${DB_LOWER}"
+        else
+            SPECIAL_OUT_FD="${OUT_PATH}/../out_${CHIP_ID}_${APP_LOWER}_${BOARD_LOWER}_${IMG_LOWER}_${RUN_LOWER}_${SIZE_LOWER}_${DB_LOWER}"
+        fi
+
+        if [ -d ${SPECIAL_OUT_FD} ]; then
+            rm -rf ${SPECIAL_OUT_FD}/*
+        fi
+        mv ${OUT_PATH} ${SPECIAL_OUT_FD}
+    fi
+fi
+
+echo "genarate image finished."
diff --git a/tools/kl2_gdbinit b/tools/kl2_gdbinit
new file mode 100644
index 0000000..b71940d
--- /dev/null
+++ b/tools/kl2_gdbinit
@@ -0,0 +1,1031 @@
+# These are some useful functions to add to your ~/.xt-gdbinit file
+# Standard gdb debug settings
+
+set history filename ~/.gdb_history
+set history save on
+set print pretty on
+set print object on
+set print vtbl on
+set pagination off
+set output-radix 16
+
+set $new=1
+
+define fpga_ver
+x 0xa6048
+end
+
+define dmem_usage
+end
+
+define ana_read_gain
+set *0x51c00180=1
+x/w 0x51c0017c
+set *0x51c00180=25
+x/w 0x51c0017c
+set *0x51c00180=41
+x/w 0x51c0017c
+end
+
+define ana_read
+set *0x51c00180=$arg0*4+1
+x/w 0x51c0017c
+x/b 0x51c00181
+end
+
+define ana_write
+set $addr = $arg0
+set $value = $arg1
+set $mask = $arg2
+set *0x51c00178=$mask
+set *0x51c00174=$value
+set *0x51c00180=$addr*4+3
+end
+
+define dump_all
+set $phy_reg=0x51800000
+set $phy_tx_reg=0x51900000
+set $phy_rxtd_reg=0x51a00000
+set $phy_rxfd_reg=0x51b00000
+set $phy_dfe_reg=0x51c00000
+set $mac_sys_reg=0x51000000
+set $rgf_rx_reg=0x51000c00
+set $ahb_reg=0x50000000
+set $apb_reg=0x44000000
+set $clk_reg=0x44009000
+set $start=0
+set $size=0x700/4
+set $end=$size
+set logging file phy_reg_dump.txt
+set logging on
+while $start < $end
+    x $phy_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file phy_tx_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $phy_tx_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file phy_rxtd_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $phy_rxtd_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file phy_rx_fd_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $phy_rxfd_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file phy_dfe_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $phy_dfe_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file mac_sys_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $mac_sys_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file rgf_rx_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $rgf_rx_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file ahb_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $ahb_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file apb_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $apb_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file clk_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $clk_reg+$start*4
+    set $start++
+end
+set logging off
+
+# reset fpga
+define resetfpga
+set *0x00100000=0x6f
+set *0x50000004=0xffffffff
+end
+
+# Run to appstart and load app
+define loadfw
+monitor soft_reset_halt
+disable_watchdog
+load
+set_cpu_freq_150
+set $sp = &__StackTop
+#set $pc = __Vectors[1]
+end
+
+#dump uart register
+define dump_uart
+p *(struct pl011_regs*)0x44001000
+p *(struct pl011_regs*)0x44005000
+end
+
+define uart_info
+p g_uart_info
+end
+
+#dump intc register
+define dump_intc
+p *(struct intc_regs*)0x44004000
+end
+
+#dump apb register
+define dump_apb
+p *(struct apb_regs*)0x44000000
+end
+
+#dump gptimer register
+define dump_gptmr
+p *(struct gpmtr_regs*)0x44003000
+end
+
+define cache_disable
+set *0x50000008 &= ~(0x18)
+set *0x50000004 |= (0x18)
+# disable dmc cache
+set *0x500000c8 = 0x000c0000
+# disable icache1 cache
+set *0x500000d8 = 0x000c0000
+end
+
+define map_flash_core
+set *0x4400703c |= 0x30
+set *0x44007098 |= 0x30
+set *0x44007038 |= 0x30
+set *0x44007064 |= 0x30
+set *0x44007068 |= 0x30
+set *0x44007040 |= 0x30
+
+set *0x4400001c |= 0x4
+
+set *0x44020010 |= 0x1000
+set *0x44020014 |= 0x1000
+set *0x44020018 |= 0x1000
+set *0x4402001c |= 0x1000
+end
+
+define map_flash_gpio_ver14
+# config pin 23-28 select FUNCTION0
+set *0x44007080=0
+set *0x44007084=0
+set *0x44007088=0
+set *0x4400708c=0
+set *0x44007090=0
+set *0x44007094=0
+# enable gpio matrix
+set *0x4400001c=0x4
+# config gpio matrix in
+# SFC INID 4-7 => GPIO 25-28
+set *0x44020010=25
+set *0x44020014=26
+set *0x44020018=27
+set *0x4402001c=28
+#config gpio matrix out
+# SFC OUTID 6-11 => GPIO 25-28
+set *0x4402045c=0x6
+set *0x44020460=0x7
+set *0x44020464=0x8
+set *0x44020468=0x9
+set *0x4402046c=10
+set *0x44020470=11
+end
+
+define map_uart2_gpio_mtx
+set *0x44007040=0
+set *0x44007044=0
+set *0x4400001c=0x4
+set *0x44020024=0x1000
+set *0x4402002c=0x8
+set *0x440200f8=15
+end
+define map_uart2_gpio_ver14
+set *0x44007040=0
+set *0x44007044=0
+set *0x4400001c |= 0x4
+set *0x44020024 |= 0x1000
+set *0x4402002c=0x8
+set *0x44020464=15
+end
+
+define map_psram_core_def
+set *0x4400001c |= 0x4
+set *0x44020000 |= 0x1000
+set *0x44020004 |= 0x1000
+set *0x44020008 |= 0x1000
+set *0x4402000c |= 0x1000
+end
+
+define set_cache_buffer_mode
+set *0x5000000c=0x10000
+set *0x50000008=0x00090010
+set *0x50000004=0xe
+end
+
+define cache_qspi_enable
+set *0x50000004=0x2001A
+set *0x50000008=0x90004
+# modify
+set *0x52000188=0x03057a75
+set *0x5200018c=0x100
+set *0x52000190=0x08180000
+# dual
+#set *0x52000188=0x3b057a75
+#set *0x5200018c=0x102
+#set *0x52000190=0x08180008
+#quad
+#set *0x52000188=0xeb057a75
+#set *0x5200018c=0x115
+#set *0x52000190=0x08060204
+
+set *0x52000194=0x100
+set *0x52000198=0x08000000
+set *0x5200019c=0x100
+set *0x520001a0=0x08000000
+set *0x520001a4=0x100
+set *0x520001a8=0x08000000
+#set *0x52000130=0x3
+# set cache quad
+#set *0x5200020c=0x102
+set *0x5200020c=0x1102
+set *0x52000208=0x35000000
+set *0x52000204=0x80000000
+
+set *0x50000004=0x20002
+set *0x50000008=0x9001C
+end
+
+define enable_emc
+set *0x62000004 |= 0x1
+set *0x62000008 |= 0x1
+set *0x62000008 &= ~(0x1)
+end
+
+define init_flash
+set *0x61000140=0x2000
+#set *0x61000188=0x03057a75
+#set *0x6100018c=0x100
+#set *0x61000190=0x08180000
+set *0x52000188=0xeb057a75
+set *0x5200018c=0x115
+set *0x52000190=0x08060204
+
+set *0x61000194=0x100
+set *0x61000198=0x08000000
+set *0x6100019c=0x100
+set *0x610001a0=0x08000000
+set *0x610001a4=0x100
+set *0x610001a8=0x08000000
+end
+
+define psram_qpi_mode
+set *0x6100020c=0x1102
+set *0x61000208=0x35000000
+set *0x61000204=0x80000000
+end
+
+define psram_spi_mode
+set *0x6100020c=0x1000
+set *0x61000208=0xf5000000
+set *0x61000204=0x80000000
+set *0x6100020c=0x0000
+end
+
+define space_cache
+set $val = $arg0
+set *0x5000008c = $val
+end
+
+define enable_cache
+set *0x50000008 |= 0x18
+set *0x50000004 &= ~(0x18)
+# dmc cache enable
+set *0x500000c8 |= 0x20000
+set *0x500000c8 &= ~0x140000
+# dmc cache enable
+set *0x500000d8 |= 0x20000
+set *0x500000d8 &= ~0x40000
+end
+
+define cache_cfg_qpi_ver14
+enable_emc
+#init_flash
+psram_qpi_mode
+enable_cache
+space_cache 0x44
+end
+
+define cache_cfg_spi_ver14
+enable_emc
+psram_spi_mode
+init_flash
+enable_cache
+space_cache 0x44
+end
+
+define loadfirmware
+monitor soft_reset_halt
+cache_disable
+map_flash_gpio_mtx
+map_psram_core_def
+map_uart2_gpio_mtx
+cache_qspi_enable
+load
+end
+
+define disable_watchdog
+set *0x44000004 |= 0x2000
+set *0x62000004 |= 0x10
+set *0x4400001c |= 0x1000
+set *0x90008000 |= 0x40000040
+set *0x4400e080 = 0x57444750
+set *0x4400e008 = 0
+set *0x62010080 = 0x57444750
+set *0x62010008 = 0
+set *0x4402a080 = 0x57444750
+set *0x4402a008 = 0
+set *0x90005080 = 0x57444750
+set *0x90005008 = 0
+set *0x90010080 = 0x57444750
+set *0x90010008 = 0
+set *0x4400e080 = 0
+set *0x62010080 = 0
+set *0x4402a080 = 0
+set *0x90005080 = 0
+set *0x90010080 = 0
+end
+
+define set_cpu_freq_150
+set *0x44009004=0x100
+set *0x44009000=0x1
+end
+
+define set_sfc_clk_75
+set *0x61000134=0x10
+end
+
+define set_smc_clk_75
+set *0x61000210=0x10
+end
+
+define load_ver14_qpi
+monitor soft_reset_halt
+disable_watchdog
+cache_disable
+if $new == 1
+    map_flash_core
+else
+    map_flash_gpio_ver14
+end
+map_psram_core_def
+#map_uart2_gpio_ver14
+cache_cfg_qpi_ver14
+load
+set_cpu_freq_150
+#set_sfc_clk_75
+#set_smc_clk_75
+while $a0 != 0x0
+    set $a0=0x0
+end
+end
+
+define load_ver14_spi
+monitor soft_reset_halt
+disable_watchdog
+cache_disable
+if $new == 1
+    map_flash_core
+else
+    map_flash_gpio_ver14
+end
+map_psram_core_def
+#map_uart2_gpio_ver14
+cache_cfg_spi_ver14
+load
+set $a0=0x0
+end
+
+define snapshot
+set *0x52000004=0x10101
+set *0x52000008=0x1e007
+end
+
+define map_jtag_gpio_mtx
+# config pin 00 - 04 select FUCNTION0
+set *0x44007024=0
+set *0x44007028=0
+set *0x4400702c=0
+set *0x44007030=0
+set *0x44007034=0
+# enable gpio matrix
+set *0x4400001c=0x4
+#in 44 - 47 => 00 01 03 04
+set *0x440200b0=00
+set *0x440200b4=01
+set *0x440200b8=03
+set *0x440200bc=04
+#out 2 => 66
+set *0x44020408=62
+end
+
+define map_jtag0_gpio
+#config pin 12-15 45 select FUNCTION0
+set *0x44007054 = 0
+set *0x44007058 = 0
+set *0x4400705c = 0
+set *0x44007060 = 0
+set *0x440070a0 = 0
+# enable gpio matrix
+set *0x4400001c=0x4
+#in 44 TMS 12
+set *0x440200b0=12
+#in 45 TCK 13
+set *0x440200b4=13
+#in 46 TDI 15
+set *0x440200b8=15
+#in 47 RST 45
+set *0x440200bc=45
+#out 14 => 62
+set *0x44020438=62
+end
+
+define print_dump_info
+    set trace-commands off
+    set $i = 0
+    while($i < 10)
+        set $dump = g_exception_dump.ra[$i]
+        if ($dump != 0x0)
+            p/a $dump
+        end
+        set $i = $i + 1
+    end
+    set trace-commands on
+end
+
+define map_dmc_psram
+    set *0x5522a03c = 0x15501
+end
+
+define map_emc_flash_kl2
+# 48 - 53
+set *0x440070c4 &= ~0x30
+set *0x440070c8 &= ~0x30
+set *0x440070cc &= ~0x30
+set *0x440070d0 &= ~0x30
+set *0x440070d4 &= ~0x30
+set *0x440070d8 &= ~0x30
+set *0x440070c4 |= 0x10
+set *0x440070c8 |= 0x10
+set *0x440070cc |= 0x10
+set *0x440070d0 |= 0x10
+set *0x440070d4 |= 0x10
+set *0x440070d8 |= 0x10
+set *0x440070dc |= 0x10
+
+set *0x4400001c |= 0x4
+
+set *0x44020010 |= 0x1000
+set *0x44020014 |= 0x1000
+set *0x44020018 |= 0x1000
+set *0x4402001c |= 0x1000
+end
+
+# reg_write reg lowest_bit bit_num value
+define reg_write
+    set $reg = $arg0
+    set $low = $arg1
+    set $cnt = $arg2
+    set $value = $arg3
+    set $tmp = *(uint32_t *)$reg
+    set $mask = 0
+    while($cnt > 0)
+        set $cnt--
+        set $mask = (($mask << 1) + 1)
+    end
+    set $mask = $mask << $low
+    set $tmp &= ~$mask
+    set $tmp |= (($value << $low) & $mask)
+    set *(uint32_t *)$reg = $tmp
+end
+
+define ddr_op_clear
+    reg_write 0x5522811c 8 1 0
+    reg_write 0x5522811c 0 2 0
+    reg_write 0x5522801c 8 1 0
+    reg_write 0x55228004 6 2 3
+    reg_write 0x55228004 6 2 0
+end
+
+define ddr_soft_read
+    set trace-commands off
+    set $instr = $arg0
+    set $addr = $arg1
+    # step 1
+    reg_write 0x5522811c 9 1 0
+    reg_write 0x5522811c 0 2 0
+    reg_write 0x55228004 6 2 3
+    reg_write 0x55228004 6 2 0
+    echo step1 finish\n
+
+    #step 2
+    reg_write 0x5522801c 8 1 0
+    reg_write 0x5522801c 0 8 $instr
+    reg_write 0x55228020 0 32 $addr
+    reg_write 0x5522811c 8 1 0
+    reg_write 0x5522801c 8 1 1
+    echo step2 finish\n
+
+    # step 3
+    reg_write 0x5522811c 8 1 1
+    reg_write 0x5522811c 1 1 1
+    reg_write 0x5522811c 0 1 1
+    echo step3 finish\n
+
+    #step 4
+    echo \nrdata0:\n
+    x/x 0x55228108
+    echo \nrdata1:\n
+    x/x 0x55228120
+
+    # reset clear
+    ddr_op_clear
+    set trace-commands on
+end
+
+define ddr_soft_write
+    set trace-commands off
+    set $instr = $arg0
+    set $addr = $arg1
+    set $latency = $arg2
+    set $wdata0 = $arg3
+    set $wdata1 = $arg4
+    # step 1
+    reg_write 0x5522811c 9 1 1
+    reg_write 0x5522811c 0 2 0
+    reg_write 0x55228004 6 2 3
+    reg_write 0x55228004 6 2 0
+    reg_write 0x55228010 16 4 $latency
+    echo step1 finish\n
+
+    # step 2
+    reg_write 0x5522801c 8 1 0
+    reg_write 0x5522801c 0 8 $instr
+    reg_write 0x55228020 0 32 $addr
+    reg_write 0x5522811c 8 1 0
+    reg_write 0x5522801c 8 1 1
+    echo step2 finish\n
+
+    # step 3
+    reg_write 0x5522811c 8 1 1
+    reg_write 0x55228100 0 32 $wdata0
+    reg_write 0x55228104 28 1 0
+    if ($instr == 0xc0)
+        reg_write 0x55228104 0 24 0x6db69a
+    else
+        reg_write 0x55228104 0 24 0x69a69a
+    end
+    reg_write 0x5522811c 3 1 1
+    reg_write 0x5522811c 8 1 1
+    reg_write 0x55228100 0 32 $wdata1
+    reg_write 0x55228104 28 1 0
+    if ($instr == 0xc0)
+        reg_write 0x55228104 0 24 0x6db6db
+    else
+        reg_write 0x55228104 0 24 0x69a69a
+    end
+    reg_write 0x5522811c 3 1 1
+    echo step3 finish\n
+
+    # step 4
+    reg_write 0x55228100 0 32 0
+    reg_write 0x55228104 28 1 0
+    reg_write 0x55228104 0 24 0xaebaeb
+    reg_write 0x5522811c 3 1 1
+    reg_write 0x5522811c 3 1 1
+    reg_write 0x5522811c 1 1 1
+    echo step4 finish\n
+
+    # reset clear
+    ddr_op_clear
+    set trace-commands on
+end
+
+define ddr_mode_x8
+    reg_write 0x55228008 1 2 2
+    reg_write 0x55228008 4 4 6
+    reg_write 0x55228014 0 4 6
+end
+
+define ddr_mode_x16
+    reg_write 0x55228008 1 2 1
+    reg_write 0x55228014 0 4 5
+end
+
+define ddr_cfg
+    # set ddr mode
+    ddr_mode_x16
+    # set ddr reg0 to 0x01
+    #ddr_soft_write 0xc0 0 1 0x01010101 0x01010101
+    # set ddr reg4 to 0x0
+    #ddr_soft_write 0xc0 4 1 0x0 0x0
+    # set ddr read/write latency
+    #reg_write 0x55228010 16 8 0x33
+    # set ddr echo chip size, size = 2^n Mb, now 16MB
+    reg_write 0x55228008 4 4 7
+    # set dmc echo chip size, size = 2^n Mb, now 16MB
+    reg_write 0x5522a008 8 4 7
+
+    #ddr_op_clear
+end
+
+define ddr_cfg_x8
+    # set ddr mode
+    ddr_mode_x8
+    # set dmc echo chip size, size = 2^n Mb, now 8MB
+    reg_write 0x5522a008 8 4 6
+end
+
+define ddr_dmc_mode
+set *0x5000000c |= 0x180000
+set *0x500000d8 |= 0x100000
+end
+
+define load_kl2_psram
+#monitor soft_reset_halt
+cache_disable
+map_dmc_psram
+map_emc_flash_kl2
+cache_cfg_qpi_ver14
+space_cache 0x1004
+load
+while $a0 != 0x0
+    set $a0=0x0
+end
+end
+
+define load_kl2_ddr
+#monitor soft_reset_halt
+cache_disable
+ddr_cfg
+map_emc_flash_kl2
+enable_cache
+space_cache 0x1004
+ddr_dmc_mode
+load
+while $a0 != 0x0
+    set $a0=0x0
+end
+end
+
+define load_kl2_ddr_x8
+#monitor soft_reset_halt
+cache_disable
+ddr_cfg_x8
+map_emc_flash_kl2
+enable_cache
+space_cache 0x0804
+ddr_dmc_mode
+load
+while $a0 != 0x0
+    set $a0=0x0
+end
+end
+
+define load_kl2_a10
+#monitor soft_reset_halt
+cache_disable
+ddr_cfg
+enable_cache
+space_cache 0x4008
+ddr_dmc_mode
+load
+while $a0 != 0x0
+    set $a0=0x0
+end
+end
+
+define load_kl2_a10_x8
+#monitor soft_reset_halt
+cache_disable
+ddr_cfg_x8
+enable_cache
+space_cache 0x4008
+ddr_dmc_mode
+load
+while $a0 != 0x0
+    set $a0=0x0
+end
+end
+
+define k3d_enable
+#ahb ai enable
+set *0x50000008 |= 0x80
+set *0x50000004 |= 0x80
+set *0x50000004 &= ~0x80
+#ai k3d ena
+set *0x70000000 |= 0x1
+
+#ahb dvp enable
+set *0x50000008 |= 0x800
+set *0x50000004 |= 0x800
+set *0x50000004 &= ~0x800
+end
+
+define k3d_disable
+set *0x70000000 &= ~0x1
+end
+
+define dvp_enable
+set *0x50000008 |= 0x800
+set *0x50000004 |= 0x800
+set *0x50000004 &= ~0x800
+end
+
+define dvp_ram_mode
+set *0x52300000 = 0x21f21
+set *0x52300054 = 0x3
+set *0x52300004 = 0x1cc
+set *0x52300008 = 0x1
+set *0x52300024 = 720
+set *0x52300028 = 1280
+set *0x52300060 = 0x1
+set *0x52300058 = 0x72105
+set *0x523000b4 = 0x72ff
+set *0x52300100 = 0x1
+end
+
+define dvp_ram_mode_no_force
+set *0x52300000 = 0x0
+set *0x52300054 = 0x3
+set *0x52300004 = 0x1cc
+set *0x52300008 = 0x1
+set *0x52300024 = 720
+set *0x52300028 = 1280
+set *0x52300060 = 0x1
+set *0x52300058 = 0x72105
+set *0x523000b4 = 0x72ff
+set *0x52300100 = 0x1
+set *0x52300000 = 0x01f01
+end
+
+define dvp_ram_mode_crop
+# dvp data to psram address
+set *0x52300018 = 0x00000
+set *0x5230010c = 0x100000
+set *0x52300000 = 0x0
+set *0x52300054 = 0x0
+set *0x52300004 = 0x11cc
+
+#set *0x52300008 = 0x1
+#set *0x5230000c = 0xff
+#set *0x52300010 = 0x02cf04ff
+set *0x52300008 = 0x1
+set *0x5230000c = 0x1
+set *0x52300010 = 0x02cf0400
+
+set *0x52300014 = 0x04000000
+set *0x52300024 = 720
+set *0x52300028 = 1280
+set *0x52300000 = 0x01f33
+end
+
+define dvp_ram_mode_no_crop
+# dvp data to psram address
+set *0x52300018 = 0x00000
+set *0x5230010c = 0x1000000
+set *0x52300000 = 0x0
+set *0x52300054 = 0x0
+set *0x52300004 = 0x11cc
+set *0x52300008 = 0x1
+set *0x5230000c = 0x1
+set *0x52300010 = 0x02cf0400
+set *0x52300014 = 0x05000000
+set *0x52300024 = 720
+set *0x52300028 = 1280
+set *0x52300000 = 0x01f31
+end
+
+define dvp_bina_mode
+set *0x52300000 = 0x021f21
+set *0x52300054 = 0x5
+set *0x52300004 = 0x1cc
+set *0x52300008 = 0x1
+#set *0x52300024 = 720
+#set *0x52300028 = 1280
+set *0x52300024 = 720
+set *0x52300028 = 1024
+set *0x52300060 = 0x1
+set *0x52300058 = 0x72105
+set *0x523000b4 = 0x72ff
+end
+
+define dvp_bina_mode_no_force
+set *0x52300000 = 0x0
+set *0x52300054 = 0x5
+set *0x52300004 = 0x1cc
+set *0x52300008 = 0x1
+set *0x52300024 = 720
+set *0x52300028 = 1280
+set *0x52300060 = 0x1
+set *0x52300058 = 0x72105
+set *0x523000b4 = 0x72ff
+set *0x52300000 = 0x001f21
+end
+
+define dvp_bina_mode_auto
+set *0x52300000 = 0x0
+set *0x52300054 = 0x7
+set *0x52300004 = 0x11cc
+set *0x52300008 = 0x1
+set *0x52300024 = 720
+set *0x52300028 = 1280
+set *0x52300060 = 0x1
+set *0x52300058 = 0x72105
+set *0x523000b4 = 0x72ff
+set *0x52300000 = 0x001f21
+end
+# crop 1024 * 720
+define dvp_bina_mode_crop
+set *0x52300000 = 0x0
+# dvp data to psram address
+set *0x52300018 = 0x10000
+set *0x52300054 = 0x7
+set *0x52300004 = 0x11cc
+set *0x52300008 = 0x1
+set *0x5230000c = 0xff
+#set *0x5230000c = 0x0
+set *0x52300010 = 0x02d004ff
+#set *0x52300010 = 0x02d00400
+set *0x52300024 = 720
+#set *0x52300028 = 1280
+set *0x52300028 = 1024
+set *0x52300060 = 0x1
+set *0x52300058 = 0x72105
+set *0x523000b4 = 0x72ff
+set *0x52300000 = 0x001f23
+end
+
+define fake_data
+set $addr = $arg0
+set $size = $arg1
+set $offset = $arg2
+set $i = 0
+while $size > 0
+    set *$addr =  $i
+    set $i = $i + 0x11111111 + $offset
+    if ($i == 0xffffffff)
+        set $i = 0x0
+    end
+    set $addr = $addr + 4
+    set $size = $size - 1
+end
+end
+
+define ai_glb_config
+reg_write 0x7000000c 0 20 0x38400
+reg_write 0x70000010 0 16 0x5760
+reg_write 0x70000014 0 17 0x0
+reg_write 0x70000018 0 17 0x1680
+reg_write 0x7000001c 0 32 0
+set *0x70000008 = 0x4005
+set *0x70000000 = 0x4531
+end
+
+define clear_cache
+set *0x5000000c |= 0xc
+end
+
+define cpu0_enable
+set $start_pc = $arg0
+set *0x5000004c = $start_pc
+set *0x50000008 |= 0x10000
+set *0x50000004 |= 0x10000
+set *0x50000004 &= ~0x10000
+end
+
+define cpu2_enable
+set $start_pc = $arg0
+set *0x500000b0 = $start_pc
+set *0x50000008 |= 0x20000
+set *0x50000004 |= 0x20000
+set *0x50000004 &= ~0x20000
+end
+
+define vm
+target remote localhost:3333
+disable_watchdog
+end
+
+define kl2_vm
+vm
+monitor reset halt
+kill
+shell sleep 0.001
+vm
+end
+
+define kl2_target_remote
+
+target remote $arg0
+monitor reset halt
+kill
+shell sleep 0.001
+target remote $arg0
+disable_watchdog
+end
+
+define bpll_calibration
+reg_write 0x90008074 13 2 0
+reg_write 0x90008074 6 1 1
+reg_write 0x900080f8 12 1 1
+reg_write 0x900080f8 12 1 0
+reg_write 0x90008078 0 7 100
+reg_write 0x90008074 6 1 0
+reg_write 0x90008074 6 1 0
+reg_write 0x90008074 13 1 1
+set $done = 1
+while($done == 1)
+    set $i = *(uint32_t *) 0x90008078
+    set $i = $i & 0x20000
+    if $i > 0
+        set $done = 0
+    end
+end
+end
+
+define set_level_to_1p1
+set *0x90008000 = 0x80
+reg_write 0x9000f034 24 1 0
+reg_write 0x9000f034 26 4 9
+end
+
+define switch_to_150m
+set_level_to_1p1
+# enable ana_reg
+set *0x44000004 |= 0x40000
+reg_write 0x4401101c 17 8 36
+bpll_calibration
+set *0x44009000 = 0x4165
+end
+
+define set_level_to_1p2
+set *0x90008000 = 0x80
+reg_write 0x9000f034 24 1 0
+reg_write 0x9000f034 26 4 14
+end
+
+define switch_to_200m
+set_level_to_1p2
+# enable ana_reg
+set *0x44000004 |= 0x40000
+reg_write 0x4401101c 17 8 48
+bpll_calibration
+set *0x44009000 = 0x4165
+end
+
diff --git a/tools/kl3_gdbinit b/tools/kl3_gdbinit
new file mode 100644
index 0000000..96d6d33
--- /dev/null
+++ b/tools/kl3_gdbinit
@@ -0,0 +1,172 @@
+# These are some useful functions to add to your ~/.xt-gdbinit file
+# Standard gdb debug settings
+
+set history filename ~/.gdb_history
+set history save on
+set print pretty on
+set print object on
+set print vtbl on
+set pagination off
+set output-radix 16
+
+set $new=1
+
+######## mtd function ########
+define emc_enable
+# disable emc
+set *(0x50019000 + 0x08) &= ~(1 << 11)
+# reset emc
+set *(0x50019000 + 0x04) |= (1 << 11)
+set *(0x50019000 + 0x04) &= ~(1 << 11)
+# enable emc
+set *(0x50019000 + 0x08) |= (1 << 11)
+end
+
+define mtd_io_share_disable
+end
+
+define mtd_io_share_enable
+end
+
+define smc_init
+# set qspi mode
+set *(0x58080200 + 0x0c) = 0x01201102
+set *(0x58080200 + 0x3c) |= 0x11
+# enable smc and cfg clk
+set *(0x58080200 + 0x10) |= 0x10
+end
+
+define psram_init
+# enter qpi mode
+set *(0x58080200 + 0x08) = (0x35 << 24) + 0x00
+set *(0x58080200 + 0x04) &= 0xFE00FFFC
+set *(0x58080200 + 0x0c) &= ~(1 << 12)
+set *(0x58080200 + 0x04) |= (1 << 31)
+end
+
+define sfc_init
+end
+
+define flash_init
+end
+
+define cache_enable
+# cache init step: disable, reset, enable, set space
+# icache0
+set *(0x50019000 + 0x04) |= (1 << 4)
+set *(0x50019000 + 0x04) &= ~(1 << 4)
+set *(0x50019000 + 0x08) |= (1 << 4)
+set *(0x58000000 + 0x44) = 0x0804
+while !((*(0x58000000 + 0x00)) & (1 << 6))
+end
+# icache1
+set *(0x50019000 + 0x04) |= (1 << 5)
+set *(0x50019000 + 0x04) &= ~(1 << 5)
+set *(0x50019000 + 0x08) |= (1 << 5)
+set *(0x58000000 + 0x44) = 0x0804
+while !((*(0x58010000 + 0x00)) & (1 << 6))
+end
+# icache2
+set *(0x50019000 + 0x04) |= (1 << 6)
+set *(0x50019000 + 0x04) &= ~(1 << 6)
+set *(0x50019000 + 0x08) |= (1 << 6)
+set *(0x58000000 + 0x44) = 0x0804
+while !((*(0x58020000 + 0x00)) & (1 << 6))
+end
+# dcache0
+set *(0x50019000 + 0x04) |= (1 << 7)
+set *(0x50019000 + 0x04) &= ~(1 << 7)
+set *(0x50019000 + 0x08) |= (1 << 7)
+set *(0x58030000 + 0x44) = 0x0804
+while !((*(0x58030000 + 0x00)) & (1 << 6))
+end
+# dcache1
+set *(0x50019000 + 0x04) |= (1 << 8)
+set *(0x50019000 + 0x04) &= ~(1 << 8)
+set *(0x50019000 + 0x08) |= (1 << 8)
+set *(0x58030000 + 0x44) = 0x0804
+while !((*(0x58040000 + 0x00)) & (1 << 6))
+end
+end
+
+define mtd_init
+emc_enable
+psram_init
+smc_init
+cache_enable
+sfc_init
+flash_init
+end
+
+define disable_watchdog
+set *0x40040080 = 0x57444750
+set *0x40040008 = 0
+set *0x40040080 = 0
+set *0x40041080 = 0x57444750
+set *0x40041008 = 0
+set *0x40041080 = 0
+set *0x40042080 = 0x57444750
+set *0x40042008 = 0
+set *0x40042080 = 0
+end
+
+define disable_tick_int
+# disable tick int0
+set *0x40030054 = 0x0
+# clear tick int0
+set *0x40030058 = 0x1
+# disable tick int1
+set *0x40031054 = 0x0
+# clear tick int1
+set *0x40031058 = 0x1
+# disable tick int2
+set *0x40032054 = 0x0
+# clear tick int2
+set *0x40032058 = 0x1
+end
+
+define reset_chip
+set *0x4000003c = 0x125A3410
+set *0x40000038 = 0x1
+end
+
+define ram_test
+    set $offset = 0
+    set $addr = 0
+    set $value = 0
+    set $value_r = 0
+    while $offset < 0x70000
+        set $addr = 0x10000000 + $offset * 4
+        #p $addr
+        set $value = ($offset << 8) | $offset
+        #p $value
+        set *$addr = $value
+        set $value_r = *(uint32_t *)$addr
+        #p *(uint32_t *)$addr
+        #p $value_r
+        if $value_r != $value
+            p $value
+            p $value_r
+        end
+        set $offset = $offset + 4
+        if $offset % 0x100 == 0
+            p $offset
+        end
+    end
+end
+
+######## system function ########
+
+define vm
+target remote localhost:3333
+disable_tick_int
+disable_watchdog
+end
+
+define vm1
+target remote localhost:3334
+disable_tick_int
+disable_watchdog
+end
+
+
diff --git a/tools/kl3_multi_gdbinit b/tools/kl3_multi_gdbinit
new file mode 100644
index 0000000..3ab3b1b
--- /dev/null
+++ b/tools/kl3_multi_gdbinit
@@ -0,0 +1,146 @@
+# These are some useful functions to add to your ~/.xt-gdbinit file
+# Standard gdb debug settings
+
+set history filename ~/.gdb_history
+set history save on
+set print pretty on
+set print object on
+set print vtbl on
+set pagination off
+set output-radix 16
+
+set $new=1
+
+######## mtd function ########
+define emc_enable
+# disable emc
+set *(0x50019000 + 0x08) &= ~(1 << 11)
+# reset emc
+set *(0x50019000 + 0x04) |= (1 << 11)
+set *(0x50019000 + 0x04) &= ~(1 << 11)
+# enable emc
+set *(0x50019000 + 0x08) |= (1 << 11)
+end
+
+define mtd_io_share_disable
+end
+
+define mtd_io_share_enable
+end
+
+define smc_init
+# set qspi mode
+set *(0x58080200 + 0x0c) = 0x01201102
+set *(0x58080200 + 0x3c) |= 0x11
+# enable smc and cfg clk
+set *(0x58080200 + 0x10) |= 0x10
+end
+
+define psram_init
+# enter qpi mode
+set *(0x58080200 + 0x08) = (0x35 << 24) + 0x00
+set *(0x58080200 + 0x04) &= 0xFE00FFFC
+set *(0x58080200 + 0x0c) &= ~(1 << 12)
+set *(0x58080200 + 0x04) |= (1 << 31)
+end
+
+define sfc_init
+end
+
+define flash_init
+end
+
+define cache_enable
+# cache init step: disable, reset, enable, set space
+# icache0
+set *(0x50019000 + 0x04) |= (1 << 4)
+set *(0x50019000 + 0x04) &= ~(1 << 4)
+set *(0x50019000 + 0x08) |= (1 << 4)
+set *(0x58000000 + 0x44) = 0x0404
+while !((*(0x58000000 + 0x00)) & (1 << 6))
+end
+# icache1
+set *(0x50019000 + 0x04) |= (1 << 5)
+set *(0x50019000 + 0x04) &= ~(1 << 5)
+set *(0x50019000 + 0x08) |= (1 << 5)
+set *(0x58000000 + 0x44) = 0x0404
+while !((*(0x58010000 + 0x00)) & (1 << 6))
+end
+# icache2
+set *(0x50019000 + 0x04) |= (1 << 6)
+set *(0x50019000 + 0x04) &= ~(1 << 6)
+set *(0x50019000 + 0x08) |= (1 << 6)
+set *(0x58000000 + 0x44) = 0x0404
+while !((*(0x58020000 + 0x00)) & (1 << 6))
+end
+# dcache0
+set *(0x50019000 + 0x04) |= (1 << 7)
+set *(0x50019000 + 0x04) &= ~(1 << 7)
+set *(0x50019000 + 0x08) |= (1 << 7)
+set *(0x58030000 + 0x44) = 0x0404
+while !((*(0x58030000 + 0x00)) & (1 << 6))
+end
+# dcache1
+set *(0x50019000 + 0x04) |= (1 << 8)
+set *(0x50019000 + 0x04) &= ~(1 << 8)
+set *(0x50019000 + 0x08) |= (1 << 8)
+set *(0x58030000 + 0x44) = 0x0404
+while !((*(0x58040000 + 0x00)) & (1 << 6))
+end
+end
+
+define mtd_init
+emc_enable
+psram_init
+smc_init
+cache_enable
+sfc_init
+flash_init
+end
+
+define disable_watchdog
+set *0x40040080 = 0x57444750
+set *0x40040008 = 0
+set *0x40040080 = 0
+set *0x40041080 = 0x57444750
+set *0x40041008 = 0
+set *0x40041080 = 0
+set *0x40042080 = 0x57444750
+set *0x40042008 = 0
+set *0x40042080 = 0
+end
+
+define disable_tick_int
+# disable tick int0
+set *0x40030054 = 0x0
+# clear tick int0
+set *0x40030058 = 0x1
+# disable tick int1
+set *0x40031054 = 0x0
+# clear tick int1
+set *0x40031058 = 0x1
+# disable tick int2
+set *0x40032054 = 0x0
+# clear tick int2
+set *0x40032058 = 0x1
+end
+
+######## system function ########
+
+define vm
+target extended-remote:3333
+disable_tick_int
+disable_watchdog
+end
+
+define vm1
+target extended-remote:3334
+disable_tick_int
+disable_watchdog
+end
+define vm2
+target extended-remote:3335
+disable_tick_int
+disable_watchdog
+end
+
diff --git a/tools/kl3_multi_riscv.cfg b/tools/kl3_multi_riscv.cfg
new file mode 100644
index 0000000..9b02e31
--- /dev/null
+++ b/tools/kl3_multi_riscv.cfg
@@ -0,0 +1,99 @@
+#source [file join [file dirname [string map {"\\" "/"} [info script]]] openocd_jtag.cfg]
+source [find /opt/riscv/share/openocd/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+adapter_khz     1000
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5
+
+gdb_port 3333
+
+proc disable_watchdog {} {
+    echo "Disabling watchdog..."
+    halt
+    mww 0x40040080 0x57444750
+    mww 0x40040008 0
+    mww 0x40040080 0
+    mww 0x40041080 0x57444750
+    mww 0x40041008 0
+    mww 0x40041080 0
+    mww 0x40042080 0x57444750
+    mww 0x40042008 0
+    mww 0x40042080 0	
+	
+	
+#    mww 0x012c0080 0x57444750
+#    mww 0x012c0008 0
+#    mww 0x012c0080 0
+#    mww 0x108C0080 0x57444750
+#    mww 0x108C0008 0
+#    mww 0x108C0080 0
+#    mww 0x10B00080 0x57444750
+#    mww 0x10B00008 0
+#    mww 0x10B00080 0
+#    mww 0x208C0080 0x57444750
+#    mww 0x208C0008 0
+#    mww 0x208C0080 0
+#    mww 0x0194F080 0x57444750
+#    mww 0x0194F008 0
+#    mww 0x0194F080 0
+}
+
+# mrw: "memory read word", returns value of $reg
+proc mrw {reg} {
+    set value ""
+    mem2array value 32 $reg 1
+    return $value(0)
+}
+
+# core 0
+set _TARGETNAME0 $_CHIPNAME.cpu0
+target create $_TARGETNAME0 riscv -chain-position $_CHIPNAME.cpu -coreid 0
+$_TARGETNAME0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+$_TARGETNAME0 configure -event reset-init disable_watchdog
+$_TARGETNAME0 configure -event examine-end {
+    echo "start core 1 & core 2"
+    halt
+    # core 1 & 2 clk
+#    mww 0x10800010 0x00000900
+    mww 0x50019400 0x00000006
+
+    # core 1 start pc
+    mww 0x10030000 0x0000006F
+    mww 0x50019024 0x10030000
+    # core 2 start pc
+    mww 0x10060000 0x0000006F
+    mww 0x50019028 0x10060000
+    # core 1 enable
+    mww 0x50019004 [expr [mrw 0x50019004] & 0x2]
+    # core 2 enable
+    mww 0x50019004 [expr [mrw 0x50019004] & 0x4]	
+	
+#    # core 1 & 2 clk
+#    mww 0x10800010 0x00000900
+#
+#    # core 1 start pc
+#    mww 0x1023EFF0 0x0000006F
+#    mww 0x10800040 0x1023EFF0
+#    # core 2 start pc
+#    mww 0x1023EFF4 0x0000006F
+#    mww 0x10800044 0x1023EFF4
+#    # core 1 enable
+#    mww 0x01200160 [expr [mrw 0x01200160] | 0x20]
+#    # core 2 enable
+#    mww 0x01200160 [expr [mrw 0x01200160] | 0x40]
+
+    sleep 100
+}
+
+# core 1
+set _TARGETNAME1 $_CHIPNAME.cpu1
+target create $_TARGETNAME1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
+$_TARGETNAME1 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+$_TARGETNAME1 configure -event examine-end halt
+
+# core 2
+set _TARGETNAME2 $_CHIPNAME.cpu2
+target create $_TARGETNAME2 riscv -chain-position $_CHIPNAME.cpu -coreid 2
+$_TARGETNAME2 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+$_TARGETNAME2 configure -event examine-end halt
diff --git a/tools/kl3_riscv.cfg b/tools/kl3_riscv.cfg
new file mode 100644
index 0000000..ab786a4
--- /dev/null
+++ b/tools/kl3_riscv.cfg
@@ -0,0 +1,25 @@
+adapter_khz     10000
+
+source [find /opt/riscv/share/openocd/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+#$_TARGETNAME configure -rtos auto
+
+#flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+  #Wait for the reset stretcher
+  #It will work without this, but
+  #will incur lots of delays for later commands.
+  sleep 1500
+}
+halt
+#flash protect 0 64 last off
diff --git a/tools/kunlun_cm3.cfg b/tools/kunlun_cm3.cfg
new file mode 100644
index 0000000..5969d50
--- /dev/null
+++ b/tools/kunlun_cm3.cfg
@@ -0,0 +1,82 @@
+# This is an STM32F4 discovery board with a single STM32F407VGT6 chip.
+# http://www.st.com/internet/evalboard/product/252419.jsp
+
+source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME kunlun
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0090
+      # Section 38.6.3 - corresponds to Cortex-M4 r0p1
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+$_TARGETNAME configure -rtos auto
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+adapter_khz 1000
+
+adapter_nsrst_assert_width 100
+adapter_nsrst_delay 100
+if {[using_jtag]} {
+        jtag_ntrst_assert_width 100
+        jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+#reset_config trst_and_srst
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+        # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
+        #              DBG_STANDBY | DBG_STOP | DBG_SLEEP
+        mmw 0xE0042004 0x00000307 0
+	mmw 0xE000ED08 0x00000000 0
+}
+
+$_TARGETNAME configure -event trace-config {
+        # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+        # change this value accordingly to configure trace pins
+        # assignment
+        mmw 0xE0042004 0x00000020 0
+}
diff --git a/tools/kunlun_cm3_norts.cfg b/tools/kunlun_cm3_norts.cfg
new file mode 100644
index 0000000..4d2db54
--- /dev/null
+++ b/tools/kunlun_cm3_norts.cfg
@@ -0,0 +1,82 @@
+# This is an STM32F4 discovery board with a single STM32F407VGT6 chip.
+# http://www.st.com/internet/evalboard/product/252419.jsp
+
+source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME kunlun
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0090
+      # Section 38.6.3 - corresponds to Cortex-M4 r0p1
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+#$_TARGETNAME configure -rtos auto
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+adapter_khz 1000
+
+adapter_nsrst_assert_width 100
+adapter_nsrst_delay 100
+if {[using_jtag]} {
+        jtag_ntrst_assert_width 100
+        jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+#reset_config trst_and_srst
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+        # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
+        #              DBG_STANDBY | DBG_STOP | DBG_SLEEP
+        mmw 0xE0042004 0x00000307 0
+	mmw 0xE000ED08 0x00000000 0
+}
+
+$_TARGETNAME configure -event trace-config {
+        # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+        # change this value accordingly to configure trace pins
+        # assignment
+        mmw 0xE0042004 0x00000020 0
+}
diff --git a/tools/kunlun_gdbinit b/tools/kunlun_gdbinit
new file mode 100644
index 0000000..698defd
--- /dev/null
+++ b/tools/kunlun_gdbinit
@@ -0,0 +1,463 @@
+# These are some useful functions to add to your ~/.xt-gdbinit file
+# Standard gdb debug settings
+
+set history filename ~/.gdb_history
+set history save on
+set print pretty on
+set print object on
+set print vtbl on
+set pagination off
+set output-radix 16
+
+set $new=1
+
+define fpga_ver
+x 0xa6048
+end
+
+define dmem_usage
+end
+
+define ana_read_gain
+set *0x51c00180=1
+x/w 0x51c0017c
+set *0x51c00180=25
+x/w 0x51c0017c
+set *0x51c00180=41
+x/w 0x51c0017c
+end
+
+define ana_read
+set *0x51c00180=$arg0*4+1
+x/w 0x51c0017c
+x/b 0x51c00181
+end
+
+define ana_write
+set $addr = $arg0
+set $value = $arg1
+set $mask = $arg2
+set *0x51c00178=$mask
+set *0x51c00174=$value
+set *0x51c00180=$addr*4+3
+end
+
+define dump_all
+set $phy_reg=0x51800000
+set $phy_tx_reg=0x51900000
+set $phy_rxtd_reg=0x51a00000
+set $phy_rxfd_reg=0x51b00000
+set $phy_dfe_reg=0x51c00000
+set $mac_sys_reg=0x51000000
+set $rgf_rx_reg=0x51000c00
+set $ahb_reg=0x50000000
+set $apb_reg=0x44000000
+set $clk_reg=0x44009000
+set $start=0
+set $size=0x700/4
+set $end=$size
+set logging file phy_reg_dump.txt
+set logging on
+while $start < $end
+    x $phy_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file phy_tx_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $phy_tx_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file phy_rxtd_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $phy_rxtd_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file phy_rx_fd_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $phy_rxfd_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file phy_dfe_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $phy_dfe_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file mac_sys_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $mac_sys_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file rgf_rx_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $rgf_rx_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file ahb_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $ahb_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file apb_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $apb_reg+$start*4
+    set $start++
+end
+set logging off
+
+set logging file clk_reg_dump.txt
+set logging on
+set $start=0
+while $start < $end
+    x $clk_reg+$start*4
+    set $start++
+end
+set logging off
+end
+
+define vm
+target remote localhost:3333
+end
+
+# reset fpga
+define resetfpga
+set *0x00100000=0x6f
+set *0x50000004=0xffffffff
+end
+
+# Run to appstart and load app
+define loadfw
+monitor soft_reset_halt
+disable_watchdog
+load
+set $sp = &__StackTop
+#set $pc = __Vectors[1]
+end
+
+#dump uart register
+define dump_uart
+p *(struct pl011_regs*)0x44001000
+p *(struct pl011_regs*)0x44005000
+end
+
+define uart_info
+p g_uart_info
+end
+
+#dump intc register
+define dump_intc
+p *(struct intc_regs*)0x44004000
+end
+
+#dump apb register
+define dump_apb
+p *(struct apb_regs*)0x44000000
+end
+
+#dump gptimer register
+define dump_gptmr
+p *(struct gpmtr_regs*)0x44003000
+end
+
+define cache_disable
+set *0x50000008 &= ~(0x18)
+set *0x50000004 |= (0x18)
+end
+
+define map_flash_core
+set *0x4400703c |= 0x30
+set *0x44007098 |= 0x30
+set *0x44007038 |= 0x30
+set *0x44007064 |= 0x30
+set *0x44007068 |= 0x30
+set *0x44007040 |= 0x30
+
+set *0x4400001c |= 0x4
+
+set *0x44020010 |= 0x1000
+set *0x44020014 |= 0x1000
+set *0x44020018 |= 0x1000
+set *0x4402001c |= 0x1000
+end
+
+define map_flash_gpio_ver14
+# config pin 23-28 select FUNCTION0
+set *0x44007080=0
+set *0x44007084=0
+set *0x44007088=0
+set *0x4400708c=0
+set *0x44007090=0
+set *0x44007094=0
+# enable gpio matrix
+set *0x4400001c=0x4
+# config gpio matrix in
+# SFC INID 4-7 => GPIO 25-28
+set *0x44020010=25
+set *0x44020014=26
+set *0x44020018=27
+set *0x4402001c=28
+#config gpio matrix out
+# SFC OUTID 6-11 => GPIO 25-28
+set *0x4402045c=0x6
+set *0x44020460=0x7
+set *0x44020464=0x8
+set *0x44020468=0x9
+set *0x4402046c=10
+set *0x44020470=11
+end
+
+define map_uart2_gpio_mtx
+set *0x44007040=0
+set *0x44007044=0
+set *0x4400001c=0x4
+set *0x44020024=0x1000
+set *0x4402002c=0x8
+set *0x440200f8=15
+end
+
+define map_uart2_gpio_ver14
+set *0x44007040=0
+set *0x44007044=0
+set *0x4400001c |= 0x4
+set *0x44020024 |= 0x1000
+set *0x4402002c=0x8
+set *0x44020464=15
+end
+
+define map_psram_core_def
+set *0x4400001c |= 0x4
+set *0x44020000 |= 0x1000
+set *0x44020004 |= 0x1000
+set *0x44020008 |= 0x1000
+set *0x4402000c |= 0x1000
+end
+
+define set_cache_buffer_mode
+set *0x5000000c=0x10000
+set *0x50000008=0x00090010
+set *0x50000004=0xe
+end
+
+define cache_qspi_enable
+set *0x50000004=0x2001A
+set *0x50000008=0x90004
+# modify
+set *0x52000188=0x03057a75
+set *0x5200018c=0x100
+set *0x52000190=0x08180000
+# dual
+#set *0x52000188=0x3b057a75
+#set *0x5200018c=0x102
+#set *0x52000190=0x08180008
+#quad
+#set *0x52000188=0xeb057a75
+#set *0x5200018c=0x115
+#set *0x52000190=0x08060204
+
+set *0x52000194=0x100
+set *0x52000198=0x08000000
+set *0x5200019c=0x100
+set *0x520001a0=0x08000000
+set *0x520001a4=0x100
+set *0x520001a8=0x08000000
+#set *0x52000130=0x3
+# set cache quad
+#set *0x5200020c=0x102
+set *0x5200020c=0x1102
+set *0x52000208=0x35000000
+set *0x52000204=0x80000000
+
+set *0x50000004=0x20002
+set *0x50000008=0x9001C
+end
+
+define enable_emc
+set *0x62000004 |= 0x1
+set *0x62000008 |= 0x1
+set *0x62000008 &= ~(0x1)
+end
+
+define init_flash
+set *0x61000140=0x2000
+#set *0x61000188=0x03057a75
+#set *0x6100018c=0x100
+#set *0x61000190=0x08180000
+set *0x52000188=0xeb057a75
+set *0x5200018c=0x115
+set *0x52000190=0x08060204
+
+set *0x61000194=0x100
+set *0x61000198=0x08000000
+set *0x6100019c=0x100
+set *0x610001a0=0x08000000
+set *0x610001a4=0x100
+set *0x610001a8=0x08000000
+end
+
+define psram_qpi_mode
+set *0x6100020c=0x1102
+set *0x61000208=0x35000000
+set *0x61000204=0x80000000
+end
+
+define psram_spi_mode
+set *0x6100020c=0x1000
+set *0x61000208=0xf5000000
+set *0x61000204=0x80000000
+set *0x6100020c=0x0000
+end
+
+define enable_cache
+set *0x50000008 |= 0x18
+set *0x50000004 &= ~(0x18)
+set $space = *0x5000008c
+if $space != 0x44
+    set *0x5000008c=0x44
+end
+end
+
+define cache_cfg_qpi_ver14
+enable_emc
+init_flash
+psram_qpi_mode
+enable_cache
+end
+
+define cache_cfg_spi_ver14
+enable_emc
+psram_spi_mode
+init_flash
+enable_cache
+end
+
+define loadfirmware
+monitor soft_reset_halt
+cache_disable
+map_flash_gpio_mtx
+map_psram_core_def
+map_uart2_gpio_mtx
+cache_qspi_enable
+load
+end
+
+define disable_watchdog
+set *0x62010008=0x0
+set *0x4400e008=0x0
+end
+
+define set_cpu_freq_150
+set *0x44009004=0x100
+set *0x44009000=0x1
+end
+
+define set_sfc_clk_75
+set *0x61000134=0x10
+end
+
+define set_smc_clk_75
+set *0x61000210=0x10
+end
+
+define load_ver14_qpi
+monitor soft_reset_halt
+disable_watchdog
+cache_disable
+if $new == 1
+    map_flash_core
+else
+    map_flash_gpio_ver14
+end
+map_psram_core_def
+#map_uart2_gpio_ver14
+cache_cfg_qpi_ver14
+load
+set_cpu_freq_150
+#set_sfc_clk_75
+#set_smc_clk_75
+while $a0 != 0x0
+    set $a0=0x0
+end
+end
+
+define load_ver14_spi
+monitor soft_reset_halt
+disable_watchdog
+cache_disable
+if $new == 1
+    map_flash_core
+else
+    map_flash_gpio_ver14
+end
+map_psram_core_def
+#map_uart2_gpio_ver14
+cache_cfg_spi_ver14
+load
+set $a0=0x0
+end
+
+define snapshot
+set *0x52000004=0x10101
+set *0x52000008=0x1e007
+end
+
+define map_jtag_gpio_mtx
+# config pin 00 - 04 select FUCNTION0
+set *0x44007024=0
+set *0x44007028=0
+set *0x4400702c=0
+set *0x44007030=0
+set *0x44007034=0
+# enable gpio matrix
+set *0x4400001c=0x4
+#in 44 - 47 => 00 01 03 04
+set *0x440200b0=00
+set *0x440200b4=01
+set *0x440200b8=03
+set *0x440200bc=04
+#out 2 => 66
+set *0x44020408=62
+end
+
+define print_dump_info
+    set trace-commands off
+    set $i = 0
+    while($i < 10)
+        set $dump = g_exception_dump.ra[$i]
+        if ($dump != 0x0)
+            p/a $dump
+        end
+        set $i = $i + 1
+    end
+    set trace-commands on
+end
diff --git a/tools/kunlun_multi_riscv.cfg b/tools/kunlun_multi_riscv.cfg
new file mode 100644
index 0000000..1d630ec
--- /dev/null
+++ b/tools/kunlun_multi_riscv.cfg
@@ -0,0 +1,35 @@
+adapter_khz     10000
+
+source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+set _TARGETNAME0 $_CHIPNAME.cpu0
+target create $_TARGETNAME0 riscv -chain-position $_TARGETNAME -coreid 0
+$_TARGETNAME0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+set _TARGETNAME1 $_CHIPNAME.cpu1
+target create $_TARGETNAME1 riscv -chain-position $_TARGETNAME -coreid 1
+$_TARGETNAME1 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+set _TARGETNAME1 $_CHIPNAME.cpu2
+target create $_TARGETNAME1 riscv -chain-position $_TARGETNAME -coreid 2
+$_TARGETNAME1 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+#$_TARGETNAME configure -rtos auto
+
+#flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+  #Wait for the reset stretcher
+  #It will work without this, but
+  #will incur lots of delays for later commands.
+  sleep 1500
+}
+halt
+#flash protect 0 64 last off
diff --git a/tools/kunlun_riscv.cfg b/tools/kunlun_riscv.cfg
new file mode 100644
index 0000000..debd348
--- /dev/null
+++ b/tools/kunlun_riscv.cfg
@@ -0,0 +1,24 @@
+adapter_khz     10000
+
+source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+#$_TARGETNAME configure -rtos auto
+
+#flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+  #Wait for the reset stretcher
+  #It will work without this, but
+  #will incur lots of delays for later commands.
+  sleep 1500
+}
+halt
+#flash protect 0 64 last off
diff --git a/tools/kunlun_riscv_rtos.cfg b/tools/kunlun_riscv_rtos.cfg
new file mode 100644
index 0000000..9e5f932
--- /dev/null
+++ b/tools/kunlun_riscv_rtos.cfg
@@ -0,0 +1,24 @@
+adapter_khz     10000
+
+source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+$_TARGETNAME configure -rtos auto
+
+#flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+  #Wait for the reset stretcher
+  #It will work without this, but
+  #will incur lots of delays for later commands.
+  sleep 1500
+}
+halt
+#flash protect 0 64 last off
diff --git a/tools/mac_cfg/MAC Test Tool Specification.docx b/tools/mac_cfg/MAC Test Tool Specification.docx
new file mode 100644
index 0000000..8d0b757
Binary files /dev/null and b/tools/mac_cfg/MAC Test Tool Specification.docx differ
diff --git a/tools/mac_cfg/cmd_cfg.txt b/tools/mac_cfg/cmd_cfg.txt
new file mode 100644
index 0000000..deae7d0
--- /dev/null
+++ b/tools/mac_cfg/cmd_cfg.txt
@@ -0,0 +1,87 @@
+cmd_cfg:
+{
+    uint8_t  ping_cmd_num = 3;
+    uint32_t  ping_bcn_period = 60;      //unit 1ms
+    
+    uint8_t  pong_cmd_num = 3;
+    uint32_t  pong_bcn_period = 60;      //unit 1ms
+    
+    uint8_t  st_flag0 = 0;
+    uint8_t  r_flag0 = 0;
+    uint8_t  r_start_flag0 = 0;
+    uint8_t  r_end_flag0 = 0;
+    uint8_t  phase0 = 2;
+    uint8_t  idle_bit0 = 0;
+    uint8_t  req_int0 = 0;
+    uint8_t  rx_rate_mode0 = 0;
+    uint8_t  narrow_band0 = 0;
+    uint32_t enable_bitmap0 = 1;
+    uint32_t start_time0 = 0;
+    uint32_t end_time0 = 20;
+    
+    uint8_t  st_flag1 = 0;
+    uint8_t  r_flag1 = 0;
+    uint8_t  r_start_flag1 = 0;
+    uint8_t  r_end_flag1 = 0;
+    uint8_t  phase1 = 2;
+    uint8_t  idle_bit1 = 0;
+    uint8_t  req_int1 = 0;
+    uint8_t  rx_rate_mode1 = 0;
+    uint8_t  narrow_band1 = 0;
+    uint32_t enable_bitmap1 = 2;
+    uint32_t start_time1 = 0;
+    uint32_t end_time1 = 40;
+    
+    uint8_t  st_flag2 = 0;
+    uint8_t  r_flag2 = 0;
+    uint8_t  r_start_flag2 = 0;
+    uint8_t  r_end_flag2 = 0;
+    uint8_t  phase2 = 2;
+    uint8_t  idle_bit2 = 0;
+    uint8_t  req_int2 = 0;
+    uint8_t  rx_rate_mode2 = 0;
+    uint8_t  narrow_band2 = 0;
+    uint32_t enable_bitmap2 = 4;
+    uint32_t start_time2 = 0;
+    uint32_t end_time2 = 60;
+    
+    uint8_t  st_flag3 = 0;
+    uint8_t  r_flag3 = 0;
+    uint8_t  r_start_flag3 = 0;
+    uint8_t  r_end_flag3 = 0;
+    uint8_t  phase3 = 2;
+    uint8_t  idle_bit3 = 0;
+    uint8_t  req_int3 = 0;
+    uint8_t  rx_rate_mode3 = 0;
+    uint8_t  narrow_band3 = 0;
+    uint32_t enable_bitmap3 = 1;
+    uint32_t start_time3 = 0;
+    uint32_t end_time3 = 20;
+    
+    uint8_t  st_flag4 = 0;
+    uint8_t  r_flag4 = 0;
+    uint8_t  r_start_flag4 = 0;
+    uint8_t  r_end_flag4 = 0;
+    uint8_t  phase4 = 2;
+    uint8_t  idle_bit4 = 0;
+    uint8_t  req_int4 = 0;
+    uint8_t  rx_rate_mode4 = 0;
+    uint8_t  narrow_band4 = 0;
+    uint32_t enable_bitmap4 = 2;
+    uint32_t start_time4 = 0;
+    uint32_t end_time4 = 40;
+    
+    uint8_t  st_flag5 = 0;
+    uint8_t  r_flag5 = 0;
+    uint8_t  r_start_flag5 = 0;
+    uint8_t  r_end_flag5 = 0;
+    uint8_t  phase5 = 2;
+    uint8_t  idle_bit5 = 0;
+    uint8_t  req_int5 = 0;
+    uint8_t  rx_rate_mode5 = 0;
+    uint8_t  narrow_band5 = 0;
+    uint32_t enable_bitmap5 = 4;
+    uint32_t start_time5 = 0;
+    uint32_t end_time5 = 60;
+    
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/crc_cfg.txt b/tools/mac_cfg/crc_cfg.txt
new file mode 100644
index 0000000..9014251
--- /dev/null
+++ b/tools/mac_cfg/crc_cfg.txt
@@ -0,0 +1,12 @@
+
+crc_cfg:
+{
+    uint8_t  fccs_by_sw = 0; //1:by sw, 0:by hw
+    uint8_t  pb_crc_by_sw = 0;
+    uint8_t  bcn_crc_by_sw = 1;
+    
+    //is verify by sw
+    uint8_t is_verify_fc = 0;
+    uint8_t is_verify_pb = 0;
+    uint8_t is_verify_payload = 0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/hwq_cfg.txt b/tools/mac_cfg/hwq_cfg.txt
new file mode 100644
index 0000000..4194bac
--- /dev/null
+++ b/tools/mac_cfg/hwq_cfg.txt
@@ -0,0 +1,25 @@
+
+hwq_cfg:
+{
+    uint8_t tx_mode=0x11; // plc mode and debug q mode
+
+    uint8_t hwqid0=0;
+    uint8_t qtype0=0;
+    uint8_t qcap0=0;
+
+    uint8_t hwqid1=1;
+    uint8_t qtype1=0;
+    uint8_t qcap1=0;
+
+    uint8_t hwqid2=2;
+    uint8_t qtype2=0;
+    uint8_t qcap2=0;
+
+    uint8_t hwqid3=3;
+    uint8_t qtype3=0;
+    uint8_t qcap3=0;
+
+    uint8_t hwqid4=4;
+    uint8_t qtype4=0;
+    uint8_t qcap4=0;
+}
diff --git a/tools/mac_cfg/ping_tput.txt b/tools/mac_cfg/ping_tput.txt
new file mode 100644
index 0000000..4ae56ec
--- /dev/null
+++ b/tools/mac_cfg/ping_tput.txt
@@ -0,0 +1,10 @@
+typedef struct _mac_ping_tput{
+    uint32_t stei = 0x0001;
+    uint32_t dtei = 0x0002;
+    uint32_t nid = 0x1;
+    uint8_t tmi = 0;
+    uint8_t ext_tmi=0;
+    uint8_t pb_num =1;
+    uint32_t cont = 4;
+    uint8_t ping_or_tput = 0; //0:ping  1:tput
+}mac_ping_tput_t;
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_cert.txt b/tools/mac_cfg/pkt_cfg_cert.txt
new file mode 100644
index 0000000..e24286f
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_cert.txt
@@ -0,0 +1,24 @@
+
+pkt_cfg:
+{
+    uint8_t  proto=0;
+    uint8_t  qid=0;
+    uint8_t  bcast=1;
+    uint8_t  delimiter_type=0;
+    uint32_t nid=0x0;
+    uint32_t dtei=0xfff;
+    uint32_t stei=0x00;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=0;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt = 0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_gp0.txt b/tools/mac_cfg/pkt_cfg_gp0.txt
new file mode 100755
index 0000000..6241954
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_gp0.txt
@@ -0,0 +1,24 @@
+
+pkt_cfg:
+{
+    uint8_t  proto=1;
+    uint8_t  qid=0;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=0;
+    uint32_t snid=0xb;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=2;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt=0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_gp1.txt b/tools/mac_cfg/pkt_cfg_gp1.txt
new file mode 100755
index 0000000..b812321
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_gp1.txt
@@ -0,0 +1,24 @@
+
+pkt_cfg:
+{
+    uint8_t  proto=1;
+    uint8_t  qid=1;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=1;
+    uint32_t snid=0xb;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt=0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_gp2.txt b/tools/mac_cfg/pkt_cfg_gp2.txt
new file mode 100755
index 0000000..5e493aa
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_gp2.txt
@@ -0,0 +1,24 @@
+
+pkt_cfg:
+{
+    uint8_t  proto=1;
+    uint8_t  qid=2;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=1;
+    uint32_t snid=0xb;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt=0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_gp3.txt b/tools/mac_cfg/pkt_cfg_gp3.txt
new file mode 100755
index 0000000..a2fdd1c
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_gp3.txt
@@ -0,0 +1,24 @@
+
+pkt_cfg:
+{
+    uint8_t  proto=1;
+    uint8_t  qid=3;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=1;
+    uint32_t snid=0xb;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt=0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_gp4.txt b/tools/mac_cfg/pkt_cfg_gp4.txt
new file mode 100755
index 0000000..1c25b93
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_gp4.txt
@@ -0,0 +1,24 @@
+
+pkt_cfg:
+{
+    uint8_t  proto=1;
+    uint8_t  qid=4;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=1;
+    uint32_t snid=0xb;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt=0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_sg0.txt b/tools/mac_cfg/pkt_cfg_sg0.txt
new file mode 100755
index 0000000..0cf5319
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_sg0.txt
@@ -0,0 +1,24 @@
+
+pkt_cfg:
+{
+    uint8_t  proto=0;
+    uint8_t  qid=0;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=1;
+    uint32_t nid=0x1;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt = 0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_sg1.txt b/tools/mac_cfg/pkt_cfg_sg1.txt
new file mode 100755
index 0000000..9cf8d46
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_sg1.txt
@@ -0,0 +1,25 @@
+
+
+pkt_cfg:
+{
+    uint8_t  proto=0;
+    uint8_t  qid=1;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=1;
+    uint32_t nid=0x1;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt = 0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_sg2.txt b/tools/mac_cfg/pkt_cfg_sg2.txt
new file mode 100755
index 0000000..c11e2c2
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_sg2.txt
@@ -0,0 +1,24 @@
+
+pkt_cfg:
+{
+    uint8_t  proto=0;
+    uint8_t  qid=2;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=1;
+    uint32_t nid=0x1;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt = 0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_sg3.txt b/tools/mac_cfg/pkt_cfg_sg3.txt
new file mode 100755
index 0000000..907da7d
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_sg3.txt
@@ -0,0 +1,24 @@
+
+pkt_cfg:
+{
+    uint8_t  proto=0;
+    uint8_t  qid=3;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=1;
+    uint32_t nid=0x1;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt = 0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_sg4.txt b/tools/mac_cfg/pkt_cfg_sg4.txt
new file mode 100755
index 0000000..0476d61
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_sg4.txt
@@ -0,0 +1,24 @@
+
+pkt_cfg:
+{
+    uint8_t  proto=0;
+    uint8_t  qid=4;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=1;
+    uint32_t nid=0x1;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt = 0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_spg0.txt b/tools/mac_cfg/pkt_cfg_spg0.txt
new file mode 100755
index 0000000..9428b50
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_spg0.txt
@@ -0,0 +1,24 @@
+
+pkt_cfg:
+{
+    uint8_t  proto=3;
+    uint8_t  qid=0;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=1;
+    uint32_t nid=0x1;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt = 0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_spg1.txt b/tools/mac_cfg/pkt_cfg_spg1.txt
new file mode 100755
index 0000000..b526021
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_spg1.txt
@@ -0,0 +1,25 @@
+
+
+pkt_cfg:
+{
+    uint8_t  proto=3;
+    uint8_t  qid=1;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=1;
+    uint32_t nid=0x1;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt = 0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_spg2.txt b/tools/mac_cfg/pkt_cfg_spg2.txt
new file mode 100755
index 0000000..39a6033
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_spg2.txt
@@ -0,0 +1,24 @@
+
+pkt_cfg:
+{
+    uint8_t  proto=3;
+    uint8_t  qid=2;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=1;
+    uint32_t nid=0x1;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt = 0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_spg3.txt b/tools/mac_cfg/pkt_cfg_spg3.txt
new file mode 100755
index 0000000..56d3a1c
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_spg3.txt
@@ -0,0 +1,24 @@
+
+pkt_cfg:
+{
+    uint8_t  proto=3;
+    uint8_t  qid=3;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=1;
+    uint32_t nid=0x1;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt = 0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_cfg_spg4.txt b/tools/mac_cfg/pkt_cfg_spg4.txt
new file mode 100755
index 0000000..32aff93
--- /dev/null
+++ b/tools/mac_cfg/pkt_cfg_spg4.txt
@@ -0,0 +1,24 @@
+
+pkt_cfg:
+{
+    uint8_t  proto=3;
+    uint8_t  qid=4;
+    uint8_t  bcast=0;
+    uint8_t  delimiter_type=1;
+    uint32_t nid=0x1;
+    uint32_t dtei=0x0002;
+    uint32_t stei=0x0001;
+    uint8_t  tmi=0;
+    uint8_t  ext_tmi=0;
+    uint8_t  lid=0;
+    uint8_t  pb_num=1;
+    uint8_t  need_ack=1;
+    uint8_t  need_encry = 0;
+    uint8_t  need_decrypt = 0;
+    uint32_t avln_idx_in_desc = 0;
+    uint32_t key_table_idx_in_desc = 0;
+    uint32_t key_idx_in_desc = 0;
+    uint8_t  hw_retry_cnt = 0;
+    uint8_t phase=0;
+    uint8_t pkt_idx=0;
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_data0.txt b/tools/mac_cfg/pkt_data0.txt
new file mode 100644
index 0000000..d47fc5a
--- /dev/null
+++ b/tools/mac_cfg/pkt_data0.txt
@@ -0,0 +1,14 @@
+
+pkt_cfg:
+{
+uint8_t data_num =0;
+uint8_t pkt[]={
+00 00 58 00 00 02 00 56 80 11 50 03 56 00 00 00
+00 7f 11 22 33 44 55 3b 01 00 00 00 00 00 00 00
+00 00 01 03 00 00 01 00 ef be ad de 00 12 00 00
+00 00 11 05 13 10 09 00 00 00 00 00 ad de 00 23
+67 45 bd fe ff 00 11 00 02 00 01 00 00 56 93 80
+f9 f4 8e 27 42 cd 00 00 00 e8 03 00 01 b0 01 50
+00 00 00 00
+};
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_data1.txt b/tools/mac_cfg/pkt_data1.txt
new file mode 100644
index 0000000..32d9c94
--- /dev/null
+++ b/tools/mac_cfg/pkt_data1.txt
@@ -0,0 +1,15 @@
+
+pkt_cfg:
+{
+uint8_t data_num =1;
+uint8_t pkt[]={
+
+00 00 01 00 00 02 00 56 80 11 50 03 56 00 00 00
+00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f
+40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f
+50 51 52 53
+};
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_data_band0.txt b/tools/mac_cfg/pkt_data_band0.txt
new file mode 100755
index 0000000..d048674
--- /dev/null
+++ b/tools/mac_cfg/pkt_data_band0.txt
@@ -0,0 +1,13 @@
+
+pkt_cfg:
+{
+uint8_t data_idx =0;
+uint8_t pkt[]={
+
+08 00 ff 5f 00 02 00 30 30 10 50 03 56 30 00 00
+11 06 00 00 00 60 00 00 00 00 00 00 00 00 00 00
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+
+};
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_data_band1.txt b/tools/mac_cfg/pkt_data_band1.txt
new file mode 100755
index 0000000..b3bdddf
--- /dev/null
+++ b/tools/mac_cfg/pkt_data_band1.txt
@@ -0,0 +1,13 @@
+
+pkt_cfg:
+{
+uint8_t data_idx =0;
+uint8_t pkt[]={
+
+08 00 ff 5f 00 02 00 30 30 10 50 03 56 30 00 00
+11 06 00 00 00 60 10 00 00 00 00 00 00 00 00 00
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+
+};
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_data_band2.txt b/tools/mac_cfg/pkt_data_band2.txt
new file mode 100755
index 0000000..a27d832
--- /dev/null
+++ b/tools/mac_cfg/pkt_data_band2.txt
@@ -0,0 +1,13 @@
+
+pkt_cfg:
+{
+uint8_t data_idx =0;
+uint8_t pkt[]={
+
+08 00 ff 5f 00 02 00 30 30 10 50 03 56 30 00 00
+11 06 00 00 00 60 20 00 00 00 00 00 00 00 00 00
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+
+};
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_data_band3.txt b/tools/mac_cfg/pkt_data_band3.txt
new file mode 100755
index 0000000..73f1f81
--- /dev/null
+++ b/tools/mac_cfg/pkt_data_band3.txt
@@ -0,0 +1,13 @@
+
+pkt_cfg:
+{
+uint8_t data_idx =0;
+uint8_t pkt[]={
+
+08 00 ff 5f 00 02 00 30 30 10 50 03 56 30 00 00
+11 06 00 00 00 60 30 00 00 00 00 00 00 00 00 00
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+
+};
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_data_cert.txt b/tools/mac_cfg/pkt_data_cert.txt
new file mode 100644
index 0000000..1366e2b
--- /dev/null
+++ b/tools/mac_cfg/pkt_data_cert.txt
@@ -0,0 +1,23 @@
+
+pkt_cfg:
+{
+uint8_t data_idx =0;
+uint8_t pkt[]={
+
+08 00 ff 5f 00 02 00 56 80 11 50 03 56 30 11 06
+00 00 00 40 00 01 00 00 00 00 00 00 00 00 00 00
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f
+40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f
+50 51 52 53 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f
+40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f
+40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f
+};
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_data_mac_tt.txt b/tools/mac_cfg/pkt_data_mac_tt.txt
new file mode 100644
index 0000000..ee4b64c
--- /dev/null
+++ b/tools/mac_cfg/pkt_data_mac_tt.txt
@@ -0,0 +1,13 @@
+
+pkt_cfg:
+{
+uint8_t data_idx =0;
+uint8_t pkt[]={
+
+08 00 ff 5f 00 02 00 30 30 10 50 03 56 30 00 00
+11 06 00 00 00 50 ff ff 00 00 00 00 00 00 00 00
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+
+};
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_data_mask0.txt b/tools/mac_cfg/pkt_data_mask0.txt
new file mode 100755
index 0000000..f536544
--- /dev/null
+++ b/tools/mac_cfg/pkt_data_mask0.txt
@@ -0,0 +1,13 @@
+
+pkt_cfg:
+{
+uint8_t data_idx =0;
+uint8_t pkt[]={
+
+08 00 ff 5f 00 02 00 30 30 10 50 03 56 30 00 00
+11 06 00 00 00 70 00 00 00 00 00 00 00 00 00 00
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+
+};
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_data_mask1.txt b/tools/mac_cfg/pkt_data_mask1.txt
new file mode 100755
index 0000000..6566b25
--- /dev/null
+++ b/tools/mac_cfg/pkt_data_mask1.txt
@@ -0,0 +1,13 @@
+
+pkt_cfg:
+{
+uint8_t data_idx =0;
+uint8_t pkt[]={
+
+08 00 ff 5f 00 02 00 30 30 10 50 03 56 30 00 00
+11 06 00 00 00 70 10 00 00 00 00 00 00 00 00 00
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+
+};
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_data_mask2.txt b/tools/mac_cfg/pkt_data_mask2.txt
new file mode 100755
index 0000000..3af0128
--- /dev/null
+++ b/tools/mac_cfg/pkt_data_mask2.txt
@@ -0,0 +1,13 @@
+
+pkt_cfg:
+{
+uint8_t data_idx =0;
+uint8_t pkt[]={
+
+08 00 ff 5f 00 02 00 30 30 10 50 03 56 30 00 00
+11 06 00 00 00 70 20 00 00 00 00 00 00 00 00 00
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+
+};
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_data_mask3.txt b/tools/mac_cfg/pkt_data_mask3.txt
new file mode 100755
index 0000000..49371ca
--- /dev/null
+++ b/tools/mac_cfg/pkt_data_mask3.txt
@@ -0,0 +1,13 @@
+
+pkt_cfg:
+{
+uint8_t data_idx =0;
+uint8_t pkt[]={
+
+08 00 ff 5f 00 02 00 30 30 10 50 03 56 30 00 00
+11 06 00 00 00 70 30 00 00 00 00 00 00 00 00 00
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+
+};
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_data_phy_lp.txt b/tools/mac_cfg/pkt_data_phy_lp.txt
new file mode 100644
index 0000000..6ab9fed
--- /dev/null
+++ b/tools/mac_cfg/pkt_data_phy_lp.txt
@@ -0,0 +1,13 @@
+
+pkt_cfg:
+{
+uint8_t data_idx =0;
+uint8_t pkt[]={
+
+08 00 ff 5f 00 02 00 30 30 10 50 03 56 30 00 00
+11 06 00 00 00 40 ff ff 00 00 00 00 00 00 00 00
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+
+};
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/pkt_data_phy_tt.txt b/tools/mac_cfg/pkt_data_phy_tt.txt
new file mode 100644
index 0000000..c6964f1
--- /dev/null
+++ b/tools/mac_cfg/pkt_data_phy_tt.txt
@@ -0,0 +1,13 @@
+
+pkt_cfg:
+{
+uint8_t data_idx =0;
+uint8_t pkt[]={
+
+08 00 ff 5f 00 02 00 30 30 10 50 03 56 30 00 00
+11 06 00 00 00 30 ff ff 00 00 00 00 00 00 00 00
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+
+};
+}
\ No newline at end of file
diff --git a/tools/mac_cfg/ring_cfg.txt b/tools/mac_cfg/ring_cfg.txt
new file mode 100644
index 0000000..419eab3
--- /dev/null
+++ b/tools/mac_cfg/ring_cfg.txt
@@ -0,0 +1,21 @@
+
+/*rx_cfg*/
+typedef struct _rx_cfg
+{
+    uint8_t ring_id = 0;
+    uint8_t ring_sz = 10;   //20            40
+    uint32_t buf_sz = 584;  //200:64+136  584:64+520  136:64+72  328:64+264
+    uint8_t bufsz_filter_sel=0;
+    uint8_t filter=0;
+//0 rx_desc
+    uint8_t cfg_type0 = 0;  //desc
+    uint8_t cfg_offset0 = 0;
+    uint8_t cfg_enable0 = 1;
+
+//1 rx_payload
+    uint8_t cfg_type1 = 6;
+    uint8_t cfg_offset1 = 64; //payload offset
+    uint8_t cfg_enable1 = 1;
+
+    uint8_t cert_flag = 0;
+}rx_cfg_t;
\ No newline at end of file
diff --git a/tools/mac_cfg/test_case.txt b/tools/mac_cfg/test_case.txt
new file mode 100644
index 0000000..58d917f
--- /dev/null
+++ b/tools/mac_cfg/test_case.txt
@@ -0,0 +1,6 @@
+
+send_case_cfg {
+    uint32_t interval_time=20;//unit 1'ms
+    uint32_t packe_num=1; // total numbers
+    uint32_t user_updata_time=1;
+} 
\ No newline at end of file
diff --git a/tools/oem/BRKI3C02_OEM.ini b/tools/oem/BRKI3C02_OEM.ini
new file mode 100644
index 0000000..e754a26
--- /dev/null
+++ b/tools/oem/BRKI3C02_OEM.ini
@@ -0,0 +1,43 @@
+general
+ bid 30
+ mid 2
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ meter
+
+uart1
+ tx 38
+ rx 29
+ ext
+
+uart2
+ tx 28
+ log
+
+uart3
+ ext
+ tx 20
+ rx 21
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 5
+ rx 4
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 12
+ phase_b 13
+ phase_c 14
+
+spi
+ clk 41
+ mosi 42
+ miso 43
+
+#use iic0
+iic
+ sda 24
+ scl 25
diff --git a/tools/oem/BRKSTA02_OEM.ini b/tools/oem/BRKSTA02_OEM.ini
new file mode 100644
index 0000000..3b5d2d1
--- /dev/null
+++ b/tools/oem/BRKSTA02_OEM.ini
@@ -0,0 +1,28 @@
+general
+ bid 43
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ meter
+
+uart1
+ tx 38
+ rx 29
+ ext
+
+uart2
+ tx 28
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 27
+ rx 26
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 23
+ phase_b 18
+ phase_c 19
diff --git a/tools/oem/BRMTCCO01_OEM.ini b/tools/oem/BRMTCCO01_OEM.ini
new file mode 100644
index 0000000..6cd7880
--- /dev/null
+++ b/tools/oem/BRMTCCO01_OEM.ini
@@ -0,0 +1,44 @@
+general
+ bid 26
+ mid 1
+ vid HT
+
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ log
+
+uart2
+ tx 0
+ rx 1
+ cli
+
+led
+ tx 32
+ rx 33
+ phase_a 34
+ phase_b 35
+ phase_c 36
+ 
+tx_e
+ phase_a 26
+ phase_b 24
+ phase_c 22
+
+rx_e
+ phase_a 27
+ phase_b 25
+ phase_c 23
+ 
+glna
+ phase_a 28
+ phase_b 20
+ phase_c 21
+
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/BRMTCCO02_OEM.ini b/tools/oem/BRMTCCO02_OEM.ini
new file mode 100644
index 0000000..6cd7880
--- /dev/null
+++ b/tools/oem/BRMTCCO02_OEM.ini
@@ -0,0 +1,44 @@
+general
+ bid 26
+ mid 1
+ vid HT
+
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ log
+
+uart2
+ tx 0
+ rx 1
+ cli
+
+led
+ tx 32
+ rx 33
+ phase_a 34
+ phase_b 35
+ phase_c 36
+ 
+tx_e
+ phase_a 26
+ phase_b 24
+ phase_c 22
+
+rx_e
+ phase_a 27
+ phase_b 25
+ phase_c 23
+ 
+glna
+ phase_a 28
+ phase_b 20
+ phase_c 21
+
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/BRMTI3C02_OEM.ini b/tools/oem/BRMTI3C02_OEM.ini
new file mode 100644
index 0000000..d513074
--- /dev/null
+++ b/tools/oem/BRMTI3C02_OEM.ini
@@ -0,0 +1,43 @@
+general
+ bid 28
+ mid 2
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ meter
+
+uart1
+ tx 38
+ rx 29
+ ir
+
+uart2
+ tx 28
+ log
+
+uart3
+ ext
+ tx 20
+ rx 21
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 27
+ rx 26
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 23
+ phase_b 18
+ phase_c 19
+
+spi
+ clk 41
+ mosi 42
+ miso 43
+
+#use iic0
+iic
+ sda 24
+ scl 25
diff --git a/tools/oem/BRMTSTA01_OEM.ini b/tools/oem/BRMTSTA01_OEM.ini
new file mode 100644
index 0000000..d805729
--- /dev/null
+++ b/tools/oem/BRMTSTA01_OEM.ini
@@ -0,0 +1,29 @@
+general
+ bid 27
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ rx 9
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 32
+ rx 33
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 47
diff --git a/tools/oem/BRMTSTA02_OEM.ini b/tools/oem/BRMTSTA02_OEM.ini
new file mode 100644
index 0000000..d805729
--- /dev/null
+++ b/tools/oem/BRMTSTA02_OEM.ini
@@ -0,0 +1,29 @@
+general
+ bid 27
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ rx 9
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 32
+ rx 33
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 47
diff --git a/tools/oem/BSRMSTA02_OEM.ini b/tools/oem/BSRMSTA02_OEM.ini
new file mode 100644
index 0000000..cc38dce
--- /dev/null
+++ b/tools/oem/BSRMSTA02_OEM.ini
@@ -0,0 +1,14 @@
+general
+ bid 40
+ mid 2
+ vid HT
+
+uart1
+ meter
+ tx 43
+ rx 42
+
+uart2
+ tx 23
+ log
+
diff --git a/tools/oem/CCTTCCO01_OEM.ini b/tools/oem/CCTTCCO01_OEM.ini
new file mode 100644
index 0000000..4f90435
--- /dev/null
+++ b/tools/oem/CCTTCCO01_OEM.ini
@@ -0,0 +1,43 @@
+general
+ bid 85
+ mid 1
+ vid HT
+
+uart0
+ tx 30
+ log
+
+uart1
+ tx 34
+ rx 35
+
+uart2
+ tx 0
+ rx 1
+
+uart3
+ tx 2
+ rx 3
+
+led
+ tx 44
+
+tx_e
+ phase_a 26
+ phase_b 24
+ phase_c 22
+
+rx_e
+ phase_a 27
+ phase_b 25
+ phase_c 23
+
+glna
+ phase_a 28
+ phase_b 20
+ phase_c 21
+
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/CPLTCCO02_OEM.ini b/tools/oem/CPLTCCO02_OEM.ini
new file mode 100755
index 0000000..13e1fe7
--- /dev/null
+++ b/tools/oem/CPLTCCO02_OEM.ini
@@ -0,0 +1,25 @@
+general
+ bid 23
+ mid 1
+# uart's option: tx/rx
+uart0
+ meter
+
+uart1
+ tx 41
+ rx 40
+ cli
+
+uart2
+ tx 29
+ rx 28
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 43
+ rx 42
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 38
\ No newline at end of file
diff --git a/tools/oem/CPLTSTA02_OEM.ini b/tools/oem/CPLTSTA02_OEM.ini
new file mode 100755
index 0000000..5a9881a
--- /dev/null
+++ b/tools/oem/CPLTSTA02_OEM.ini
@@ -0,0 +1,26 @@
+general
+ bid 24
+ mid 0
+
+# uart's option: tx/rx
+uart0
+ meter
+
+uart1
+ tx 41
+ rx 40
+ cli
+
+uart2
+ tx 29
+ rx 28
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 43
+ rx 42
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 38
diff --git a/tools/oem/D2DCCO01_OEM.ini b/tools/oem/D2DCCO01_OEM.ini
new file mode 100755
index 0000000..55e77f6
--- /dev/null
+++ b/tools/oem/D2DCCO01_OEM.ini
@@ -0,0 +1,44 @@
+general
+ bid 78
+ mid 1
+ vid HT
+
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ log
+
+uart2
+ tx 0
+ rx 1
+ cli
+
+led
+ tx 32
+ rx 33
+ phase_a 34
+ phase_b 35
+ phase_c 36
+
+tx_e
+ phase_a 26
+ phase_b 24
+ phase_c 22
+
+rx_e
+ phase_a 27
+ phase_b 25
+ phase_c 23
+
+glna
+ phase_a 28
+ phase_b 20
+ phase_c 21
+
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/D2DSTA01_OEM.ini b/tools/oem/D2DSTA01_OEM.ini
new file mode 100755
index 0000000..4dc5db5
--- /dev/null
+++ b/tools/oem/D2DSTA01_OEM.ini
@@ -0,0 +1,47 @@
+general
+ bid 79
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ log
+
+uart2
+ tx 0
+ rx 1
+ cli
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 32
+ rx 33
+ phase_a 34
+ phase_b 35
+ phase_c 36
+
+tx_e
+ phase_a 26
+ phase_b 24
+ phase_c 22
+
+rx_e
+ phase_a 27
+ phase_b 25
+ phase_c 23
+
+glna
+ phase_a 28
+ phase_b 20
+ phase_c 21
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/DMPLIIC01_OEM.ini b/tools/oem/DMPLIIC01_OEM.ini
new file mode 100644
index 0000000..2bf1211
--- /dev/null
+++ b/tools/oem/DMPLIIC01_OEM.ini
@@ -0,0 +1,24 @@
+general
+ bid 15
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 32
+ rx 48
+ cli
+
+uart2
+ tx 8
+ rx 1
+ log
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 47
diff --git a/tools/oem/DMPLSTA01_OEM.ini b/tools/oem/DMPLSTA01_OEM.ini
new file mode 100644
index 0000000..2bf1211
--- /dev/null
+++ b/tools/oem/DMPLSTA01_OEM.ini
@@ -0,0 +1,24 @@
+general
+ bid 15
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 32
+ rx 48
+ cli
+
+uart2
+ tx 8
+ rx 1
+ log
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 47
diff --git a/tools/oem/DT0530CCO03_OEM.ini b/tools/oem/DT0530CCO03_OEM.ini
new file mode 100644
index 0000000..59e6645
--- /dev/null
+++ b/tools/oem/DT0530CCO03_OEM.ini
@@ -0,0 +1,184 @@
+# DT0530 cco board, external rf chip, external pa chip
+general
+    bid     91  #BOARD_DTCCO03
+    mid     1   #MODULE_TYPE_CCO
+    vid     DT
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio  function              gpio  function
+# 12    rf_spi_clk          11    rf_spi_mosi           10    rf_spi_miso
+# 9     rf_spi_cs           42    rf_mclk               43    rf_fclk
+# 39    zc_c                38    zc_c_ext              37    zc_b
+# 36    zc_b_ext            35    zc_a                  34    pa_led\uart1_tx
+# 33    pb_led\uart1_rx     32    pc_led                31    charge_en
+# 30    pa_c_tx_en          29    pa_c_rx_en            28    uart2_tx
+# 46    rf_agc_gain         45    rf_enable             44    rf_txnrx
+# 47    rf_dq0              48    rf_dq1                49    rf_dq2
+# 27    nc                  1     tx_led                0     rx_led
+# 3     pa_testp(warning)   2     pa_a_rx_en            4     pa_a_tx_en
+# 7     pa_lan_gain_ctr0    6     uart0_tx              5     uart0_rx
+# 8     pa_lan_gain_ctr1    26    pa_lan_gain_ctr2      50    rf_dq3
+# 51    rf_dq4              52    rf_dq5                53    rf_dq6
+# 54    rf_dq7              55    rf_dq8                56    rf_dq9
+# 57    rf_dq10             58    rf_dq11               59    rf_pd
+# 61    uart2_rx            62    rf_channel_sw2(io)    63    nc
+# 64    m_sta(adc_gnd)      65    adc_12v               66    adc_3.3v
+# 67    pa_b_tx_en          68    zc_a_ext              69    pa_b_rx_en
+# 70    nc
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function(to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    9   1   108 #GPIO_SPI_RF_CS
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    12  1   107 #GPIO_SPI_RF_CLK
+
+    3   1   10  #GPIO_GEODE_OVT
+
+    35  1   18  #GPIO_PA_ZC
+    37  1   19  #GPIO_PB_ZC
+    39  1   20  #GPIO_PC_ZC
+    68  1   44  #GPIO_PA_ZC_EXT
+    36  1   45  #GPIO_PB_ZC_EXT
+    38  1   46  #GPIO_PC_ZC_EXT
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   1   #UART_CLI_PORT
+    tx  28
+    rx  61
+
+    1   1   0   #UART_PRINT
+    tx  34
+    rx  33
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   2   #IOT_PLC_PHASE_A_LED
+    ledout  34
+
+    1   1   3   #IOT_PLC_PHASE_B_LED
+    ledout  33
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  32
+
+    3   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    4   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+#   up_0    35
+#   up_1    37
+#   up_2    39
+#   down_0  68
+#   down_1  36
+#   down_2  38
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    rx_en_1 69  #Phase B Enable receiving
+    tx_en_1 67  #Phase B Enable sending
+    rx_en_2 29  #Phase C Enable receiving
+    tx_en_2 30  #Phase C Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3201覆膜为DT0530
+#   chip id: 0x1003     subid: 0x1063
+
+#=================== 13.10.08.61(HW_VERSION_DT_CCO_DM_V1) ===================#
+# DT CCO 覆膜HZ3201芯片 资源与DT0530的一样
+# overview
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_mosi         10    rf_spi_miso         9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    zc_c
+#   38  zc_c_ext            37    zc_b                36    zc_b_ext
+#   35  zc_a                34    pa_led\uart1_tx     33    pb_led\uart1_rx
+#   32  pc_led              31    charge_en           30    pa_c_tx_en
+#   29  pa_c_rx_en          28    uart2_tx            46    rf_agc_gain
+#   45  rf_enable           44    rf_txnrx            47    rf_dq0
+#   48  rf_dq1              49    rf_dq2              27    nc
+#   1   tx_led              0     rx_led              3     pa_testp(warning)
+#   2   pa_rx_en            4     pa_tx_en            7     pa_lan_gain_ctr0
+#   6   uart0_tx            5     uart0_rx            8     pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50    rf_dq3              51    rf_dq4
+#   52  rf_dq5              53    rf_dq6              54    rf_dq7
+#   55  rf_dq8              56    rf_dq9              57    rf_dq10
+#   58  rf_dq11             59    rf_pd               61    uart2_rx
+#   62  rf_channel_sw(io)   64    m_sta(adc_gnd)      65    adc_12v
+#   66  adc_3.3v            67    pa_b_tx_en          68    zc_a_ext
+#   69  pa_b_rx_en          12    rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0A083D  #13.10.08.61 Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
diff --git a/tools/oem/DT0530CKB03_OEM.ini b/tools/oem/DT0530CKB03_OEM.ini
new file mode 100644
index 0000000..a633229
--- /dev/null
+++ b/tools/oem/DT0530CKB03_OEM.ini
@@ -0,0 +1,115 @@
+# DT0530 ckb board, external rf chip, external pa chip.
+general
+    bid     104  #BOARD_DTCKB03
+    mid     0   #MODULE_TYPE_STA
+    vid     DT
+    fver    1
+
+#=============================== default rc====================================#
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  nc                  37      nc                  36      nc
+#   35  nc                  34      rf_clk              32      set
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      m_sta(adc0)         65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(adc3)         68      zc_a_up(adc4)
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    39  1   120 #GPIO_LIC_CTRL
+    34  1   121 #GPIO_RF_CLK
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   12  #GPIO_PM_CHARGE_EN
+    29  1   1   #GPIO_STA_OUT
+    3   1   10  #GPIO_GEODE_OVT
+    67  1   13  #GPIO_RST_CTRL
+    68  1   18  #GPIO_PA_ZC
+    69  1   0   #GPIO_PLC_EVENT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
\ No newline at end of file
diff --git a/tools/oem/DT05313PS03_OEM.ini b/tools/oem/DT05313PS03_OEM.ini
new file mode 100644
index 0000000..9d294ca
--- /dev/null
+++ b/tools/oem/DT05313PS03_OEM.ini
@@ -0,0 +1,213 @@
+# GX2011 3ps board, external rf chip, external pa chip.
+general
+    bid     92  #BOARD_DT3PS03
+    mid     4   #MODULE_TYPE_3_PHASE_STA
+    vid     DT
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio  function              gpio  function
+# 12    rf_spi_clk          11    rf_spi_mosi           10    rf_spi_miso
+# 9     rf_spi_cs           42    rf_mclk               43    rf_fclk
+# 39    mo_clk_flash        38    mo_si_flash           37    mi_so_flash
+# 36    zc_b                35    zc_c                  34    clk_rf
+# 33    mo_cs_flash         32    set                   31    charge_en
+# 30    nc                  29    sta_out               28    uart2_tx
+# 46    rf_agc_gain         45    rf_enable             44    rf_txnrx
+# 47    rf_dq0              48    rf_dq1                49    rf_dq2
+# 27    nc                  1     tx_led                0     rx_led
+# 3     pa_testp(warning)   2     pa_a_rx_en            4     pa_a_tx_en
+# 7     pa_lan_gain_ctr0    6     uart0_tx              5     uart0_rx
+# 8     pa_lan_gain_ctr1    26    pa_lan_gain_ctr2      50    rf_dq3
+# 51    rf_dq4              52    rf_dq5                53    rf_dq6
+# 54    rf_dq7              55    rf_dq8                56    rf_dq9
+# 57    rf_dq10             58    rf_dq11               59    rf_pd
+# 61    lic_ctr             62    rf_channel_sw2(io)    63    nc
+# 64    m_sta(adc_gnd)      65    adc_12v               66    adc_3.3v
+# 67    d_rst(soft reset)   68    zc_a                  69    event
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    39  1   68  #GPIO_SPI_FLASH_CLK
+    38  1   70  #GPIO_SPI_FLASH_MOSI
+    37  1   71  #GPIO_SPI_FLASH_MISO
+    33  1   69  #GPIO_SPI_FLASH_CS
+
+    61  1   120 #GPIO_LIC_CTRL
+
+    34  1   121 #GPIO_RF_CLK
+    3   1   10  #GPIO_GEODE_OVT
+
+    32  1   17  #GPIO_GOLDEN_SET
+    29  1   1   #GPIO_STA_OUT
+    69  1   0   #GPIO_PLC_EVENT
+    67  1   13  #GPIO_RST_CTRL
+
+    68  1   18  #GPIO_PA_ZC
+    36  1   19  #GPIO_PB_ZC
+    35  1   20  #GPIO_PC_ZC
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+#   up_1    36
+#   up_2    35
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3211覆膜为DT0531
+#   chip id: 0x1001     subid: 0x1061
+
+#==================== 13.10.02.61(HW_VERSION_DT_3PS_DM_V1) ==================#
+# overview
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_mosi         10    rf_spi_miso         9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    flash_spi_clk
+#   38  flash_spi_mosi      37    flash_spi_miso      36    zc_b
+#   35  zc_c                34    rf_clk              33    flash_spi_cs
+#   32  set(sta)            31    charge_en           30    nc
+#   29  sta_out             28    uart2_tx            46    rf_agc_gain
+#   45  rf_enable           44    rf_txnrx            47    rf_dq0
+#   48  rf_dq1              49    rf_dq2              27    multi
+#   1   tx_led              0     rx_led              3     pa_testp(warning)
+#   2   pa_rx_en            4     pa_tx_en            7     pa_lan_gain_ctr0
+#   6   uart0_tx            5     uart0_rx            8     pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50    rf_dq3              51    rf_dq4
+#   52  rf_dq5              53    rf_dq6              54    rf_dq7
+#   55  rf_dq8              56    rf_dq9              57    rf_dq10
+#   58  rf_dq11             59    rf_pd               61    pa_lic_ctr
+#   62  rf_channel_sw2      64    m_sta(adc_gnd)      65    adc_12v
+#   66  adc_3.3v            67    d_rst(soft reset)   68    zc_a
+#   69  event               12    rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0A023D  #13.10.02.61   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    27  1   127 #GPIO_MULTI_PULSE
+
+#==================== 13.10.02.62(HW_VERSION_DT_3PS_DM_LOAD_V1) ==================#
+# DT 3PS 带小负载
+# overview
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_mosi         10    rf_spi_miso         9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    flash_spi_clk
+#   38  flash_spi_mosi      37    flash_spi_miso      36    zc_b
+#   35  zc_c                34    rf_clk              33    flash_spi_cs
+#   32  set(sta)            31    charge_en           30    load_send
+#   29  sta_out             28    uart2_tx            46    rf_agc_gain
+#   45  rf_enable           44    rf_txnrx            47    rf_dq0
+#   48  rf_dq1              49    rf_dq2              27    multi
+#   1   tx_led              0     rx_led              3     pa_testp(warning)
+#   2   pa_rx_en            4     pa_tx_en            7     pa_lan_gain_ctr0
+#   6   uart0_tx            5     uart0_rx            8     pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50    rf_dq3              51    rf_dq4
+#   52  rf_dq5              53    rf_dq6              54    rf_dq7
+#   55  rf_dq8              56    rf_dq9              57    rf_dq10
+#   58  rf_dq11             59    rf_pd               61    pa_lic_ctr
+#   62  rf_channel_sw2      64    m_sta(adc_gnd)      65    adc_12v
+#   66  adc_3.3v            67    d_rst(soft reset)   68    zc_a
+#   69  event               12    rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0A023E  #13.10.02.62   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x0D0A023D
+
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   load send gpio
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
diff --git a/tools/oem/DT0531IIC03_OEM.ini b/tools/oem/DT0531IIC03_OEM.ini
new file mode 100644
index 0000000..cffd583
--- /dev/null
+++ b/tools/oem/DT0531IIC03_OEM.ini
@@ -0,0 +1,171 @@
+# DT0531 IIC board, external rf chip, external pa chip.
+general
+    bid     95  #BOARD_DTIIC03
+    mid     2   #MODULE_TYPE_COLLECTOR_II
+    vid     DT
+    fver    1
+
+#=============================== default rc====================================#
+# DT IIC 真实芯片无资源分配
+#===================================== 覆膜资源 ===============================#
+# HZ3211覆膜为DT0531
+#   chip id: 0x1001     subid: 0x1061
+
+#================#13.11.04.61(HW_VERSION_DT_IIC_DM_V1)=======================#
+# overview: extern flash chip
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_do           10    rf_spi_di           9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    flash_spi_cs
+#   38  flash_spi_clk       37    flash_spi_mosi      36    flash_spi_miso
+#   35  rf_clk              34    ir_rx               33    nc
+#   32  485_ctr             31    charge_en           30    ir_tx
+#   29  zc_rise             28    uart2_tx            46    rf_agc_gain
+#   45  rf_enable           44    rf_txnrx            47    rf_dq0
+#   48  rf_dq1              49    rf_dq2              27    nc
+#   1   485_led             0     sta led             3     pa_testp(warning)
+#   2   pa_rx_en            4     pa_tx_en            7     pa_lna_gain_ctr0
+#   6   uart0_tx            5     uart0_rx            8     pa_lna_gain_ctr1
+#   26  pa_lna_gain_ctr2    50    rf_dq3              51    rf_dq4
+#   52  rf_dq5              53    rf_dq6              54    rf_dq7
+#   55  rf_dq8              56    rf_dq9              57    rf_dq10
+#   58  rf_dq11             59    rf_pd               61    rf_channel_sw1
+#   62  rf_channel_sw2      64    pwr_led             65    adc_12v
+#   66  adc_3.3v            67    nc                  68    485_rxd
+#   69  485_txd             12    rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0B043D  #13.11.04.61  Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    39  1   69  #GPIO_SPI_FLASH_CS
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+    36  1   71  #GPIO_SPI_FLASH_MISO
+
+    35  1   121 #GPIO_RF_CLK
+    34  1   9   #GPIO_IR_RXD
+    32  1   7   #GPIO_RS485_TXE
+    31  1   12  #GPIO_PM_CHARGE_EN
+    30  1   8   #GPIO_IR_TXD
+    29  1   18  #GPIO_PA_ZC
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    1   1   3   #UART_IR_PORT
+    tx  30
+    rx  34
+
+    2   1   0   #UART_PRINT
+    tx  28
+
+    3   1   2   #UART_METER_PORT
+    tx  69
+    rx  68
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   6   #IOT_RS485_LED
+    ledout  1
+
+    1   1   7   #IOT_PLC_TR_LED
+    ledout  0
+
+    2   1   5   #IOT_PWR_LED
+    ledout  64
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    29
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#================#13.11.04.62(HW_VERSION_DT_IIC_DM_LOAD_V1)=======================#
+# overview: extern flash chip
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_do           10    rf_spi_di           9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    flash_spi_cs
+#   38  flash_spi_clk       37    flash_spi_mosi      36    flash_spi_miso
+#   35  rf_clk              34    ir_rx               33    nc
+#   32  485_ctr             31    charge_en           30    ir_tx
+#   29  zc_rise             28    uart2_tx            46    rf_agc_gain
+#   45  rf_enable           44    rf_txnrx            47    rf_dq0
+#   48  rf_dq1              49    rf_dq2              27    nc
+#   1   485_led             0     sta led             3     pa_testp(warning)
+#   2   pa_rx_en            4     pa_tx_en            7     pa_lna_gain_ctr0
+#   6   uart0_tx            5     uart0_rx            8     pa_lna_gain_ctr1
+#   26  pa_lna_gain_ctr2    50    rf_dq3              51    rf_dq4
+#   52  rf_dq5              53    rf_dq6              54    rf_dq7
+#   55  rf_dq8              56    rf_dq9              57    rf_dq10
+#   58  rf_dq11             59    rf_pd               61    rf_channel_sw1
+#   62  rf_channel_sw2      64    pwr_led             65    adc_12v
+#   66  adc_3.3v            67    load_send           68    485_rxd
+#   69  485_txd             12    rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0B043E  #13.11.04.62  Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x0D0B043D
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    67  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO67和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
diff --git a/tools/oem/DT0531STA03_OEM.ini b/tools/oem/DT0531STA03_OEM.ini
new file mode 100644
index 0000000..6946313
--- /dev/null
+++ b/tools/oem/DT0531STA03_OEM.ini
@@ -0,0 +1,239 @@
+# GX2011 sta board, external rf chip, external pa chip.
+general
+    bid     93  #BOARD_DTSTA03
+    mid     0   #MODULE_TYPE_STA
+    vid     DT
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio  function              gpio  function
+# 12    rf_spi_clk          11    rf_spi_mosi           10    rf_spi_miso
+# 9     rf_spi_cs           42    rf_mclk               43    rf_fclk
+# 39    lic_ctr             38    mo_clk_flash          37    mo_si_flash
+# 36    mi_so_flash         35    mo_cs_flash           34    clk_rf
+# 33    nc                  32    set                   31    charge_en
+# 30    send                29    sta_out               28    uart2_tx
+# 46    rf_agc_gain         45    rf_enable             44    rf_txnrx
+# 47    rf_dq0              48    rf_dq1                49    rf_dq2
+# 27    nc                  1     tx_led                0     rx_led
+# 3     pa_testp(warning)   2     pa_a_rx_en            4     pa_a_tx_en
+# 7     pa_lan_gain_ctr0    6     uart0_tx              5     uart0_rx
+# 8     pa_lan_gain_ctr1    26    pa_lan_gain_ctr2      50    rf_dq3
+# 51    rf_dq4              52    rf_dq5                53    rf_dq6
+# 54    rf_dq7              55    rf_dq8                56    rf_dq9
+# 57    rf_dq10             58    rf_dq11               59    rf_pd
+# 61    rf_channel_sw1(io)  62    rf_channel_sw2(io)    63    nc
+# 64    m_sta(adc_gnd)      65    adc_12v               66    adc_3.3v
+# 67    d_rst(soft reset)   68    zc_a                  69    event
+# 70    nc
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    39  1   120 #GPIO_LIC_CTRL
+
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+    36  1   71  #GPIO_SPI_FLASH_MISO
+    35  1   69  #GPIO_SPI_FLASH_CS
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+
+    34  1   121 #GPIO_RF_CLK
+    32  1   17  #GPIO_GOLDEN_SET
+    29  1   1   #GPIO_STA_OUT
+    3   1   10  #GPIO_GEODE_OVT
+    5   1   24  #GPIO_GOLDEN_RXD0
+    6   1   34  #GPIO_GOLDEN_TXD0
+    67  1   13  #GPIO_RST_CTRL
+    68  1   18  #GPIO_PA_ZC
+    69  1   0   #GPIO_PLC_EVENT
+
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3211覆膜为GX2011
+#   chip id: 0x1001     subid: 0x1061
+
+#=================== 13.10.01.61(HW_VERSION_DT_STA_DM_V1) ===================#
+# overview
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_do           10    rf_spi_di           9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    pa_lic_ctr
+#   38  flash_spi_clk       37    flash_spi_mosi      36    flash_spi_miso
+#   35  flash_spi_cs        34    rf_clk              32    set(sta)
+#   31  charge_en           30    nc                  29    sta_out
+#   28  uart2_tx            46    rf_agc_gain         45    rf_enable
+#   44  rf_txnrx            47    rf_dq0              48    rf_dq1
+#   49  rf_dq2              27    nc                  1     tx_led
+#   0   rx_led              3     pa_testp(warning)   2     pa_rx_en
+#   4   pa_tx_en            7     pa_lna_gain_ctr0    6     uart0_tx
+#   5   uart0_rx            8     pa_lna_gain_ctr1    26    pa_lna_gain_ctr2
+#   50  rf_dq3              51    rf_dq4              52    rf_dq5
+#   53  rf_dq6              54    rf_dq7              55    rf_dq8
+#   56  rf_dq9              57    rf_dq10             58    rf_dq11
+#   59  rf_pd               61    rf_channel_sw1      62    rf_channel_sw2
+#   64  m_sta(adc_gnd)      65    adc_12v             66    adc_3v3
+#   67  d_rst(soft reset)   68    zc_a                69    event
+#   12  rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A013D  #13.10.01.61   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+#=================== 13.10.01.62(HW_VERSION_DT_STA_DM_LOAD_V1) ===================#
+# DT STA 带小负载
+# overview
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_do           10    rf_spi_di           9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    pa_lic_ctr
+#   38  flash_spi_clk       37    flash_spi_mosi      36    flash_spi_miso
+#   35  flash_spi_cs        34    rf_clk              32    set(sta)
+#   31  charge_en           30    load_send           29    sta_out
+#   28  uart2_tx            46    rf_agc_gain         45    rf_enable
+#   44  rf_txnrx            47    rf_dq0              48    rf_dq1
+#   49  rf_dq2              27    nc                  1     tx_led
+#   0   rx_led              3     pa_testp(warning)   2     pa_rx_en
+#   4   pa_tx_en            7     pa_lna_gain_ctr0    6     uart0_tx
+#   5   uart0_rx            8     pa_lna_gain_ctr1    26    pa_lna_gain_ctr2
+#   50  rf_dq3              51    rf_dq4              52    rf_dq5
+#   53  rf_dq6              54    rf_dq7              55    rf_dq8
+#   56  rf_dq9              57    rf_dq10             58    rf_dq11
+#   59  rf_pd               61    rf_channel_sw1      62    rf_channel_sw2
+#   64  m_sta(adc_gnd)      65    adc_12v             66    adc_3v3
+#   67  d_rst(soft reset)   68    zc_a                69    event
+#   12  rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A013E  #13.10.01.62   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x0D0A013D
+
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   load send gpio
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+#=============================== 13.10.01.12(HW_VERSION_STA_CKQ_DM_V1) ==============#
+# overview
+# gpio  function            gpio  function              gpio  function
+# 12    rf_spi_clk          11    rf_spi_mosi           10    rf_spi_miso
+# 9     rf_spi_cs           42    rf_mclk               43    rf_fclk
+# 39    lic_ctr             38    mo_clk_flash          37    mo_si_flash
+# 36    mi_so_flash         35    mo_cs_flash           34    nc
+# 33    nc                  32    set                   31    charge_en
+# 30    send                29    sta_out               28    uart2_tx
+# 46    rf_agc_gain         45    rf_enable             44    rf_txnrx
+# 47    rf_dq0              48    rf_dq1                49    rf_dq2
+# 27    nc                  1     tx_led                0     rx_led
+# 3     pa_testp(warning)   2     pa_a_rx_en            4     pa_a_tx_en
+# 7     pa_lan_gain_ctr0    6     uart0_tx              5     uart0_rx
+# 8     pa_lan_gain_ctr1    26    pa_lan_gain_ctr2      50    rf_dq3
+# 51    rf_dq4              52    rf_dq5                53    rf_dq6
+# 54    rf_dq7              55    rf_dq8                56    rf_dq9
+# 57    rf_dq10             58    rf_dq11               59    rf_pd
+# 61    rf_channel_sw1(io)  62    rf_channel_sw2(io)    63    nc
+# 64    m_sta(adc_gnd)      65    adc_12v               66    adc_3.3v
+# 67    d_rst(soft reset)   68    zc_a                  69    event
+# 70    nc
+
+rc_hdr
+    hw_ver      0x0D0A010C  #13.10.01.12   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    34  255   255 #GPIO_SPI_RF_CLK
\ No newline at end of file
diff --git a/tools/oem/EVB3031CCO03_AMPIOT_OEM.ini b/tools/oem/EVB3031CCO03_AMPIOT_OEM.ini
new file mode 100644
index 0000000..eaabc20
--- /dev/null
+++ b/tools/oem/EVB3031CCO03_AMPIOT_OEM.ini
@@ -0,0 +1,140 @@
+# kl3 k48 evb board, some pins have two functions,
+# the second function is shielded, only one function can be enabled at a time.
+
+general
+    bid     48  #BOARD_EVB3031
+    mid     1   #cco
+    vid     WQ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name    func_default            func_2
+#   6       adc0\gpio64 adc0_test(ate use)      adc channel(0-3v adjustable)
+#   7       adc1\gpio65 m_sta(in place detect)  adc channel(0-3v adjustable)
+#   8       adc1\gpio66 ZB(phase B zero-cross)  adc channel(0-3v adjustable)
+#   9       adc1\gpio67 ZC(phase C zero-cross)  adc channel(0-3v adjustable)
+#   10      adc1\gpio68 D_RST(soft reset)       adc channel(0-3v adjustable)
+#   11      adc1\gpio69 ZA(phase A zero-cross)  adc channel(0-3v adjustable)
+#   15      GPIO39      SPI_CLK(extern flash)
+#   16      GPIO38      SPI_CS(extern flash)
+#   17      GPIO37      SPI_D0(extern flash)
+#   18      GPIO36      SPI_D1(extern flash)
+#   19      GPIO35      SPI_D2(extern flash)
+#   20      GPIO34      SPI_D3(extern flash)
+#   21      gpio33      uart2_tx                485_txd
+#   22      gpio32      uart2_rx                485_rxd
+#   23      gpio31      event                   485_ctr
+#   28      gpio27      pwm3_led(cathode)       key1(press down is low)
+#   29      tms\gpio01  pwm2\tx_led(cathode)    jtag_tms
+#   30      tck\gpio00  pwm1\rx_led(cathode)    jtag_tck
+#   31      tdo\gpio03  uart1_tx                jtag tdo
+#   32      tdi\gpio02  uart1_rx                jtag tdi
+#   33      trst\gpio04 sta_out                 jtag trst
+#   34      gpio07      set(sta)                key2(press down is low)
+#   37      uart0_tx\gpio06 uart0_tx
+#   38      uart0_rx\gpio07 uart0_rx
+#   39      gpio08      i2c_scl(link lm75bdp)   ir_tx
+#   40      gpio26      i2c_sda(link lm75bdp)   ir_rx
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    69  1   18  #GPIO_PA_ZC
+    #66  1   19  #GPIO_PB_ZC
+    #67  1   20  #GPIO_PC_ZC
+
+    68  1   13  #GPIO_RST_CTRL
+    31  1   0   #GPIO_PLC_EVENT
+    4   1   1   #GPIO_STA_OUT
+    7   1   17  #GPIO_GOLDEN_SET
+
+    #39  1   68  #GPIO_SPI_FLASH_CLK
+    #38  1   69  #GPIO_SPI_FLASH_CS
+    #37  1   70  #GPIO_SPI_FLASH_MOSI
+    #36  1   71  #GPIO_SPI_FLASH_MISO
+    #35  1   x   #spi_d2
+    #34  1   x   #spi_d3
+    #27  1   x   #pwm_led3
+    #8   1   x   #lm75bdp scl
+    #26  1   x   #lm75bdp sda
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   0   11  #UART_CUS_PORT_0
+    tx  6
+    rx  5
+
+    1   0   0   #UART_PRINT
+    tx  3
+    rx  2
+
+    2   1   0   #UART_PRINT
+    tx  33
+    rx  32
+
+    3   1   1   #UART_CLI_PORT
+    tx  64
+    rx  7
+
+    6   0   14  #UART_ICC_PORT
+    tx  11
+    rx  12
+
+    7   1   11  #UART_CUS_PORT_0
+    tx  12
+    rx  11
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    # sampling of gnd, but 12v\3v samples are not designed,
+    # power mgmt is invalid
+    1   1   1   #ADC_PM_GND
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+    #up_0    69
+    #up_1    66
+    #up_2    67
+
+# internal sealing one pa chips
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 80  #enlic_pad_0. Phase A Enable receiving
+    tx_en_0 81  #enlic_pad_1. Phase A Enable sending
+    gain_0  82  #glna_pad_0. Phase A gain control
+    gain_1  83  #glna_pad_1. Phase B gain control
+    gain_2  84  #glna_pad_2. Phase C gain control
\ No newline at end of file
diff --git a/tools/oem/EVB3031CCO03_OEM.ini b/tools/oem/EVB3031CCO03_OEM.ini
new file mode 100644
index 0000000..4e3e9ca
--- /dev/null
+++ b/tools/oem/EVB3031CCO03_OEM.ini
@@ -0,0 +1,128 @@
+# kl3 k48 evb board, some pins have two functions,
+# the second function is shielded, only one function can be enabled at a time.
+
+general
+    bid     48  #BOARD_EVB3031
+    mid     1   #cco
+    vid     WQ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name    func_default            func_2
+#   6       adc0\gpio64 adc0_test(ate use)      adc channel(0-3v adjustable)
+#   7       adc1\gpio65 m_sta(in place detect)  adc channel(0-3v adjustable)
+#   8       adc1\gpio66 ZB(phase B zero-cross)  adc channel(0-3v adjustable)
+#   9       adc1\gpio67 ZC(phase C zero-cross)  adc channel(0-3v adjustable)
+#   10      adc1\gpio68 D_RST(soft reset)       adc channel(0-3v adjustable)
+#   11      adc1\gpio69 ZA(phase A zero-cross)  adc channel(0-3v adjustable)
+#   15      GPIO39      SPI_CLK(extern flash)
+#   16      GPIO38      SPI_CS(extern flash)
+#   17      GPIO37      SPI_D0(extern flash)
+#   18      GPIO36      SPI_D1(extern flash)
+#   19      GPIO35      SPI_D2(extern flash)
+#   20      GPIO34      SPI_D3(extern flash)
+#   21      gpio33      uart2_tx                485_txd
+#   22      gpio32      uart2_rx                485_rxd
+#   23      gpio31      event                   485_ctr
+#   28      gpio27      pwm3_led(cathode)       key1(press down is low)
+#   29      tms\gpio01  pwm2\tx_led(cathode)    jtag_tms
+#   30      tck\gpio00  pwm1\rx_led(cathode)    jtag_tck
+#   31      tdo\gpio03  uart1_tx                jtag tdo
+#   32      tdi\gpio02  uart1_rx                jtag tdi
+#   33      trst\gpio04 sta_out                 jtag trst
+#   34      gpio07      set(sta)                key2(press down is low)
+#   37      uart0_tx\gpio06 uart0_tx
+#   38      uart0_rx\gpio07 uart0_rx
+#   39      gpio08      i2c_scl(link lm75bdp)   ir_tx
+#   40      gpio26      i2c_sda(link lm75bdp)   ir_rx
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    69  1   18  #GPIO_PA_ZC
+    #66  1   19  #GPIO_PB_ZC
+    #67  1   20  #GPIO_PC_ZC
+
+    68  1   13  #GPIO_RST_CTRL
+    31  1   0   #GPIO_PLC_EVENT
+    4   1   1   #GPIO_STA_OUT
+    7   1   17  #GPIO_GOLDEN_SET
+
+    #39  1   68  #GPIO_SPI_FLASH_CLK
+    #38  1   69  #GPIO_SPI_FLASH_CS
+    #37  1   70  #GPIO_SPI_FLASH_MOSI
+    #36  1   71  #GPIO_SPI_FLASH_MISO
+    #35  1   x   #spi_d2
+    #34  1   x   #spi_d3
+    #27  1   x   #pwm_led3
+    #8   1   x   #lm75bdp scl
+    #26  1   x   #lm75bdp sda
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    1   1   1   #UART_CLI_PORT
+    tx  3
+    rx  2
+
+    2   1   0   #UART_PRINT
+    tx  33
+    rx  32
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    # sampling of gnd, but 12v\3v samples are not designed,
+    # power mgmt is invalid
+    1   1   1   #ADC_PM_GND
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+    #up_0    69
+    #up_1    66
+    #up_2    67
+
+# internal sealing one pa chips
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 80  #enlic_pad_0. Phase A Enable receiving
+    tx_en_0 81  #enlic_pad_1. Phase A Enable sending
+    gain_0  82  #glna_pad_0. Phase A gain control
+    gain_1  83  #glna_pad_1. Phase B gain control
+    gain_2  84  #glna_pad_2. Phase C gain control
\ No newline at end of file
diff --git a/tools/oem/EVB3031STA03_AMPIOT_OEM.ini b/tools/oem/EVB3031STA03_AMPIOT_OEM.ini
new file mode 100644
index 0000000..f12d203
--- /dev/null
+++ b/tools/oem/EVB3031STA03_AMPIOT_OEM.ini
@@ -0,0 +1,140 @@
+# kl3 k48 evb board, some pins have two functions,
+# the second function is shielded, only one function can be enabled at a time.
+
+general
+    bid     48  #BOARD_EVB3031
+    mid     0   #MODULE_TYPE_STA
+    vid     WQ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name    func_default            func_2
+#   6       adc0\gpio64 adc0_test(ate use)      adc channel(0-3v adjustable)
+#   7       adc1\gpio65 m_sta(in place detect)  adc channel(0-3v adjustable)
+#   8       adc1\gpio66 ZB(phase B zero-cross)  adc channel(0-3v adjustable)
+#   9       adc1\gpio67 ZC(phase C zero-cross)  adc channel(0-3v adjustable)
+#   10      adc1\gpio68 D_RST(soft reset)       adc channel(0-3v adjustable)
+#   11      adc1\gpio69 ZA(phase A zero-cross)  adc channel(0-3v adjustable)
+#   15      GPIO39      SPI_CLK(extern flash)
+#   16      GPIO38      SPI_CS(extern flash)
+#   17      GPIO37      SPI_D0(extern flash)
+#   18      GPIO36      SPI_D1(extern flash)
+#   19      GPIO35      SPI_D2(extern flash)
+#   20      GPIO34      SPI_D3(extern flash)
+#   21      gpio33      uart2_tx                485_txd
+#   22      gpio32      uart2_rx                485_rxd
+#   23      gpio31      event                   485_ctr
+#   28      gpio27      pwm3_led(cathode)       key1(press down is low)
+#   29      tms\gpio01  pwm2\tx_led(cathode)    jtag_tms
+#   30      tck\gpio00  pwm1\rx_led(cathode)    jtag_tck
+#   31      tdo\gpio03  uart1_tx                jtag tdo
+#   32      tdi\gpio02  uart1_rx                jtag tdi
+#   33      trst\gpio04 sta_out                 jtag trst
+#   34      gpio07      set(sta)                key2(press down is low)
+#   37      uart0_tx\gpio06 uart0_tx
+#   38      uart0_rx\gpio07 uart0_rx
+#   39      gpio08      i2c_scl(link lm75bdp)   ir_tx
+#   40      gpio26      i2c_sda(link lm75bdp)   ir_rx
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    69  1   18  #GPIO_PA_ZC
+    #66  1   19  #GPIO_PB_ZC
+    #67  1   20  #GPIO_PC_ZC
+
+    68  1   13  #GPIO_RST_CTRL
+    31  1   0   #GPIO_PLC_EVENT
+    4   1   1   #GPIO_STA_OUT
+    7   1   17  #GPIO_GOLDEN_SET
+
+    #39  1   68  #GPIO_SPI_FLASH_CLK
+    #38  1   69  #GPIO_SPI_FLASH_CS
+    #37  1   70  #GPIO_SPI_FLASH_MOSI
+    #36  1   71  #GPIO_SPI_FLASH_MISO
+    #35  1   x   #spi_d2
+    #34  1   x   #spi_d3
+    #27  1   x   #pwm_led3
+    #8   1   x   #lm75bdp scl
+    #26  1   x   #lm75bdp sda
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   0   11  #UART_CUS_PORT_0
+    tx  6
+    rx  5
+
+    1   0   0   #UART_PRINT
+    tx  3
+    rx  2
+
+    2   1   0   #UART_PRINT
+    tx  33
+    rx  32
+
+    3   1   1   #UART_CLI_PORT
+    tx  64
+    rx  7
+
+    6   0   14  #UART_ICC_PORT
+    tx  11
+    rx  12
+
+    7   1   11  #UART_CUS_PORT_0
+    tx  12
+    rx  11
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    # sampling of gnd, but 12v\3v samples are not designed,
+    # power mgmt is invalid
+    1   1   1   #ADC_PM_GND
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+    #up_0    69
+    #up_1    66
+    #up_2    67
+
+# internal sealing one pa chips
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 80  #enlic_pad_0. Phase A Enable receiving
+    tx_en_0 81  #enlic_pad_1. Phase A Enable sending
+    gain_0  82  #glna_pad_0. Phase A gain control
+    gain_1  83  #glna_pad_1. Phase B gain control
+    gain_2  84  #glna_pad_2. Phase C gain control
\ No newline at end of file
diff --git a/tools/oem/EVB3031STA03_OEM.ini b/tools/oem/EVB3031STA03_OEM.ini
new file mode 100644
index 0000000..8edd12a
--- /dev/null
+++ b/tools/oem/EVB3031STA03_OEM.ini
@@ -0,0 +1,128 @@
+# kl3 k48 evb board, some pins have two functions,
+# the second function is shielded, only one function can be enabled at a time.
+
+general
+    bid     48  #BOARD_EVB3031
+    mid     0   #sta
+    vid     WQ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name    func_default            func_2
+#   6       adc0\gpio64 adc0_test(ate use)      adc channel(0-3v adjustable)
+#   7       adc1\gpio65 m_sta(in place detect)  adc channel(0-3v adjustable)
+#   8       adc1\gpio66 ZB(phase B zero-cross)  adc channel(0-3v adjustable)
+#   9       adc1\gpio67 ZC(phase C zero-cross)  adc channel(0-3v adjustable)
+#   10      adc1\gpio68 D_RST(soft reset)       adc channel(0-3v adjustable)
+#   11      adc1\gpio69 ZA(phase A zero-cross)  adc channel(0-3v adjustable)
+#   15      GPIO39      SPI_CLK(extern flash)
+#   16      GPIO38      SPI_CS(extern flash)
+#   17      GPIO37      SPI_D0(extern flash)
+#   18      GPIO36      SPI_D1(extern flash)
+#   19      GPIO35      SPI_D2(extern flash)
+#   20      GPIO34      SPI_D3(extern flash)
+#   21      gpio33      uart2_tx                485_txd
+#   22      gpio32      uart2_rx                485_rxd
+#   23      gpio31      event                   485_ctr
+#   28      gpio27      pwm3_led(cathode)       key1(press down is low)
+#   29      tms\gpio01  pwm2\tx_led(cathode)    jtag_tms
+#   30      tck\gpio00  pwm1\rx_led(cathode)    jtag_tck
+#   31      tdo\gpio03  uart1_tx                jtag tdo
+#   32      tdi\gpio02  uart1_rx                jtag tdi
+#   33      trst\gpio04 sta_out                 jtag trst
+#   34      gpio07      set(sta)                key2(press down is low)
+#   37      uart0_tx\gpio06 uart0_tx
+#   38      uart0_rx\gpio07 uart0_rx
+#   39      gpio08      i2c_scl(link lm75bdp)   ir_tx
+#   40      gpio26      i2c_sda(link lm75bdp)   ir_rx
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    69  1   18  #GPIO_PA_ZC
+    #66  1   19  #GPIO_PB_ZC
+    #67  1   20  #GPIO_PC_ZC
+
+    68  1   13  #GPIO_RST_CTRL
+    31  1   0   #GPIO_PLC_EVENT
+    4   1   1   #GPIO_STA_OUT
+    7   1   17  #GPIO_GOLDEN_SET
+
+    #39  1   68  #GPIO_SPI_FLASH_CLK
+    #38  1   69  #GPIO_SPI_FLASH_CS
+    #37  1   70  #GPIO_SPI_FLASH_MOSI
+    #36  1   71  #GPIO_SPI_FLASH_MISO
+    #35  1   x   #spi_d2
+    #34  1   x   #spi_d3
+    #27  1   x   #pwm_led3
+    #8   1   x   #lm75bdp scl
+    #26  1   x   #lm75bdp sda
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    1   1   1   #UART_CLI_PORT
+    tx  3
+    rx  2
+
+    2   1   0   #UART_PRINT
+    tx  33
+    rx  32
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    # sampling of gnd, but 12v\3v samples are not designed,
+    # power mgmt is invalid
+    1   1   1   #ADC_PM_GND
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+    #up_0    69  #phase a
+    #up_1    66  #phase b
+    #up_2    67  #phase c
+
+# internal sealing one pa chips
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 80  #enlic_pad_0. Phase A Enable receiving
+    tx_en_0 81  #enlic_pad_1. Phase A Enable sending
+    gain_0  82  #glna_pad_0. Phase A gain control
+    gain_1  83  #glna_pad_1. Phase B gain control
+    gain_2  84  #glna_pad_2. Phase C gain control
\ No newline at end of file
diff --git a/tools/oem/EVB3201CCO03_AMPSG_OEM.ini b/tools/oem/EVB3201CCO03_AMPSG_OEM.ini
new file mode 100644
index 0000000..a4c506f
--- /dev/null
+++ b/tools/oem/EVB3201CCO03_AMPSG_OEM.ini
@@ -0,0 +1,218 @@
+# kl3 k76 evb board, some pins have two functions,
+# the second function is shielded, only one function can be enabled at a time.
+
+general
+    bid     49  #BOARD_EVB3201
+    mid     1   #cco
+    vid     WQ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name    func_default            func_2
+#   1       GPIO11      RF_SPI_DI(rf module)
+#   2       GPIO10      RF_SPI_DO(rf module)
+#   3       GPIO09      RF_SPI_CS(rf module)
+#   4       GPIO42      207_MCLK(rf module)
+#   5       GPIO43      207_FCLK(rf module)
+#   8       GPIO39      pc_tx_en(pa module)     spi_cs(extern flash)
+#   9       GPIO38      pc_rx_en(pa module)     spi_clk(extern flash)
+#   10      GPIO37      pb_tx_en(pa module)     spi_d1(extern flash)
+#   11      GPIO36      pb_rx_en(pa module)     spi_d2(extern flash)
+#   12      GPIO35      pa_tx_en(pa module)     spi_d0(extern flash)
+#   13      GPIO34      pa_rx_en(pa module)     spi_d3(extern flash)
+#   14      GPIO33      m_sta(in place detect)  key1(press down is low)
+#   15      gpio32      set(sta)                i2c_scl(lm75bdp)
+#   16      gpio31      event                   i2c_sda(lm75bdp)
+#   18      gpio30      sta0                    485_ctr
+#   19      gpio29      uart2_tx                485_tx
+#   20      gpio28      uart2_rx                485_rx
+#   24      GPIO46      AGC_GAIN(rf module)
+#   25      GPIO45      207_ENABLE(rf module)
+#   26      GPIO44      207_TXNRX(rf module)
+#   27      GPIO47      207_DQ0(rf module)
+#   28      GPIO48      207_DQ1(rf module)
+#   29      GPIO49      207_DQ2(rf module)
+#   30      gpio27      testp(pa module warning) key2(press down is low)
+#   31      tms\gpio01  pc_led\d_rst            jtag_tms
+#   32      tck\gpio00  tx_led                  jtag_tck
+#   33      tdo\gpio03  rx_led                  jtag tdo
+#   34      tdi\gpio02  uart1_tx\pa_led         jtag tdi
+#   35      trst\gpio04 uart1_rx\pb_led         jtag trst
+#   36      GPIO07      LNA_GAIN_CTR0(pa module)
+#   39      gpio06\tx0  uart0_tx                ir_tx
+#   40      gpio05\rx0  uart0_rx                ir_rx
+#   41      GPIO08      LNA_GAIN_CTR1(pa module)
+#   42      GPIO26      LNA_GAIN_CTR2(pa module)
+#   51      GPIO50      207_DQ3(rf module)
+#   52      GPIO51      207_DQ4(rf module)
+#   53      GPIO52      207_DQ5(rf module)
+#   54      GPIO53      207_DQ6(rf module)
+#   55      GPIO54      207_DQ7(rf module)
+#   56      GPIO55      207_DQ8(rf module)
+#   57      GPIO56      207_DQ9(rf module)
+#   58      GPIO57      207_DQ10(rf module)
+#   59      GPIO58      207_DQ11(rf module)
+#   60      GPIO59      RF_PD(rf module)
+#   61      GPIO61      SW_VC2(rf module, send and receive mode transitions)
+#   62      GPIO62      SW_VC1(rf module, send and receive mode transitions)
+#   68      ADC0/GPIO64 ZA_DOWN(phase A zero-cross, falling edge)
+#   69      ADC1/GPIO65 ZC_DOWN(phase C zero-cross, falling edge)
+#   70      ADC2/GPIO66 ZB_DOWN(phase B zero-cross, falling edge)
+#   71      ADC3/GPIO67 ZC_RISE(phase C zero-cross, rising edge)
+#   72      ADC4/GPIO68 ZB_RISE(phase B zero-cross, rising edge)
+#   73      ADC5/GPIO69 ZA_RISE(phase A zero-cross, rising edge)
+#   76      GPIO12      RF_SPI_CLK(rf module)
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    # bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    #33 1   x   #does not support gpio for in place detection
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   0   #GPIO_PLC_EVENT
+    30  1   1   #GPIO_STA_OUT
+
+    27  1   10  #GPIO_GEODE_OVT
+
+    64  1   18  #GPIO_PA_ZC
+    66  1   19  #GPIO_PB_ZC
+    65  1   20  #GPIO_PC_ZC
+    69  1   44  #GPIO_PA_ZC_EXT
+    68  1   45  #GPIO_PB_ZC_EXT
+    67  1   46  #GPIO_PC_ZC_EXT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    #plc-core print
+    1   1   0   #UART_PRINT
+    tx  2
+
+    #cus-core print
+    2   0   0   #UART_PRINT
+    tx  4
+
+    3   1   1   #UART_CLI_PORT
+    tx  29
+    rx  28
+
+    6   0   14  #UART_ICC_PORT
+    tx  60
+    rx  63
+    rts 40
+    cts 14
+
+    7   1   14  #UART_ICC_PORT
+    tx  63
+    rx  60
+    rts 14
+    cts 40
+
+spi     #SPI resource allocation
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    # bbcpu use spi1 to connect external rf chip, fixed value used now.
+    1   2   0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    # sampling of gnd, but 12v\3v samples are not designed,
+    # power mgmt is invalid
+    1   1   1   #ADC_PM_GND
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  0
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  3
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  1
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+    #up_0    64
+    #up_1    66
+    #up_2    65
+    #down_0  69
+    #down_1  68
+    #down_2  67
+
+pa  # (PARTICULAR RESOURCE)
+    tx_en_0 35  #Phase A Enable receiving
+    rx_en_0 34  #Phase A Enable sending
+    tx_en_1 37  #Phase B Enable receiving
+    rx_en_1 36  #Phase B Enable sending
+    tx_en_2 39  #Phase C Enable receiving
+    rx_en_2 38  #Phase C Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+# Fixed Signal Of Board are defined in code(board_special_signal_mtx_binding)
+#rf
+#    mclk    42
+#    fclk    43
+#    gain    46
+#    enable  45
+#    txnrx   44
+#    pd      59
+#    dq0     47
+#    dq1     48
+#    dq2     49
+#    dq3     50
+#    dq4     51
+#    dq5     52
+#    dq6     53
+#    dq7     54
+#    dq8     55
+#    dq9     56
+#    dq10    57
+#    dq11    58
+
diff --git a/tools/oem/EVB3201CCO03_OEM.ini b/tools/oem/EVB3201CCO03_OEM.ini
new file mode 100644
index 0000000..472f7bd
--- /dev/null
+++ b/tools/oem/EVB3201CCO03_OEM.ini
@@ -0,0 +1,201 @@
+# kl3 k76 evb board, some pins have two functions,
+# the second function is shielded, only one function can be enabled at a time.
+
+general
+    bid     49  #BOARD_EVB3201
+    mid     1   #cco
+    vid     WQ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name    func_default            func_2
+#   1       GPIO11      RF_SPI_DI(rf module)
+#   2       GPIO10      RF_SPI_DO(rf module)
+#   3       GPIO09      RF_SPI_CS(rf module)
+#   4       GPIO42      207_MCLK(rf module)
+#   5       GPIO43      207_FCLK(rf module)
+#   8       GPIO39      pc_tx_en(pa module)     spi_cs(extern flash)
+#   9       GPIO38      pc_rx_en(pa module)     spi_clk(extern flash)
+#   10      GPIO37      pb_tx_en(pa module)     spi_d1(extern flash)
+#   11      GPIO36      pb_rx_en(pa module)     spi_d2(extern flash)
+#   12      GPIO35      pa_tx_en(pa module)     spi_d0(extern flash)
+#   13      GPIO34      pa_rx_en(pa module)     spi_d3(extern flash)
+#   14      GPIO33      m_sta(in place detect)  key1(press down is low)
+#   15      gpio32      set(sta)                i2c_scl(lm75bdp)
+#   16      gpio31      event                   i2c_sda(lm75bdp)
+#   18      gpio30      sta0                    485_ctr
+#   19      gpio29      uart2_tx                485_tx
+#   20      gpio28      uart2_rx                485_rx
+#   24      GPIO46      AGC_GAIN(rf module)
+#   25      GPIO45      207_ENABLE(rf module)
+#   26      GPIO44      207_TXNRX(rf module)
+#   27      GPIO47      207_DQ0(rf module)
+#   28      GPIO48      207_DQ1(rf module)
+#   29      GPIO49      207_DQ2(rf module)
+#   30      gpio27      testp(pa module warning) key2(press down is low)
+#   31      tms\gpio01  pc_led\d_rst            jtag_tms
+#   32      tck\gpio00  tx_led                  jtag_tck
+#   33      tdo\gpio03  rx_led                  jtag tdo
+#   34      tdi\gpio02  uart1_tx\pa_led         jtag tdi
+#   35      trst\gpio04 uart1_rx\pb_led         jtag trst
+#   36      GPIO07      LNA_GAIN_CTR0(pa module)
+#   39      gpio06\tx0  uart0_tx                ir_tx
+#   40      gpio05\rx0  uart0_rx                ir_rx
+#   41      GPIO08      LNA_GAIN_CTR1(pa module)
+#   42      GPIO26      LNA_GAIN_CTR2(pa module)
+#   51      GPIO50      207_DQ3(rf module)
+#   52      GPIO51      207_DQ4(rf module)
+#   53      GPIO52      207_DQ5(rf module)
+#   54      GPIO53      207_DQ6(rf module)
+#   55      GPIO54      207_DQ7(rf module)
+#   56      GPIO55      207_DQ8(rf module)
+#   57      GPIO56      207_DQ9(rf module)
+#   58      GPIO57      207_DQ10(rf module)
+#   59      GPIO58      207_DQ11(rf module)
+#   60      GPIO59      RF_PD(rf module)
+#   61      GPIO61      SW_VC2(rf module, send and receive mode transitions)
+#   62      GPIO62      SW_VC1(rf module, send and receive mode transitions)
+#   68      ADC0/GPIO64 ZA_DOWN(phase A zero-cross, falling edge)
+#   69      ADC1/GPIO65 ZC_DOWN(phase C zero-cross, falling edge)
+#   70      ADC2/GPIO66 ZB_DOWN(phase B zero-cross, falling edge)
+#   71      ADC3/GPIO67 ZC_RISE(phase C zero-cross, rising edge)
+#   72      ADC4/GPIO68 ZB_RISE(phase B zero-cross, rising edge)
+#   73      ADC5/GPIO69 ZA_RISE(phase A zero-cross, rising edge)
+#   76      GPIO12      RF_SPI_CLK(rf module)
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    # bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    #33 1   x   #does not support gpio for in place detection
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   0   #GPIO_PLC_EVENT
+    30  1   1   #GPIO_STA_OUT
+
+    27  1   10  #GPIO_GEODE_OVT
+
+    64  1   18  #GPIO_PA_ZC
+    66  1   19  #GPIO_PB_ZC
+    65  1   20  #GPIO_PC_ZC
+    69  1   44  #GPIO_PA_ZC_EXT
+    68  1   45  #GPIO_PB_ZC_EXT
+    67  1   46  #GPIO_PC_ZC_EXT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    1   1   0   #UART_PRINT
+    tx  2
+    rx  4
+
+    2   1   1   #UART_CLI_PORT
+    tx  29
+    rx  28
+
+spi     #SPI resource allocation
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    # bbcpu use spi1 to connect external rf chip, fixed value used now.
+    1   2   0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    # sampling of gnd, but 12v\3v samples are not designed,
+    # power mgmt is invalid
+    1   1   1   #ADC_PM_GND
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  0
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  3
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  1
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+    #up_0    64
+    #up_1    66
+    #up_2    65
+    #down_0  69
+    #down_1  68
+    #down_2  67
+
+pa  # (PARTICULAR RESOURCE)
+    tx_en_0 35  #Phase A Enable receiving
+    rx_en_0 34  #Phase A Enable sending
+    tx_en_1 37  #Phase B Enable receiving
+    rx_en_1 36  #Phase B Enable sending
+    tx_en_2 39  #Phase C Enable receiving
+    rx_en_2 38  #Phase C Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+# Fixed Signal Of Board are defined in code(board_special_signal_mtx_binding)
+#rf
+#    mclk    42
+#    fclk    43
+#    gain    46
+#    enable  45
+#    txnrx   44
+#    pd      59
+#    dq0     47
+#    dq1     48
+#    dq2     49
+#    dq3     50
+#    dq4     51
+#    dq5     52
+#    dq6     53
+#    dq7     54
+#    dq8     55
+#    dq9     56
+#    dq10    57
+#    dq11    58
diff --git a/tools/oem/EVB3201CCO03_RFIN_OEM.ini b/tools/oem/EVB3201CCO03_RFIN_OEM.ini
new file mode 100644
index 0000000..2010a0d
--- /dev/null
+++ b/tools/oem/EVB3201CCO03_RFIN_OEM.ini
@@ -0,0 +1,185 @@
+# kl3 k76 RFIN evb board.
+
+# Some pins have multiple functions that can only be enabled one at a time,
+# and their functions are blocked.
+
+general
+    bid     97  #BOARD_EVB3201RFIN
+    mid     1 #MODULE_TYPE_CCO
+    vid     HZ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name            func_default    func_2                  func_3
+#   1       ADC5/GPIO69         ZC_RISE(Phase C rising edge zero-crossing signal)
+#   2       ADC6/GPIO70         NC
+#   3       ADC7/GPIO71         ADC_CC(DC current sampling single-ended input (0-2.25V))
+#   8       GPIO39              485_RXD         SPI_CS(spi_flash)
+#   9       GPIO38              485_TXD         SPI_DO(spi_flash)
+#   10      GPIO37              485_CTR         SPI_DI(spi_flash)
+#   12      GPIO36              RXD_BUG2        SPI_CLK(spi_flash)     I2C_SDA
+#   13      GPIO35              TXD_BUG2        I2C_SCL
+#   14      GPIO34              LNA_GAIN_CTR0
+#   15      GPIO33              LNA_GAIN_CTR1
+#   16      GPIO32              LNA_GAIN_CTR2
+#   17      GPIO31              PA_RX_EN
+#   19      GPIO30              PA_TX_EN
+#   20      GPIO14              PB_RX_EN
+#   21      GPIO29              PB_TX_EN
+#   22      GPIO28              PC_RX_EN
+#   26      GPIO27              PC_TX_EN
+#   28      GPIO01\TMS          JTAG_TMS
+#   29      GPIO00\TCK          JTAG_TCK        KEY_1(press down is low)
+#   30      GPIO03\TDO          JTAG_TDO        TXD_BUG1
+#   31      GPIO02\TDI          JTAG_TDI        RXD_BUG1
+#   32      GPIO04\TRST         JTAG_TRST       TX_LED(low light)
+#   33      GPIO07              RX_LED(low light)
+#   36      GPIO06              UART0_TXD       IR_RX
+#   37      GPIO05              UART0_RXD       IR_TX
+#   38      GPIO08              TESTP(pa module warning)
+#   39      GPIO26              SW_VC1(rf module, send and receive mode transitions)
+#   40      GPIO40              SW_VC2(rf module, send and receive mode transitions)
+#   50      TPID_ADC5\GPIO77    AP(Phase A current acquisition/branch identification +)
+#   51      TPID_ADC4\GPIO76    AN(Phase A current acquisition/branch identification -)
+#   52      TPID_ADC3\GPIO75    BP(Phase B current acquisition/branch identification +)
+#   53      TPID_ADC2\GPIO74    BN(Phase B current acquisition/branch identification -)
+#   54      TPID_ADC1\GPIO73    CP(Phase C current acquisition/branch identification +)
+#                               NP(DC current sampling 30mV +)
+#   55      TPID_ADC0\GPIO72    CN(Phase C current acquisition/branch identification -)
+#                               NN(DC current sampling 30mV -)
+#   74      ADC2\GPIO66         ZA_LOAD(Station area identification zero-crossing signal)
+#   75      ADC3\GPIO67         ZA_RISE(Phase A rising edge zero-crossing signal)
+#   76      ADC4\GPIO68         ZB_RISE(Phase B rising edge zero-crossing signal)
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    67  1   18  #GPIO_PA_ZC
+    68  1   19  #GPIO_PB_ZC
+    69  1   20  #GPIO_PC_ZC
+
+    #RF SPI (芯片内部未引出)
+    9   1   107 #GPIO_SPI_RF_CLK
+    10  1   110 #GPIO_SPI_RF_MOSI
+    11  1   109 #GPIO_SPI_RF_MISO
+    12  1   108 #GPIO_SPI_RF_CS
+
+    37  1   7   #GPIO_RS485_TXE
+
+#    5  1   8   #GPIO_IR_TXD
+#    6  1   9   #GPIO_IR_RXD
+
+    8   1   10  #GPIO_GEODE_OVT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    1   1   0   #UART_PRINT
+    tx  3
+    rx  2
+
+    2   1   1   #UART_CLI_PORT
+    tx  35
+    rx  36
+
+    3   1   4   #UART_RS485_PORT
+    tx  38
+    rx  39
+
+#spi     #SPI resource allocation. Controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  39
+#   clk 36
+#   miso 37
+#   mosi 38
+
+i2c     #I2C resource allocation
+#  A:i2c number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#    0   1   0   #IOT_I2C_PORT_0
+#    scl 35
+#    sda 36
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#    0   1   0   #IOT_PLC_TX_LED
+#    ledout  4
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  7
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#    allocation. Controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+
+pa  # (PARTICULAR RESOURCE)
+#  A:PA function name;
+#  B:PA gpio number;
+#   A       B
+    rx_en_0 31  #Phase A Enable receiving
+    tx_en_0 30  #Phase A Enable sending
+    rx_en_1 14  #Phase B Enable receiving
+    tx_en_1 29  #Phase B Enable sending
+    rx_en_2 28  #Phase C Enable receiving
+    tx_en_2 27  #Phase C Enable sending
+    gain_0  34  #Gain control of bit 0
+    gain_1  33  #Gain control of bit 1
+    gain_2  32  #Gain control of bit 2
+
+pwm        #PWM resource allocation
+#  A:pwm编号
+#  B:所属core
+#  C:用途(见iot_board_api.h中的PWM_CH_TYPE_TSFM_XXX)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIOXX和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+#    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
diff --git a/tools/oem/EVB32113PS03_OEM.ini b/tools/oem/EVB32113PS03_OEM.ini
new file mode 100644
index 0000000..36d3fb1
--- /dev/null
+++ b/tools/oem/EVB32113PS03_OEM.ini
@@ -0,0 +1,161 @@
+# kl3 k76 evb board, some pins have two functions,
+# the second function is shielded, only one function can be enabled at a time.
+
+general
+    bid     50  #BOARD_EVB3211
+    mid     4   #3ps
+    vid     WQ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name    func_default            func_2
+#   1       GPIO11      RF_SPI_DI(rf module)
+#   2       GPIO10      RF_SPI_DO(rf module)
+#   3       GPIO09      RF_SPI_CS(rf module)
+#   4       GPIO42      207_MCLK(rf module)
+#   5       GPIO43      207_FCLK(rf module)
+#   8       GPIO39      pc_tx_en(pa module)     spi_cs(extern flash)
+#   9       GPIO38      pc_rx_en(pa module)     spi_clk(extern flash)
+#   10      GPIO37      pb_tx_en(pa module)     spi_d1(extern flash)
+#   11      GPIO36      pb_rx_en(pa module)     spi_d2(extern flash)
+#   12      GPIO35      pa_tx_en(pa module)     spi_d0(extern flash)
+#   13      GPIO34      pa_rx_en(pa module)     spi_d3(extern flash)
+#   14      GPIO33      m_sta(in place detect)  key1(press down is low)
+#   15      gpio32      set(sta)                i2c_scl(lm75bdp)
+#   16      gpio31      event                   i2c_sda(lm75bdp)
+#   18      gpio30      sta0                    485_ctr
+#   19      gpio29      uart2_tx                485_tx
+#   20      gpio28      uart2_rx                485_rx
+#   24      GPIO46      AGC_GAIN(rf module)
+#   25      GPIO45      207_ENABLE(rf module)
+#   26      GPIO44      207_TXNRX(rf module)
+#   27      GPIO47      207_DQ0(rf module)
+#   28      GPIO48      207_DQ1(rf module)
+#   29      GPIO49      207_DQ2(rf module)
+#   30      gpio27      testp(pa module warning) key2(press down is low)
+#   31      tms\gpio01  pc_led\d_rst            jtag_tms
+#   32      tck\gpio00  tx_led                  jtag_tck
+#   33      tdo\gpio03  rx_led                  jtag tdo
+#   34      tdi\gpio02  uart1_tx\pa_led         jtag tdi
+#   35      trst\gpio04 uart1_rx\pb_led         jtag trst
+#   36      GPIO07      LNA_GAIN_CTR0(pa module)
+#   39      gpio06\tx0  uart0_tx                ir_tx
+#   40      gpio05\rx0  uart0_rx                ir_rx
+#   41      GPIO08      LNA_GAIN_CTR1(pa module)
+#   42      GPIO26      LNA_GAIN_CTR2(pa module)
+#   51      GPIO50      207_DQ3(rf module)
+#   52      GPIO51      207_DQ4(rf module)
+#   53      GPIO52      207_DQ5(rf module)
+#   54      GPIO53      207_DQ6(rf module)
+#   55      GPIO54      207_DQ7(rf module)
+#   56      GPIO55      207_DQ8(rf module)
+#   57      GPIO56      207_DQ9(rf module)
+#   58      GPIO57      207_DQ10(rf module)
+#   59      GPIO58      207_DQ11(rf module)
+#   60      GPIO59      RF_PD(rf module)
+#   61      GPIO61      SW_VC2(rf module, send and receive mode transitions)
+#   62      GPIO62      SW_VC1(rf module, send and receive mode transitions)
+#   68      ADC0/GPIO64 ZA_DOWN(phase A zero-cross, falling edge)
+#   69      ADC1/GPIO65 ZC_DOWN(phase C zero-cross, falling edge)
+#   70      ADC2/GPIO66 ZB_DOWN(phase B zero-cross, falling edge)
+#   71      ADC3/GPIO67 ZC_RISE(phase C zero-cross, rising edge)
+#   72      ADC4/GPIO68 ZB_RISE(phase B zero-cross, rising edge)
+#   73      ADC5/GPIO69 ZA_RISE(phase A zero-cross, rising edge)
+#   76      GPIO12      RF_SPI_CLK(rf module)
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    # bbcup spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    #33 1   x   #does not support gpio for in place detection
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   0   #GPIO_PLC_EVENT
+    30  1   1   #GPIO_STA_OUT
+
+    27  1   10  #GPIO_GEODE_OVT
+
+    64  1   18  #GPIO_PA_ZC
+    66  1   19  #GPIO_PB_ZC
+    65  1   20  #GPIO_PC_ZC
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    1   1   0   #UART_PRINT
+    tx  2
+    rx  4
+
+    2   1   1   #UART_CLI_PORT
+    tx  29
+    rx  28
+
+spi     #SPI resource allocation
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    # bbcpu use spi1 to connect external rf chip, fixed value used now.
+    1   2   0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    # sampling of gnd, but 12v\3v samples are not designed,
+    # power mgmt is invalid
+    1   1   1   #ADC_PM_GND
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  0
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  3
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  1
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+    #up_0    64
+    #up_1    66
+    #up_2    65
+
+pa  # (PARTICULAR RESOURCE)
+    tx_en_0 35  #Phase A Enable receiving
+    rx_en_0 34  #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
\ No newline at end of file
diff --git a/tools/oem/EVB3211STA03_OEM.ini b/tools/oem/EVB3211STA03_OEM.ini
new file mode 100644
index 0000000..43ec202
--- /dev/null
+++ b/tools/oem/EVB3211STA03_OEM.ini
@@ -0,0 +1,151 @@
+# kl3 k76 evb board, some pins have two functions,
+# the second function is shielded, only one function can be enabled at a time.
+
+general
+    bid     50  #BOARD_EVB3211
+    mid     0   #sta
+    vid     WQ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name    func_default            func_2
+#   1       GPIO11      RF_SPI_DI(rf module)
+#   2       GPIO10      RF_SPI_DO(rf module)
+#   3       GPIO09      RF_SPI_CS(rf module)
+#   4       GPIO42      207_MCLK(rf module)
+#   5       GPIO43      207_FCLK(rf module)
+#   8       GPIO39      pc_tx_en(pa module)     spi_cs(extern flash)
+#   9       GPIO38      pc_rx_en(pa module)     spi_clk(extern flash)
+#   10      GPIO37      pb_tx_en(pa module)     spi_d1(extern flash)
+#   11      GPIO36      pb_rx_en(pa module)     spi_d2(extern flash)
+#   12      GPIO35      pa_tx_en(pa module)     spi_d0(extern flash)
+#   13      GPIO34      pa_rx_en(pa module)     spi_d3(extern flash)
+#   14      GPIO33      m_sta(in place detect)  key1(press down is low)
+#   15      gpio32      set(sta)                i2c_scl(lm75bdp)
+#   16      gpio31      event                   i2c_sda(lm75bdp)
+#   18      gpio30      sta0                    485_ctr
+#   19      gpio29      uart2_tx                485_tx
+#   20      gpio28      uart2_rx                485_rx
+#   24      GPIO46      AGC_GAIN(rf module)
+#   25      GPIO45      207_ENABLE(rf module)
+#   26      GPIO44      207_TXNRX(rf module)
+#   27      GPIO47      207_DQ0(rf module)
+#   28      GPIO48      207_DQ1(rf module)
+#   29      GPIO49      207_DQ2(rf module)
+#   30      gpio27      testp(pa module warning) key2(press down is low)
+#   31      tms\gpio01  pc_led\d_rst            jtag_tms
+#   32      tck\gpio00  tx_led                  jtag_tck
+#   33      tdo\gpio03  rx_led                  jtag tdo
+#   34      tdi\gpio02  uart1_tx\pa_led         jtag tdi
+#   35      trst\gpio04 uart1_rx\pb_led         jtag trst
+#   36      GPIO07      LNA_GAIN_CTR0(pa module)
+#   39      gpio06\tx0  uart0_tx                ir_tx
+#   40      gpio05\rx0  uart0_rx                ir_rx
+#   41      GPIO08      LNA_GAIN_CTR1(pa module)
+#   42      GPIO26      LNA_GAIN_CTR2(pa module)
+#   51      GPIO50      207_DQ3(rf module)
+#   52      GPIO51      207_DQ4(rf module)
+#   53      GPIO52      207_DQ5(rf module)
+#   54      GPIO53      207_DQ6(rf module)
+#   55      GPIO54      207_DQ7(rf module)
+#   56      GPIO55      207_DQ8(rf module)
+#   57      GPIO56      207_DQ9(rf module)
+#   58      GPIO57      207_DQ10(rf module)
+#   59      GPIO58      207_DQ11(rf module)
+#   60      GPIO59      RF_PD(rf module)
+#   61      GPIO61      SW_VC2(rf module, send and receive mode transitions)
+#   62      GPIO62      SW_VC1(rf module, send and receive mode transitions)
+#   68      ADC0/GPIO64 ZA_DOWN(phase A zero-cross, falling edge)
+#   69      ADC1/GPIO65 ZC_DOWN(phase C zero-cross, falling edge)
+#   70      ADC2/GPIO66 ZB_DOWN(phase B zero-cross, falling edge)
+#   71      ADC3/GPIO67 ZC_RISE(phase C zero-cross, rising edge)
+#   72      ADC4/GPIO68 ZB_RISE(phase B zero-cross, rising edge)
+#   73      ADC5/GPIO69 ZA_RISE(phase A zero-cross, rising edge)
+#   76      GPIO12      RF_SPI_CLK(rf module)
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    # bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    #33 1   x   #does not support gpio for in place detection
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   0   #GPIO_PLC_EVENT
+    30  1   1   #GPIO_STA_OUT
+
+    27  1   10  #GPIO_GEODE_OVT
+
+    64  1   18  #GPIO_PA_ZC
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    1   1   0   #UART_PRINT
+    tx  2
+    rx  4
+
+    2   1   1   #UART_CLI_PORT
+    tx  29
+    rx  28
+
+spi     #SPI resource allocation
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    # bbcpu use spi1 to connect external rf chip, fixed value used now.
+    1   2   0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    # sampling of gnd, but 12v\3v samples are not designed,
+    # power mgmt is invalid
+    1   1   1   #ADC_PM_GND
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function  #
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  0
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  3
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  1
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+    #up_0    64
+
+pa  # (PARTICULAR RESOURCE)
+    tx_en_0 35  #Phase A Enable receiving
+    rx_en_0 34  #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
\ No newline at end of file
diff --git a/tools/oem/EVB3211STA03_RFIN_OEM.ini b/tools/oem/EVB3211STA03_RFIN_OEM.ini
new file mode 100644
index 0000000..bef04a5
--- /dev/null
+++ b/tools/oem/EVB3211STA03_RFIN_OEM.ini
@@ -0,0 +1,194 @@
+# kl3 k76 RFIN evb board.
+
+# Some pins have multiple functions that can only be enabled one at a time,
+# and their functions are blocked.
+
+general
+    bid     98  #BOARD_EVB3211RFIN
+    mid     0 #MODULE_TYPE_STA
+    vid     HZ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name            func_default    func_2                  func_3
+#   1       ADC7\GPIO71         V_FAST_DROP(Voltage fast drop input)
+#   5       GPIO22              ZA_LOAD
+#   6       GPIO67              ZA_RISE
+#   7       GPIO23              SPI2_CS(spi_flash)
+#   8       GPIO21              SPI2_DO(spi_flash MOSI)
+#   9       GPIO20              SPI2_DI(spi_flash MISO)
+#   10      GPIO25              SPI2_CLK(spi_flash)
+#   11      GPIO39              485_RXD         SPI_CS(spi_flash)
+#   12      GPIO38              485_TXD         SPI_D1(spi_flash)
+#   13      GPIO37              485_CTR         SPI_D2(spi_flash)
+#   14      GPIO36              I2C_SDA         SPI_D0(spi_flash)
+#   15      GPIO35              I2C_SCL         SPI_CLK(spi_flash)
+#   16      GPIO34              NC              SPI_D3(spi_flash)
+#   17      GPIO33              KEY_1(press down is low)
+#   18      GPIO32              SEND(small load emission)
+#   19      GPIO31              UART2_TXD
+#   21      GPIO30              UART2_RXD
+#   22      GPIO29              UART1_TXD
+#   26      GPIO27              UART1_RXD
+#   28      GPIO01\TMS          JTAG_TMS
+#   29      GPIO00\TCK          JTAG_TCK
+#   30      GPIO03\TDO          JTAG TDO        TX_LED(low light)
+#   31      GPIO02\TDI          JTAG TDI        RX_LED(low light)
+#   32      GPIO04\TRST         JTAG TRST       IR_TX
+#   33      GPIO07              IR_RX
+#   35      GPIO06              UART0_TXD
+#   36      GPIO05              UART0_RXD
+#   37      GPIO08              NC
+#   39      GPIO26              SW_VC1(rf module, send and receive mode transitions)
+#   40      GPIO40              SW_VC2(rf module, send and receive mode transitions)
+#   50      TPID_ADC5\GPIO77    AP(Phase A current acquisition/branch identification +)
+#                               NP(DC current sampling 30mV +)
+#   51      TPID_ADC4\GPIO76    AN(Phase A current acquisition/branch identification -)
+#                               NN(DC current sampling 30mV -)
+#   52      TPID_ADC3\GPIO75    BP(Phase B current acquisition/branch identification +)
+#   53      TPID_ADC2\GPIO74    BN(Phase B current acquisition/branch identification -)
+#   54      TPID_ADC1\GPIO73    CP(Phase C current acquisition/branch identification +)
+#   55      TPID_ADC0\GPIO72    CN(Phase C current acquisition/branch identification -)
+#   72      ADC2\GPIO66         ZA_RISE(Phase A rising edge zero-crossing signal)
+#   73      ADC3\GPIO67         ZA_LOAD(Station area identification zero-crossing signal)
+#   74      ADC4\GPIO68         NC
+#   75      ADC5\GPIO69         V_A(220V voltage measurement)
+#   76      ADC6/GPIO70         ADC_CC(DC current sampling single-ended input (0-2.25V))
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    25  1   68  #GPIO_SPI_FLASH_CLK
+    23  1   69  #GPIO_SPI_FLASH_CS
+    21  1   70  #GPIO_SPI_FLASH_MOSI
+    20  1   71  #GPIO_SPI_FLASH_MISO
+
+    #RF SPI (芯片内部未引出)
+    9   1   107 #GPIO_SPI_RF_CLK
+    10  1   110 #GPIO_SPI_RF_MOSI
+    11  1   109 #GPIO_SPI_RF_MISO
+    12  1   108 #GPIO_SPI_RF_CS
+
+    37  1   7   #GPIO_RS485_TXE
+
+    #load send gpio
+    32  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+    4   1   8   #GPIO_IR_TXD
+    7   1   9   #GPIO_IR_RXD
+
+    67  1   18  #GPIO_PA_ZC
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    3   1   4   #UART_RS485_PORT
+    tx  38
+    rx  39
+
+    2   1   1   #UART_CLI_PORT
+    tx  31
+    rx  30
+
+    1   1   0   #UART_PRINT
+    tx  29
+    rx  27
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    4   1   3   #UART_IR_PORT
+    tx  4
+    rx  7
+
+#spi     #SPI resource allocation. Controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  39
+#   clk 36
+#   miso 37
+#   mosi 38
+
+i2c     #I2C resource allocation
+#  A:i2c number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_I2C_PORT_0
+    scl 35
+    sda 36
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  3
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  2
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#    allocation. Controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+
+pa  # (PARTICULAR RESOURCE)
+#  A:PA function name;
+#  B:PA gpio number;
+#   A       B
+    rx_en_0 80  #enlic_pad_0. Phase A Enable receiving
+    tx_en_0 81  #enlic_pad_1. Phase A Enable sending
+    gain_0  82  #glna_pad_0. Phase A gain control
+    gain_1  83  #glna_pad_1. Phase B gain control
+    gain_2  84  #glna_pad_2. Phase C gain control
+
+pwm        #PWM resource allocation
+#  A:pwm编号
+#  B:所属core
+#  C:用途(见iot_board_api.h中的PWM_CH_TYPE_TSFM_XXX)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO32和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+
diff --git a/tools/oem/EVB5202I3C03_OEM.ini b/tools/oem/EVB5202I3C03_OEM.ini
new file mode 100644
index 0000000..7b0062f
--- /dev/null
+++ b/tools/oem/EVB5202I3C03_OEM.ini
@@ -0,0 +1,191 @@
+# kl3 k76 evb board, some pins have two functions,
+# the second function is shielded, only one function can be enabled at a time.
+
+general
+    bid     84  #BOARD_EVB5202
+    mid     2 #MODULE_TYPE_COLLECTOR_II
+    vid     HZ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name            func_default            func_2
+#   3       GPIO12              485_RXD
+#   4       GPIO11              485_TXD
+#   5       GPIO10              485_CTR
+#   6       GPIO09              I2C_SDA
+#   7       GPIO42              I2C_SCL
+#   8       GPIO43              NC
+#   10      GPIO39              SPI_CS(spi_flash)
+#   11      GPIO38              SPI_D1(spi_flash MISO)
+#   12      GPIO37              SPI_D2(spi_flash)
+#   13      GPIO36              SPI_D0(spi_flash MOSI)
+#   14      GPIO35              SPI_CLK(spi_flash)
+#   15      GPIO34              SPI_D3(spi_flash)
+#   16      GPIO33              FAST_BOOT               KEY_2(press down is low)
+#   17      GPIO32              KEY_1(press down is low)
+#   18      GPIO31              SEND
+#   23      GPIO46              UART2_TXD
+#   24      GPIO45              UART2_RXD
+#   25      GPIO44              UART1_TXD
+#   26      GPIO27              UART1_RXD
+#   28      GPIO01\TMS          JTAG_TMS
+#   29      GPIO00\TCK          JTAG_TCK
+#   30      GPIO03\TDO          JTAG TDO
+#   31      GPIO02\TDI          JTAG TDI
+#   32      GPIO04\TRST         JTAG TRST
+#   33      GPIO07              NC
+#   35      GPIO06\TX0          UART0_TXD
+#   36      GPIO05\RX0          UART0_RXD
+#   37      GPIO08              NC
+#   39      GPIO26              NC
+#   40      GPIO40              NC
+#   50      TPID_ADC7\GPIO79    AP(Phase A current acquisition/branch identification +)
+#   51      TPID_ADC6\GPIO78    AN(Phase A current acquisition/branch identification -)
+#   52      TPID_ADC5\GPIO77    BP(Phase B current acquisition/branch identification +)
+#   53      TPID_ADC4\GPIO76    BN(Phase B current acquisition/branch identification -)
+#   54      TPID_ADC3\GPIO75    CP(Phase C current acquisition/branch identification +)
+#   55      TPID_ADC2\GPIO74    CN(Phase C current acquisition/branch identification -)
+#   56      TPID_ADC1\GPIO73    NP(DC current sampling 30mV +)
+#   57      TPID_ADC0\GPIO72    NN(DC current sampling 30mV -)
+#   59      GPIO55              IR_RX
+#   60      GPIO57              IR_TX
+#   61      GPIO59              RX_LED(low light)
+#   62      GPIO63              TX_LED(low light)
+#   69      ADC0\GPIO64         NC
+#   70      ADC1\GPIO65         ZA_RISE(Phase A rising edge zero-crossing signal)
+#   71      ADC2\GPIO66         ZA_LOAD(Station area identification zero-crossing signal)
+#   72      ADC3\GPIO67         VA(Phase A voltage acquisition)
+#   73      ADC4\GPIO68         VB(Phase B voltage acquisition, actual phase A voltage)
+#   74      ADC5\GPIO69         VC(Phase C voltage acquisition, actual phase A voltage)
+#   75      ADC6\GPIO70         ADC_CC(DC current sampling single-ended input (0-2.25V))
+#   76      ADC7\GPIO71         V_FAST_DROP(Voltage fast drop input)
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    35  1   68  #GPIO_SPI_FLASH_CLK
+    39  1   69  #GPIO_SPI_FLASH_CS
+    36  1   70  #GPIO_SPI_FLASH_MOSI
+    38  1   71  #GPIO_SPI_FLASH_MISO
+#   37  1       #D2
+#   34  1       #D3
+
+#   load send gpio
+    31  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+    57  1   8   #GPIO_IR_TXD
+    55  1   9   #GPIO_IR_RXD
+
+    65  1   18  #GPIO_PA_ZC
+
+    10  1   7   #GPIO_RS485_TXE
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    4   1   3   #UART_IR_PORT
+    tx  57
+    rx  55
+
+    3   1   4   #UART_RS485_PORT
+    tx  11
+    rx  12
+
+    2   1   1   #UART_CLI_PORT
+    tx  46
+    rx  45
+
+    1   1   0   #UART_PRINT
+    tx  44
+    rx  27
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+#spi     #SPI resource allocation. Controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+i2c     #I2C resource allocation
+#  A:i2c number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_I2C_PORT_0
+    scl 42
+    sda 9
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  63
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  59
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#    allocation. Controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+#   up_0    65
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 80  #enlic_pad_0. Phase A Enable receiving
+    tx_en_0 81  #enlic_pad_1. Phase A Enable sending
+    gain_0  82  #glna_pad_0. Gain control of bit 0
+    gain_1  83  #glna_pad_1. Gain control of bit 1
+    gain_2  84  #glna_pad_2. Gain control of bit 2
+
+pwm        #PWM resource allocation
+#  A:pwm编号
+#  B:所属core
+#  C:用途(见iot_board_api.h中的PWM_CH_TYPE_TSFM_XXX)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
diff --git a/tools/oem/EVB5202STA03_OEM.ini b/tools/oem/EVB5202STA03_OEM.ini
new file mode 100644
index 0000000..516cf48
--- /dev/null
+++ b/tools/oem/EVB5202STA03_OEM.ini
@@ -0,0 +1,187 @@
+# kl3 k76 evb board, some pins have two functions,
+# the second function is shielded, only one function can be enabled at a time.
+
+general
+    bid     84  #BOARD_EVB5202
+    mid     0   #MODULE_TYPE_STA
+    vid     HZ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name            func_default            func_2
+#   3       GPIO12              485_RXD
+#   4       GPIO11              485_TXD
+#   5       GPIO10              485_CTR
+#   6       GPIO09              I2C_SDA
+#   7       GPIO42              I2C_SCL
+#   8       GPIO43              NC
+#   10      GPIO39              SPI_CS(spi_flash)
+#   11      GPIO38              SPI_D1(spi_flash MISO)
+#   12      GPIO37              SPI_D2(spi_flash)
+#   13      GPIO36              SPI_D0(spi_flash MOSI)
+#   14      GPIO35              SPI_CLK(spi_flash)
+#   15      GPIO34              SPI_D3(spi_flash)
+#   16      GPIO33              FAST_BOOT               KEY_2(press down is low)
+#   17      GPIO32              KEY_1(press down is low)
+#   18      GPIO31              SEND
+#   23      GPIO46              UART2_TXD
+#   24      GPIO45              UART2_RXD
+#   25      GPIO44              UART1_TXD
+#   26      GPIO27              UART1_RXD
+#   28      GPIO01\TMS          JTAG_TMS
+#   29      GPIO00\TCK          JTAG_TCK
+#   30      GPIO03\TDO          JTAG TDO
+#   31      GPIO02\TDI          JTAG TDI
+#   32      GPIO04\TRST         JTAG TRST
+#   33      GPIO07              NC
+#   35      GPIO06\TX0          UART0_TXD
+#   36      GPIO05\RX0          UART0_RXD
+#   37      GPIO08              NC
+#   39      GPIO26              NC
+#   40      GPIO40              NC
+#   50      TPID_ADC7\GPIO79    AP(Phase A current acquisition/branch identification +)
+#   51      TPID_ADC6\GPIO78    AN(Phase A current acquisition/branch identification -)
+#   52      TPID_ADC5\GPIO77    BP(Phase B current acquisition/branch identification +)
+#   53      TPID_ADC4\GPIO76    BN(Phase B current acquisition/branch identification -)
+#   54      TPID_ADC3\GPIO75    CP(Phase C current acquisition/branch identification +)
+#   55      TPID_ADC2\GPIO74    CN(Phase C current acquisition/branch identification -)
+#   56      TPID_ADC1\GPIO73    NP(DC current sampling 30mV +)
+#   57      TPID_ADC0\GPIO72    NN(DC current sampling 30mV -)
+#   59      GPIO55              IR_RX
+#   60      GPIO57              IR_TX
+#   61      GPIO59              RX_LED(low light)
+#   62      GPIO63              TX_LED(low light)
+#   69      ADC0\GPIO64         NC
+#   70      ADC1\GPIO65         ZA_RISE(Phase A rising edge zero-crossing signal)
+#   71      ADC2\GPIO66         ZA_LOAD(Station area identification zero-crossing signal)
+#   72      ADC3\GPIO67         VA(Phase A voltage acquisition)
+#   73      ADC4\GPIO68         VB(Phase B voltage acquisition, actual phase A voltage)
+#   74      ADC5\GPIO69         VC(Phase C voltage acquisition, actual phase A voltage)
+#   75      ADC6\GPIO70         ADC_CC(DC current sampling single-ended input (0-2.25V))
+#   76      ADC7\GPIO71         V_FAST_DROP(Voltage fast drop input)
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    35  1   68  #GPIO_SPI_FLASH_CLK
+    39  1   69  #GPIO_SPI_FLASH_CS
+    36  1   70  #GPIO_SPI_FLASH_MOSI
+    38  1   71  #GPIO_SPI_FLASH_MISO
+    #37  1       #D2
+    #34  1       #D3
+
+    #load send gpio
+    31  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+    57  1   8   #GPIO_IR_TXD
+    55  1   9   #GPIO_IR_RXD
+
+    65  1   18  #GPIO_PA_ZC
+
+    10  1   7   #GPIO_RS485_TXE
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    4   1   3   #UART_IR_PORT
+    tx  57
+    rx  55
+
+    3   1   4   #UART_RS485_PORT
+    tx  11
+    rx  12
+
+    2   1   1   #UART_CLI_PORT
+    tx  46
+    rx  45
+
+    1   1   0   #UART_PRINT
+    tx  44
+    rx  27
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+spi     #SPI resource allocation
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    # bbcpu use spi1 to connect external rf chip, fixed value used now.
+    1   2   0
+
+i2c        #i2c资源分配
+#  A:i2c number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_I2C_PORT_0
+    scl 42
+    sda 9
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  63
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  59
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+    #up_0    65
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 80  #enlic_pad_0. Phase A Enable receiving
+    tx_en_0 81  #enlic_pad_1. Phase A Enable sending
+    gain_0  82  #glna_pad_0. Phase A gain control
+    gain_1  83  #glna_pad_1. Phase B gain control
+    gain_2  84  #glna_pad_2. Phase C gain control
+
+pwm        #pwm资源分配
+#  A:pwm编号
+#  B:所属core
+#  C:用途(见iot_board_api.h中的PWM_CH_TYPE_TSFM_XXX)
+#   A   B   C
+    # 小负载流程中，
+    # 获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+    # 然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
diff --git a/tools/oem/EVB5580DCCO03_OEM.ini b/tools/oem/EVB5580DCCO03_OEM.ini
new file mode 100644
index 0000000..d2bc4b8
--- /dev/null
+++ b/tools/oem/EVB5580DCCO03_OEM.ini
@@ -0,0 +1,177 @@
+# kl3 k76 evb board, some pins have two functions,
+# the second function is shielded, only one function can be enabled at a time.
+
+general
+    bid     64  #BOARD_EVB5580D
+    mid     1   #MODULE_TYPE_CCO
+    vid     QJ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name    func_default            func_2
+#   1       GPIO11      RF_SPI_DI(rf module)
+#   2       GPIO10      RF_SPI_DO(rf module)
+#   3       GPIO09      RF_SPI_CS(rf module)
+#   4       GPIO42      207_MCLK(rf module)
+#   5       GPIO43      207_FCLK(rf module)
+#   7       GPIO39      pc_tx_en(pa module)     spi_cs(extern flash)
+#   8       GPIO38      pc_rx_en(pa module)     spi_clk(extern flash)
+#   9       GPIO37      pb_tx_en(pa module)     spi_d1(extern flash)
+#   10      GPIO36      pb_rx_en(pa module)     spi_d2(extern flash)
+#   11      GPIO35      pa_tx_en(pa module)     spi_d0(extern flash)
+#   12      GPIO34      pa_rx_en(pa module)     spi_d3(extern flash)
+#   13      GPIO33      m_sta(in place detect)  key1(press down is low)
+#   14      gpio32      set(sta)                i2c_scl(lm75bdp)
+#   15      gpio30      event                   i2c_sda(lm75bdp)
+#   16      gpio14      sta0                    485_ctr
+#   17      gpio29      uart2_tx                485_tx
+#   18      gpio28      uart2_rx                485_rx
+#   22      gpio31      testp(pa module warning) key2(press down is low)
+#   24      GPIO46      AGC_GAIN(rf module)
+#   25      GPIO45      207_ENABLE(rf module)
+#   26      GPIO44      207_TXNRX(rf module)
+#   27      GPIO47      207_DQ0(rf module)
+#   28      GPIO48      207_DQ1(rf module)
+#   29      GPIO49      207_DQ2(rf module)
+#   31      tms\gpio01  pc_led\d_rst            jtag_tms
+#   32      tck\gpio00  tx_led                  jtag_tck
+#   33      tdo\gpio03  rx_led                  jtag tdo
+#   34      tdi\gpio02  uart1_tx\pa_led         jtag tdi
+#   35      trst\gpio04 uart1_rx\pb_led         jtag trst
+#   36      GPIO07      LNA_GAIN_CTR0(pa module)
+#   39      gpio06\tx0  uart0_tx                ir_tx
+#   40      gpio05\rx0  uart0_rx                ir_rx
+#   41      GPIO08      LNA_GAIN_CTR1(pa module)
+#   50      GPIO26      LNA_GAIN_CTR2(pa module)
+#   51      GPIO50      207_DQ3(rf module)
+#   52      GPIO51      207_DQ4(rf module)
+#   53      GPIO52      207_DQ5(rf module)
+#   54      GPIO53      207_DQ6(rf module)
+#   55      GPIO54      207_DQ7(rf module)
+#   56      GPIO55      207_DQ8(rf module)
+#   57      GPIO56      207_DQ9(rf module)
+#   58      GPIO57      207_DQ10(rf module)
+#   59      GPIO58      207_DQ11(rf module)
+#   60      GPIO59      RF_PD(rf module)
+#   61      GPIO61      SW_VC2(rf module, send and receive mode transitions)
+#   62      GPIO62      SW_VC1(rf module, send and receive mode transitions)
+#   68      ADC0/GPIO64 ZA_RISE(phase A zero-cross, rising edge)
+#   69      ADC1/GPIO65 ZC_RISE(phase C zero-cross, rising edge)
+#   70      ADC2/GPIO66 ZB_RISE(phase B zero-cross, rising edge)
+#   71      ADC3/GPIO67 ZC_DOWN(phase C zero-cross, EXT:falling edge)
+#   72      ADC4/GPIO68 ZB_DOWN(phase B zero-cross, EXT:falling edge)
+#   73      ADC5/GPIO69 ZA_DOWN(phase A zero-cross, EXT:falling edge)
+#   76      GPIO12      RF_SPI_CLK(rf module)
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    # bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    32  1   17  #GPIO_GOLDEN_SET
+    30  1   0   #GPIO_PLC_EVENT
+    14  1   1   #GPIO_STA_OUT
+
+    31  1   10  #GPIO_GEODE_OVT
+
+    64  1   18  #GPIO_PA_ZC
+    66  1   19  #GPIO_PB_ZC
+    65  1   20  #GPIO_PC_ZC
+    69  1   44  #GPIO_PA_ZC_EXT
+    68  1   45  #GPIO_PB_ZC_EXT
+    67  1   46  #GPIO_PC_ZC_EXT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    1   1   0   #UART_PRINT
+    tx  2
+    rx  4
+
+    2   1   1   #UART_CLI_PORT
+    tx  29
+    rx  28
+
+spi     #SPI resource allocation
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    # bbcpu use spi1 to connect external rf chip, fixed value used now.
+    1   2   0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  0
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  3
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  1
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+    #up_0    64
+    #up_1    66
+    #up_2    65
+    #down_0  69
+    #down_1  68
+    #down_2  67
+
+pa  # (PARTICULAR RESOURCE)
+    tx_en_0 35  #Phase A Enable sending
+    rx_en_0 34  #Phase A Enable receiving
+    tx_en_1 37  #Phase B Enable sending
+    rx_en_1 36  #Phase B Enable receiving
+    tx_en_2 39  #Phase C Enable sending
+    rx_en_2 38  #Phase C Enable receiving
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
diff --git a/tools/oem/EVB5582D3PS03_OEM.ini b/tools/oem/EVB5582D3PS03_OEM.ini
new file mode 100644
index 0000000..1f089d5
--- /dev/null
+++ b/tools/oem/EVB5582D3PS03_OEM.ini
@@ -0,0 +1,179 @@
+# kl3 k76 evb board, some pins have two functions,
+# the second function is shielded, only one function can be enabled at a time.
+
+general
+    bid     65  #BOARD_EVB5582D
+    mid     4   #MODULE_TYPE_3_PHASE_STA
+    vid     QJ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name    func_default            func_2
+#   1       GPIO11      RF_SPI_DI(rf module)
+#   2       GPIO10      RF_SPI_DO(rf module)
+#   3       GPIO09      RF_SPI_CS(rf module)
+#   4       GPIO42      207_MCLK(rf module)
+#   5       GPIO43      207_FCLK(rf module)
+#   7       GPIO39      pc_tx_en(pa module)     spi_cs(extern flash)
+#   8       GPIO38      pc_rx_en(pa module)     spi_clk(extern flash)
+#   9       GPIO37      pb_tx_en(pa module)     spi_d1(extern flash)
+#   10      GPIO36      pb_rx_en(pa module)     spi_d2(extern flash)
+#   11      GPIO35      pa_tx_en(pa module)     spi_d0(extern flash)
+#   12      GPIO34      pa_rx_en(pa module)     spi_d3(extern flash)
+#   13      GPIO33      m_sta(in place detect)  key1(press down is low)
+#   14      gpio32      set(sta)                i2c_scl(lm75bdp)
+#   15      gpio30      event                   i2c_sda(lm75bdp)
+#   16      gpio14      sta0                    485_ctr
+#   17      gpio29      uart2_tx                485_tx
+#   18      gpio28      uart2_rx                485_rx
+#   22      gpio31      testp(pa module warning) key2(press down is low)
+#   24      GPIO46      AGC_GAIN(rf module)
+#   25      GPIO45      207_ENABLE(rf module)
+#   26      GPIO44      207_TXNRX(rf module)
+#   27      GPIO47      207_DQ0(rf module)
+#   28      GPIO48      207_DQ1(rf module)
+#   29      GPIO49      207_DQ2(rf module)
+#   31      tms\gpio01  pc_led\d_rst            jtag_tms
+#   32      tck\gpio00  tx_led                  jtag_tck
+#   33      tdo\gpio03  rx_led                  jtag tdo
+#   34      tdi\gpio02  uart1_tx\pa_led         jtag tdi
+#   35      trst\gpio04 uart1_rx\pb_led         jtag trst
+#   36      GPIO07      LNA_GAIN_CTR0(pa module)
+#   39      gpio06\tx0  uart0_tx                ir_tx
+#   40      gpio05\rx0  uart0_rx                ir_rx
+#   41      GPIO08      LNA_GAIN_CTR1(pa module)
+#   50      GPIO26      LNA_GAIN_CTR2(pa module)
+#   51      GPIO50      207_DQ3(rf module)
+#   52      GPIO51      207_DQ4(rf module)
+#   53      GPIO52      207_DQ5(rf module)
+#   54      GPIO53      207_DQ6(rf module)
+#   55      GPIO54      207_DQ7(rf module)
+#   56      GPIO55      207_DQ8(rf module)
+#   57      GPIO56      207_DQ9(rf module)
+#   58      GPIO57      207_DQ10(rf module)
+#   59      GPIO58      207_DQ11(rf module)
+#   60      GPIO59      RF_PD(rf module)
+#   61      GPIO61      SW_VC2(rf module, send and receive mode transitions)
+#   62      GPIO62      SW_VC1(rf module, send and receive mode transitions)
+#   68      ADC0/GPIO64 ZA_RISE(phase A zero-cross, rising edge)
+#   69      ADC1/GPIO65 ZC_RISE(phase C zero-cross, rising edge)
+#   70      ADC2/GPIO66 ZB_RISE(phase B zero-cross, rising edge)
+#   71      ADC3/GPIO67 ZC_DOWN(phase C zero-cross, EXT:falling edge)
+#   72      ADC4/GPIO68 ZB_DOWN(phase B zero-cross, EXT:falling edge)
+#   73      ADC5/GPIO69 ZA_DOWN(phase A zero-cross, EXT:falling edge)
+#   76      GPIO12      RF_SPI_CLK(rf module)
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    # bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    32  1   17  #GPIO_GOLDEN_SET
+    30  1   0   #GPIO_PLC_EVENT
+    14  1   1   #GPIO_STA_OUT
+
+    31  1   10  #GPIO_GEODE_OVT
+
+    64  1   18  #GPIO_PA_ZC
+    66  1   19  #GPIO_PB_ZC
+    65  1   20  #GPIO_PC_ZC
+    69  1   44  #GPIO_PA_ZC_EXT
+    68  1   45  #GPIO_PB_ZC_EXT
+    67  1   46  #GPIO_PC_ZC_EXT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    1   1   0   #UART_PRINT
+    tx  2
+    rx  4
+
+    2   1   1   #UART_CLI_PORT
+    tx  29
+    rx  28
+
+spi     #SPI resource allocation
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    # bbcpu use spi1 to connect external rf chip, fixed value used now.
+    1   2   0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  0
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  3
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  1
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+    #up_0    64
+    #up_1    66
+    #up_2    65
+    #down_0  69
+    #down_1  68
+    #down_2  67
+
+pa  # (PARTICULAR RESOURCE)
+    tx_en_0 35  #Phase A Enable sending
+    rx_en_0 34  #Phase A Enable receiving
+    tx_en_1 37  #Phase B Enable sending
+    rx_en_1 36  #Phase B Enable receiving
+    tx_en_2 39  #Phase C Enable sending
+    rx_en_2 38  #Phase C Enable receiving
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+
+
diff --git a/tools/oem/EVB5582DSTA03_OEM.ini b/tools/oem/EVB5582DSTA03_OEM.ini
new file mode 100644
index 0000000..e24e47b
--- /dev/null
+++ b/tools/oem/EVB5582DSTA03_OEM.ini
@@ -0,0 +1,178 @@
+# kl3 k76 evb board, some pins have two functions,
+# the second function is shielded, only one function can be enabled at a time.
+
+general
+    bid     65  #BOARD_EVB5582D
+    mid     0   #MODULE_TYPE_STA
+    vid     QJ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name    func_default            func_2
+#   1       GPIO11      RF_SPI_DI(rf module)
+#   2       GPIO10      RF_SPI_DO(rf module)
+#   3       GPIO09      RF_SPI_CS(rf module)
+#   4       GPIO42      207_MCLK(rf module)
+#   5       GPIO43      207_FCLK(rf module)
+#   7       GPIO39      pc_tx_en(pa module)     spi_cs(extern flash)
+#   8       GPIO38      pc_rx_en(pa module)     spi_clk(extern flash)
+#   9       GPIO37      pb_tx_en(pa module)     spi_d1(extern flash)
+#   10      GPIO36      pb_rx_en(pa module)     spi_d2(extern flash)
+#   11      GPIO35      pa_tx_en(pa module)     spi_d0(extern flash)
+#   12      GPIO34      pa_rx_en(pa module)     spi_d3(extern flash)
+#   13      GPIO33      m_sta(in place detect)  key1(press down is low)
+#   14      gpio32      set(sta)                i2c_scl(lm75bdp)
+#   15      gpio30      event                   i2c_sda(lm75bdp)
+#   16      gpio14      sta0                    485_ctr
+#   17      gpio29      uart2_tx                485_tx
+#   18      gpio28      uart2_rx                485_rx
+#   22      gpio31      testp(pa module warning) key2(press down is low)
+#   24      GPIO46      AGC_GAIN(rf module)
+#   25      GPIO45      207_ENABLE(rf module)
+#   26      GPIO44      207_TXNRX(rf module)
+#   27      GPIO47      207_DQ0(rf module)
+#   28      GPIO48      207_DQ1(rf module)
+#   29      GPIO49      207_DQ2(rf module)
+#   31      tms\gpio01  pc_led\d_rst            jtag_tms
+#   32      tck\gpio00  tx_led                  jtag_tck
+#   33      tdo\gpio03  rx_led                  jtag tdo
+#   34      tdi\gpio02  uart1_tx\pa_led         jtag tdi
+#   35      trst\gpio04 uart1_rx\pb_led         jtag trst
+#   36      GPIO07      LNA_GAIN_CTR0(pa module)
+#   39      gpio06\tx0  uart0_tx                ir_tx
+#   40      gpio05\rx0  uart0_rx                ir_rx
+#   41      GPIO08      LNA_GAIN_CTR1(pa module)
+#   50      GPIO26      LNA_GAIN_CTR2(pa module)
+#   51      GPIO50      207_DQ3(rf module)
+#   52      GPIO51      207_DQ4(rf module)
+#   53      GPIO52      207_DQ5(rf module)
+#   54      GPIO53      207_DQ6(rf module)
+#   55      GPIO54      207_DQ7(rf module)
+#   56      GPIO55      207_DQ8(rf module)
+#   57      GPIO56      207_DQ9(rf module)
+#   58      GPIO57      207_DQ10(rf module)
+#   59      GPIO58      207_DQ11(rf module)
+#   60      GPIO59      RF_PD(rf module)
+#   61      GPIO61      SW_VC2(rf module, send and receive mode transitions)
+#   62      GPIO62      SW_VC1(rf module, send and receive mode transitions)
+#   68      ADC0/GPIO64 ZA_RISE(phase A zero-cross, rising edge)
+#   69      ADC1/GPIO65 ZC_RISE(phase C zero-cross, rising edge)
+#   70      ADC2/GPIO66 ZB_RISE(phase B zero-cross, rising edge)
+#   71      ADC3/GPIO67 ZC_DOWN(phase C zero-cross, EXT:falling edge)
+#   72      ADC4/GPIO68 ZB_DOWN(phase B zero-cross, EXT:falling edge)
+#   73      ADC5/GPIO69 ZA_DOWN(phase A zero-cross, EXT:falling edge)
+#   76      GPIO12      RF_SPI_CLK(rf module)
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    # bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    32  1   17  #GPIO_GOLDEN_SET
+    30  1   0   #GPIO_PLC_EVENT
+    14  1   1   #GPIO_STA_OUT
+
+    31  1   10  #GPIO_GEODE_OVT
+
+    64  1   18  #GPIO_PA_ZC
+    66  1   19  #GPIO_PB_ZC
+    65  1   20  #GPIO_PC_ZC
+    69  1   44  #GPIO_PA_ZC_EXT
+    68  1   45  #GPIO_PB_ZC_EXT
+    67  1   46  #GPIO_PC_ZC_EXT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    1   1   0   #UART_PRINT
+    tx  2
+    rx  4
+
+    2   1   1   #UART_CLI_PORT
+    tx  29
+    rx  28
+
+spi     #SPI resource allocation
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    # bbcpu use spi1 to connect external rf chip, fixed value used now.
+    1   2   0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  0
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  3
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  1
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+    #up_0    64
+    #up_1    66
+    #up_2    65
+    #down_0  69
+    #down_1  68
+    #down_2  67
+
+pa  # (PARTICULAR RESOURCE)
+    tx_en_0 35  #Phase A Enable sending
+    rx_en_0 34  #Phase A Enable receiving
+    tx_en_1 37  #Phase B Enable sending
+    rx_en_1 36  #Phase B Enable receiving
+    tx_en_2 39  #Phase C Enable sending
+    rx_en_2 38  #Phase C Enable receiving
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+
diff --git a/tools/oem/EVB6710CCO03_OEM.ini b/tools/oem/EVB6710CCO03_OEM.ini
new file mode 100644
index 0000000..e2c8cc8
--- /dev/null
+++ b/tools/oem/EVB6710CCO03_OEM.ini
@@ -0,0 +1,179 @@
+# kl3 k76 evb board, some pins have two functions,
+# the other function is shielded, only one function can be enabled at a time.
+
+general
+    bid     66  #BOARD_EVB6710
+    mid     1   #MODULE_TYPE_CCO
+    vid     PH
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name    func_default            func_2                  func_3
+#   1       GPIO12      RF_SPI_CLK(rf module)
+#   2       GPIO11      RF_SPI_MOSI(rf module)
+#   3       GPIO10      RF_SPI_MISO(rf module)
+#   4       GPIO09      RF_SPI_CS(rf module)
+#   5       GPIO42      207_MCLK(rf module)
+#   6       GPIO43      207_FCLK(rf module)
+#   8       GPIO39      pc_tx_en(pa module)     spi_cs(extern flash)
+#   9       GPIO38      pc_rx_en(pa module)     spi_clk(extern flash)
+#   10      GPIO37      pb_tx_en(pa module)     spi_d1(extern flash)
+#   11      GPIO36      pb_rx_en(pa module)     spi_d2(extern flash)
+#   12      GPIO35      pa_tx_en(pa module)     spi_d0(extern flash)
+#   13      GPIO34      pa_rx_en(pa module)     spi_d3(extern flash)    rf_clk(resered io)
+#   14      GPIO33      m_sta(in place detect)  key1(press down is low)
+#   15      gpio32      set(sta)                i2c_scl(lm75bdp)
+#   16      gpio31      event                   i2c_sda(lm75bdp)
+#   18      gpio30      sta0                    485_ctr
+#   19      gpio29      uart2_tx                485_tx
+#   20      gpio28      uart2_rx                485_rx
+#   24      GPIO46      AGC_GAIN(rf module)
+#   25      GPIO45      207_ENABLE(rf module)
+#   26      GPIO44      207_TXNRX(rf module)
+#   27      GPIO47      207_DQ0(rf module)
+#   28      GPIO48      207_DQ1(rf module)
+#   29      GPIO49      207_DQ2(rf module)
+#   30      gpio27      testp(pa module warning) key2(press down is low)
+#   31      tms\gpio01  pc_led\d_rst            jtag_tms
+#   32      tck\gpio00  tx_led                  jtag_tck
+#   33      tdo\gpio03  rx_led                  jtag tdo
+#   34      tdi\gpio02  uart1_tx\pa_led         jtag tdi
+#   35      trst\gpio04 uart1_rx\pb_led         jtag trst
+#   36      GPIO07      LNA_GAIN_CTR0(pa module)
+#   39      gpio06\tx0  uart0_tx                ir_tx
+#   40      gpio05\rx0  uart0_rx                ir_rx
+#   41      GPIO08      LNA_GAIN_CTR1(pa module)
+#   42      GPIO26      LNA_GAIN_CTR2(pa module)
+#   51      GPIO50      207_DQ3(rf module)
+#   52      GPIO51      207_DQ4(rf module)
+#   53      GPIO52      207_DQ5(rf module)
+#   54      GPIO53      207_DQ6(rf module)
+#   55      GPIO54      207_DQ7(rf module)
+#   56      GPIO55      207_DQ8(rf module)
+#   57      GPIO56      207_DQ9(rf module)
+#   58      GPIO57      207_DQ10(rf module)
+#   59      GPIO58      207_DQ11(rf module)
+#   60      GPIO59      RF_PD(rf module)
+#   61      GPIO61      SW_VC2(rf module, send and receive mode transitions)
+#   62      GPIO62      SW_VC1(rf module, send and receive mode transitions)
+#   63      GPIO63      NC
+#   68      ADC0/GPIO64 ZA_RISE(phase A zero-cross, rising edge)
+#   69      ADC1/GPIO65 ZC_RISE(phase C zero-cross, rising edge)
+#   70      ADC2/GPIO66 ZB_RISE(phase B zero-cross, rising edge)
+#   71      ADC3/GPIO67 ZC_DOWN(phase C zero-cross, EXT:falling edge)
+#   72      ADC4/GPIO68 ZB_DOWN(phase B zero-cross, EXT:falling edge)
+#   73      ADC5/GPIO69 ZA_DOWN(phase A zero-cross, EXT:falling edge)
+#   74      GPIO70      NC
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    # bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   0   #GPIO_PLC_EVENT
+    30  1   1   #GPIO_STA_OUT
+
+    27  1   10  #GPIO_GEODE_OVT
+
+    64  1   18  #GPIO_PA_ZC
+    66  1   19  #GPIO_PB_ZC
+    65  1   20  #GPIO_PC_ZC
+    69  1   44  #GPIO_PA_ZC_EXT
+    68  1   45  #GPIO_PB_ZC_EXT
+    67  1   46  #GPIO_PC_ZC_EXT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    1   1   0   #UART_PRINT
+    tx  2
+    rx  4
+
+    2   1   1   #UART_CLI_PORT
+    tx  29
+    rx  28
+
+spi     #SPI resource allocation
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    # bbcpu use spi1 to connect external rf chip, fixed value used now.
+    1   2   0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  0
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  3
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  1
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+    #up_0    64
+    #up_1    66
+    #up_2    65
+    #down_0  69
+    #down_1  68
+    #down_2  67
+
+pa  # (PARTICULAR RESOURCE)
+    tx_en_0 35  #Phase A Enable sending
+    rx_en_0 34  #Phase A Enable receiving
+    tx_en_1 37  #Phase B Enable sending
+    rx_en_1 36  #Phase B Enable receiving
+    tx_en_2 39  #Phase C Enable sending
+    rx_en_2 38  #Phase C Enable receiving
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
diff --git a/tools/oem/EVB67113PS03_OEM.ini b/tools/oem/EVB67113PS03_OEM.ini
new file mode 100644
index 0000000..2910498
--- /dev/null
+++ b/tools/oem/EVB67113PS03_OEM.ini
@@ -0,0 +1,174 @@
+# kl3 k76 evb board, some pins have two functions,
+# the other function is shielded, only one function can be enabled at a time.
+
+general
+    bid     67  #BOARD_EVB6711
+    mid     4   #MODULE_TYPE_3_PHASE_STA
+    vid     PH
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name    func_default            func_2                  func_3
+#   1       GPIO12      RF_SPI_CLK(rf module)
+#   2       GPIO11      RF_SPI_MOSI(rf module)
+#   3       GPIO10      RF_SPI_MISO(rf module)
+#   4       GPIO09      RF_SPI_CS(rf module)
+#   5       GPIO42      207_MCLK(rf module)
+#   6       GPIO43      207_FCLK(rf module)
+#   8       GPIO39      pc_tx_en(pa module)     spi_cs(extern flash)
+#   9       GPIO38      pc_rx_en(pa module)     spi_clk(extern flash)
+#   10      GPIO37      pb_tx_en(pa module)     spi_d1(extern flash)
+#   11      GPIO36      pb_rx_en(pa module)     spi_d2(extern flash)
+#   12      GPIO35      pa_tx_en(pa module)     spi_d0(extern flash)
+#   13      GPIO34      pa_rx_en(pa module)     spi_d3(extern flash)    rf_clk(resered io)
+#   14      GPIO33      m_sta(in place detect)  key1(press down is low)
+#   15      gpio32      set(sta)                i2c_scl(lm75bdp)
+#   16      gpio31      event                   i2c_sda(lm75bdp)
+#   18      gpio30      sta0                    485_ctr
+#   19      gpio29      uart2_tx                485_tx
+#   20      gpio28      uart2_rx                485_rx
+#   24      GPIO46      AGC_GAIN(rf module)
+#   25      GPIO45      207_ENABLE(rf module)
+#   26      GPIO44      207_TXNRX(rf module)
+#   27      GPIO47      207_DQ0(rf module)
+#   28      GPIO48      207_DQ1(rf module)
+#   29      GPIO49      207_DQ2(rf module)
+#   30      gpio27      testp(pa module warning) key2(press down is low)
+#   31      tms\gpio01  pc_led\d_rst            jtag_tms
+#   32      tck\gpio00  tx_led                  jtag_tck
+#   33      tdo\gpio03  rx_led                  jtag tdo
+#   34      tdi\gpio02  uart1_tx\pa_led         jtag tdi
+#   35      trst\gpio04 uart1_rx\pb_led         jtag trst
+#   36      GPIO07      LNA_GAIN_CTR0(pa module)
+#   39      gpio06\tx0  uart0_tx                ir_tx
+#   40      gpio05\rx0  uart0_rx                ir_rx
+#   41      GPIO08      LNA_GAIN_CTR1(pa module)
+#   42      GPIO26      LNA_GAIN_CTR2(pa module)
+#   51      GPIO50      207_DQ3(rf module)
+#   52      GPIO51      207_DQ4(rf module)
+#   53      GPIO52      207_DQ5(rf module)
+#   54      GPIO53      207_DQ6(rf module)
+#   55      GPIO54      207_DQ7(rf module)
+#   56      GPIO55      207_DQ8(rf module)
+#   57      GPIO56      207_DQ9(rf module)
+#   58      GPIO57      207_DQ10(rf module)
+#   59      GPIO58      207_DQ11(rf module)
+#   60      GPIO59      RF_PD(rf module)
+#   61      GPIO61      SW_VC2(rf module, send and receive mode transitions)
+#   62      GPIO62      SW_VC1(rf module, send and receive mode transitions)
+#   63      GPIO63      NC
+#   68      ADC0/GPIO64 ZA_RISE(phase A zero-cross, rising edge)
+#   69      ADC1/GPIO65 ZC_RISE(phase C zero-cross, rising edge)
+#   70      ADC2/GPIO66 ZB_RISE(phase B zero-cross, rising edge)
+#   71      ADC3/GPIO67 ZC_DOWN(phase C zero-cross, EXT:falling edge)
+#   72      ADC4/GPIO68 ZB_DOWN(phase B zero-cross, EXT:falling edge)
+#   73      ADC5/GPIO69 ZA_DOWN(phase A zero-cross, EXT:falling edge)
+#   74      GPIO70      NC
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    # bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   0   #GPIO_PLC_EVENT
+    30  1   1   #GPIO_STA_OUT
+
+    27  1   10  #GPIO_GEODE_OVT
+
+    64  1   18  #GPIO_PA_ZC
+    66  1   19  #GPIO_PB_ZC
+    65  1   20  #GPIO_PC_ZC
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    1   1   0   #UART_PRINT
+    tx  2
+    rx  4
+
+    2   1   1   #UART_CLI_PORT
+    tx  29
+    rx  28
+
+spi     #SPI resource allocation
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    # bbcpu use spi1 to connect external rf chip, fixed value used now.
+    1   2   0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  0
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  3
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  1
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+    #up_0    64
+    #up_1    66
+    #up_2    65
+
+pa  # (PARTICULAR RESOURCE)
+    tx_en_0 35  #Phase A Enable sending
+    rx_en_0 34  #Phase A Enable receiving
+    tx_en_1 37  #Phase B Enable sending
+    rx_en_1 36  #Phase B Enable receiving
+    tx_en_2 39  #Phase C Enable sending
+    rx_en_2 38  #Phase C Enable receiving
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+
diff --git a/tools/oem/EVB6711STA03_OEM.ini b/tools/oem/EVB6711STA03_OEM.ini
new file mode 100644
index 0000000..aa3f4de
--- /dev/null
+++ b/tools/oem/EVB6711STA03_OEM.ini
@@ -0,0 +1,171 @@
+# kl3 k76 evb board, some pins have two functions,
+# the other function is shielded, only one function can be enabled at a time.
+
+general
+    bid     67  #BOARD_EVB6711
+    mid     0   #MODULE_TYPE_STA
+    vid     PH
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num   pin_name    func_default            func_2                  func_3
+#   1       GPIO12      RF_SPI_CLK(rf module)
+#   2       GPIO11      RF_SPI_MOSI(rf module)
+#   3       GPIO10      RF_SPI_MISO(rf module)
+#   4       GPIO09      RF_SPI_CS(rf module)
+#   5       GPIO42      207_MCLK(rf module)
+#   6       GPIO43      207_FCLK(rf module)
+#   8       GPIO39      pc_tx_en(pa module)     spi_cs(extern flash)
+#   9       GPIO38      pc_rx_en(pa module)     spi_clk(extern flash)
+#   10      GPIO37      pb_tx_en(pa module)     spi_d1(extern flash)
+#   11      GPIO36      pb_rx_en(pa module)     spi_d2(extern flash)
+#   12      GPIO35      pa_tx_en(pa module)     spi_d0(extern flash)
+#   13      GPIO34      pa_rx_en(pa module)     spi_d3(extern flash)    rf_clk(resered io)
+#   14      GPIO33      m_sta(in place detect)  key1(press down is low)
+#   15      gpio32      set(sta)                i2c_scl(lm75bdp)
+#   16      gpio31      event                   i2c_sda(lm75bdp)
+#   18      gpio30      sta0                    485_ctr
+#   19      gpio29      uart2_tx                485_tx
+#   20      gpio28      uart2_rx                485_rx
+#   24      GPIO46      AGC_GAIN(rf module)
+#   25      GPIO45      207_ENABLE(rf module)
+#   26      GPIO44      207_TXNRX(rf module)
+#   27      GPIO47      207_DQ0(rf module)
+#   28      GPIO48      207_DQ1(rf module)
+#   29      GPIO49      207_DQ2(rf module)
+#   30      gpio27      testp(pa module warning) key2(press down is low)
+#   31      tms\gpio01  pc_led\d_rst            jtag_tms
+#   32      tck\gpio00  tx_led                  jtag_tck
+#   33      tdo\gpio03  rx_led                  jtag tdo
+#   34      tdi\gpio02  uart1_tx\pa_led         jtag tdi
+#   35      trst\gpio04 uart1_rx\pb_led         jtag trst
+#   36      GPIO07      LNA_GAIN_CTR0(pa module)
+#   39      gpio06\tx0  uart0_tx                ir_tx
+#   40      gpio05\rx0  uart0_rx                ir_rx
+#   41      GPIO08      LNA_GAIN_CTR1(pa module)
+#   42      GPIO26      LNA_GAIN_CTR2(pa module)
+#   51      GPIO50      207_DQ3(rf module)
+#   52      GPIO51      207_DQ4(rf module)
+#   53      GPIO52      207_DQ5(rf module)
+#   54      GPIO53      207_DQ6(rf module)
+#   55      GPIO54      207_DQ7(rf module)
+#   56      GPIO55      207_DQ8(rf module)
+#   57      GPIO56      207_DQ9(rf module)
+#   58      GPIO57      207_DQ10(rf module)
+#   59      GPIO58      207_DQ11(rf module)
+#   60      GPIO59      RF_PD(rf module)
+#   61      GPIO61      SW_VC2(rf module, send and receive mode transitions)
+#   62      GPIO62      SW_VC1(rf module, send and receive mode transitions)
+#   63      GPIO63      NC
+#   68      ADC0/GPIO64 ZA_RISE(phase A zero-cross, rising edge)
+#   69      ADC1/GPIO65 ZC_RISE(phase C zero-cross, rising edge)
+#   70      ADC2/GPIO66 ZB_RISE(phase B zero-cross, rising edge)
+#   71      ADC3/GPIO67 ZC_DOWN(phase C zero-cross, EXT:falling edge)
+#   72      ADC4/GPIO68 ZB_DOWN(phase B zero-cross, EXT:falling edge)
+#   73      ADC5/GPIO69 ZA_DOWN(phase A zero-cross, EXT:falling edge)
+#   74      GPIO70      NC
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    # bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   0   #GPIO_PLC_EVENT
+    30  1   1   #GPIO_STA_OUT
+
+    27  1   10  #GPIO_GEODE_OVT
+
+    64  1   18  #GPIO_PA_ZC
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    1   1   0   #UART_PRINT
+    tx  2
+    rx  4
+
+    2   1   1   #UART_CLI_PORT
+    tx  29
+    rx  28
+
+spi     #SPI resource allocation
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    # bbcpu use spi1 to connect external rf chip, fixed value used now.
+    1   2   0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  0
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  3
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  1
+
+zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource allocation.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+    #up_0    64
+
+pa  # (PARTICULAR RESOURCE)
+    tx_en_0 35  #Phase A Enable sending
+    rx_en_0 34  #Phase A Enable receiving
+    tx_en_1 37  #Phase B Enable sending
+    rx_en_1 36  #Phase B Enable receiving
+    tx_en_2 39  #Phase C Enable sending
+    rx_en_2 38  #Phase C Enable receiving
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+
+
diff --git a/tools/oem/FLX3PS01_OEM.ini b/tools/oem/FLX3PS01_OEM.ini
new file mode 100644
index 0000000..bb2ed27
--- /dev/null
+++ b/tools/oem/FLX3PS01_OEM.ini
@@ -0,0 +1,31 @@
+general
+ bid 5
+ mid 4
+ vid PH
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+#uart1
+# tx 34
+# rx 35
+# cli
+
+uart2
+ tx 8
+ rx 9
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 32
+ rx 33
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 47
+ phase_b 34
+ phase_c 35
diff --git a/tools/oem/FLX6710CCO03_OEM.ini b/tools/oem/FLX6710CCO03_OEM.ini
new file mode 100644
index 0000000..1974c95
--- /dev/null
+++ b/tools/oem/FLX6710CCO03_OEM.ini
@@ -0,0 +1,265 @@
+# FLX6710 cco board, external rf chip, external pa chip
+general
+    bid     68  #BOARD_FLXCCO03
+    mid     1   #MODULE_TYPE_CCO
+    vid     PH
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      zc_c_up
+#   38  zc_c_down           37      zc_b_up             36      zc_b_down
+#   35  zc_a_up             34      pa_led\uart1_tx     33      pb_led\uart1_rx
+#   32  pc_led              31      charge_en           30      pa_c_tx_en
+#   29  pa_c_rx_en          28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp(warning)   2       pa_a_rx_en
+#   4   pa_a_tx_en          7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      uart2_rx            62      rf_channel_sw2(io)
+#   64  m_sta(adc0_gnd)     65      adc1_12v            66      adc2_3.3v
+#   67  pa_b_tx_en          68      zc_a_down           69      pa_b_rx_en
+#   12  rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function(to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    9   1   108 #GPIO_SPI_RF_CS
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    12  1   107 #GPIO_SPI_RF_CLK
+
+    3   1   10  #GPIO_GEODE_OVT
+
+    35  1   18  #GPIO_PA_ZC
+    37  1   19  #GPIO_PB_ZC
+    39  1   20  #GPIO_PC_ZC
+    68  1   44  #GPIO_PA_ZC_EXT
+    36  1   45  #GPIO_PB_ZC_EXT
+    38  1   46  #GPIO_PC_ZC_EXT
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   1   #UART_CLI_PORT
+    tx  28
+    rx  61
+
+    1   1   0   #UART_PRINT
+    tx  34
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   2   #IOT_PLC_PHASE_A_LED
+    ledout  34
+
+    1   1   3   #IOT_PLC_PHASE_B_LED
+    ledout  33
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  32
+
+    3   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    4   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+#   up_0    35
+#   up_1    37
+#   up_2    39
+#   down_0  68
+#   down_1  36
+#   down_2  38
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    rx_en_1 69  #Phase B Enable receiving
+    tx_en_1 67  #Phase B Enable sending
+    rx_en_2 29  #Phase C Enable receiving
+    tx_en_2 30  #Phase C Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3201覆膜为FLX6710
+#   chip id: 0x1003     subid: 0x1023
+
+#=================== 13.10.08.02(HW_VERSION_FLX_MASKCHIP_V1) ==================#
+# FLX CCO 覆膜HZ3201芯片 资源与FLX6710的一样
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_miso         10      rf_spi_mosi         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      zc_c_up
+#   38  zc_c_down           37      zc_b_up             36      zc_b_down
+#   35  zc_a_up             34      pa_led\uart1_tx     33      pb_led\uart1_rx
+#   32  pc_led              31      charge_en           30      pa_c_tx_en
+#   29  pa_c_rx_en          28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp(warning)   2       pa_a_rx_en
+#   4   pa_a_tx_en          7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      uart2_rx            62      rf_channel_sw2(io)
+#   64  m_sta(adc0_gnd)     65      adc1_12v            66      adc2_3.3v
+#   67  pa_b_tx_en          68      zc_a_down           69      pa_b_rx_en
+#   12  rf_spi_clk          27      set(mac,for cco 09 version)
+
+rc_hdr
+    hw_ver      0x0D0A0802  #13.10.08.02
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function(to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    27  1   76  #GPIO_MAC_SET
+
+#=================== 31.20.02.00(HW_VERSION_CCO_USB_V2) ==================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      zc_c_up
+#   38  zc_c_down           37      zc_b_up             36      zc_b_down
+#   35  zc_a_up             34      uart1_tx            33      run_led
+#   32  uart3_tx            31      uart3_rx            30      pa_c_tx_en
+#   29  pa_c_rx_en          28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              27      rst(gd32)
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_a_rx_en          4       pa_a_tx_en          7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      uart2_rx
+#   62  rf_channel_sw2(io)  64      m_sta(adc0_gnd)     65      adc1_12v
+#   66  boot0(gd32)         67      pa_b_tx_en          68      zc_a_down
+#   69  pa_b_rx_en          12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x1F140200  #31.20.02.00
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function(to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    34   255   255
+    32   255   255
+    31   255   255
+    66   1     74 #GPIO_VC_EXT_CHIP_BOOT
+    27   1     75 #GPIO_VC_EXT_CHIP_RST
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    3   1   5   #UART_EXT_CHIP
+    tx  32
+    rx  31
+
+# disable uart0 meter port function
+    0   255   255
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+    2   1   5   #IOT_PWR_LED
+    ledout  33
+
+    3   255   255   #IOT_LED_TYPE_INVALID
+    4   255   255   #IOT_LED_TYPE_INVALID
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    2   255   255   #ADC_TYPE_INVALID
\ No newline at end of file
diff --git a/tools/oem/FLX6710CKB03_OEM.ini b/tools/oem/FLX6710CKB03_OEM.ini
new file mode 100644
index 0000000..9573938
--- /dev/null
+++ b/tools/oem/FLX6710CKB03_OEM.ini
@@ -0,0 +1,115 @@
+# FLX6710 ckb board, external rf chip, external pa chip.
+general
+    bid     86  #BOARD_FLXCKB03
+    mid     0   #MODULE_TYPE_STA
+    vid     PH
+    fver    1
+
+#=============================== default rc====================================#
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  nc                  37      nc                  36      nc
+#   35  nc                  34      rf_clk              32      set
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      m_sta(adc0)         65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(adc3)         68      zc_a_up(adc4)
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    39  1   120 #GPIO_LIC_CTRL
+    34  1   121 #GPIO_RF_CLK
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   12  #GPIO_PM_CHARGE_EN
+    29  1   1   #GPIO_STA_OUT
+    3   1   10  #GPIO_GEODE_OVT
+    67  1   13  #GPIO_RST_CTRL
+    68  1   18  #GPIO_PA_ZC
+    69  1   0   #GPIO_PLC_EVENT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
diff --git a/tools/oem/FLX67113PS03_OEM.ini b/tools/oem/FLX67113PS03_OEM.ini
new file mode 100644
index 0000000..9d63467
--- /dev/null
+++ b/tools/oem/FLX67113PS03_OEM.ini
@@ -0,0 +1,278 @@
+# FLX6711 3ps board, external rf chip, external pa chip.
+general
+    bid     71  #BOARD_FLX3PS03
+    mid     4   #MODULE_TYPE_3_PHASE_STA
+    vid     PH
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   36  zc_b_up             35      zc_c_up             34      rf_clk
+#   32  set(sta)            31      charge_en           29      sta_out
+#   28  uart2_tx            46      rf_agc_gain         45      rf_enable
+#   44  rf_txnrx            47      rf_dq0              48      rf_dq1
+#   49  rf_dq2              1       tx_led              0       rx_led
+#   3   pa_testp(warning)   2       pa_rx_en            4       pa_tx_en
+#   7   pa_lan_gain_ctr0    6       uart0_tx            5       uart0_rx
+#   8   pa_lan_gain_ctr1    26      pa_lan_gain_ctr2    50      rf_dq3
+#   51  rf_dq4              52      rf_dq5              53      rf_dq6
+#   54  rf_dq6              55      rf_dq8              56      rf_dq9
+#   57  rf_dq10             58      rf_dq11             59      rf_pd
+#   61  rf_channel_sw(io)   62      rf_channel_sw(io)   64      m_sta(adc0_gnd)
+#   65  adc1_12v            66      adc2_3.3v           67      d_rst(soft reset)
+#   68  zc_a_up             69      event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    # bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    3   1   10  #GPIO_GEODE_OVT
+
+    32  1   17  #GPIO_GOLDEN_SET
+    29  1   1   #GPIO_STA_OUT
+    69  1   0   #GPIO_PLC_EVENT
+    67  1   13  #GPIO_RST_CTRL
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+    68  1   18  #GPIO_PA_ZC
+    36  1   19  #GPIO_PB_ZC
+    35  1   20  #GPIO_PC_ZC
+
+    39  1   120 #GPIO_LIC_CTRL
+    34  1   121 #GPIO_RF_CLK
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+#   up_1    36
+#   up_2    35
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3211覆膜为FLX6711
+#   chip id: 0x1001     subid: 0x1021
+
+#==================== 13.10.08.02(HW_VERSION_FLX_MASKCHIP_V1) =================#
+# FLX 3PS 覆膜HZ3211芯片 资源与FLX6711的一样
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   36  zc_b_up             35      zc_c_up             34      rf_clk
+#   32  set(sta)            31      charge_en           29      sta_out
+#   28  uart2_tx            46      rf_agc_gain         45      rf_enable
+#   44  rf_txnrx            47      rf_dq0              48      rf_dq1
+#   49  rf_dq2              1       tx_led              0       rx_led
+#   3   pa_testp(warning)   2       pa_rx_en            4       pa_tx_en
+#   7   pa_lan_gain_ctr0    6       uart0_tx            5       uart0_rx
+#   8   pa_lan_gain_ctr1    26      pa_lan_gain_ctr2    50      rf_dq3
+#   51  rf_dq4              52      rf_dq5              53      rf_dq6
+#   54  rf_dq6              55      rf_dq8              56      rf_dq9
+#   57  rf_dq10             58      rf_dq11             59      rf_pd
+#   61  rf_channel_sw(io)   62      rf_channel_sw(io)   64      m_sta(adc0_gnd)
+#   65  adc1_12v            66      adc2_3.3v           67      d_rst(soft reset)
+#   68  zc_a_up             69      event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A0802  #13.10.08.02   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+#================= 13.10.01.29(HW_VERSION_STA_3PS_DM_LOAD_V1) =================#
+# FLX 3PS 带小负载 覆膜HZ3211芯片
+# overview, external pa, external rf, load_send
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   36  zc_b_up             35      zc_c_up             34      rf_clk
+#   32  set(sta)            31      charge_en           29      sta_out
+#   28  uart2_tx            46      rf_agc_gain         45      rf_enable
+#   44  rf_txnrx            47      rf_dq0              48      rf_dq1
+#   49  rf_dq2              1       tx_led              0       rx_led
+#   3   pa_testp(warning)   2       pa_rx_en            4       pa_tx_en
+#   7   pa_lan_gain_ctr0    6       uart0_tx            5       uart0_rx
+#   8   pa_lan_gain_ctr1    26      pa_lan_gain_ctr2    50      rf_dq3
+#   51  rf_dq4              52      rf_dq5              53      rf_dq6
+#   54  rf_dq6              55      rf_dq8              56      rf_dq9
+#   57  rf_dq10             58      rf_dq11             59      rf_pd
+#   61  rf_channel_sw(io)   62      rf_channel_sw(io)   64      m_sta(adc0_gnd)
+#   65  adc1_12v            66      adc2_3.3v           67      d_rst(soft reset)
+#   68  zc_a_up             69      event               12      rf_spi_clk
+#   30  fz_send(load)
+
+rc_hdr
+    hw_ver      0x0D0A011D  #13.10.1.29
+    mode        1
+    d_hw_ver    0x0D0A0802
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+#==================== 13.10.02.31(HW_VERSION_STA_FLX_3PS_DM_V1) ==================#
+#==================== FLX三相09规约的PCB =========================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      mo_clk_flash
+#   38  mo_si_flash         37      mi_so_flash         36      zc_b_up
+#   35  zc_c_up             34      rf_clk              33      mo_cs_flash
+#   32  set                 31      charge_en           30      nc
+#   29  sta_out             28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp            2       pa_rx_en
+#   4   pa_tx_en            7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      pa_lic_crt          62      rf_channel_sw(io)
+#   64  m_sta(adc_0)        65      adc_12v             66      adc_3.3v
+#   67  d_rst(soft reset)   68      zc_a_up             69      event
+#   12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A021F  #13.10.02.31   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x0D0A0802
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    39  1   68  #GPIO_SPI_FLASH_CLK
+    38  1   70  #GPIO_SPI_FLASH_MOSI
+    37  1   71  #GPIO_SPI_FLASH_MISO
+    33  1   69  #GPIO_SPI_FLASH_CS
+
+    61  1   120 #GPIO_LIC_CTRL
+
+#==================== 13.12.02.30(HW_VERSION_STA_FLX_3PS_DM_V0) ==================#
+#==================== FLX三相物联网产品采用HT三相物联网的PCB(510-12版本)==========#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      mo_clk_flash
+#   38  mo_si_flash         37      mi_so_flash         36      zc_b_up
+#   35  zc_c_up             34      rf_clk              33      mo_cs_flash
+#   32  set                 31      charge_en           30      fz_send(load)
+#   29  sta_out             28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp            2       pa_rx_en
+#   4   pa_tx_en            7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      pa_lic_crt          62      rf_channel_sw(io)
+#   64  m_sta(adc_0)        65      adc_12v             66      adc_3.3v
+#   67  d_rst(soft reset)   68      zc_a_up             69      event
+#   12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0C021E  #13.12.02.30   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x0D0A0802
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    39  1   68  #GPIO_SPI_FLASH_CLK
+    38  1   70  #GPIO_SPI_FLASH_MOSI
+    37  1   71  #GPIO_SPI_FLASH_MISO
+    33  1   69  #GPIO_SPI_FLASH_CS
+
+    61  1   120 #GPIO_LIC_CTRL
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
\ No newline at end of file
diff --git a/tools/oem/FLX6711IIC03_OEM.ini b/tools/oem/FLX6711IIC03_OEM.ini
new file mode 100644
index 0000000..3d496db
--- /dev/null
+++ b/tools/oem/FLX6711IIC03_OEM.ini
@@ -0,0 +1,203 @@
+# see KL3_EXAMPLE_OEM.ini for file format description
+# FLX6711 IIC board, external rf chip, external pa chip.
+general
+    bid     70  #BOARD_FLXIIC03
+    mid     2   #MODULE_TYPE_COLLECTOR_II
+    vid     PH
+    fver    1
+
+#===================================== 真实资源 ===============================#
+# NONE
+
+#===================================== 覆膜资源 ===============================#
+# HZ3211覆膜为FLX6711
+#   chip id: 0x1001     subid: 0x1021
+
+#=============================== default rc====================================#
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      ext_flash_cs
+#   38  ext_flash_clk       36      ext_flash_miso      37      ext_flash_mosi
+#   34  ir_rx               32      485_ctr             31      charge_en
+#   30  ir_tx               29      zc_up               28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   0   sta_485_led         1       tx\rx_led           3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      pwr_led             65      adc_12v
+#   66  adc_3.3v            68      485_rxd             69      485_txd
+#   12  rf_spi_clk          35      rf_clk
+
+rc_hdr
+    hw_ver      0x00000000
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+#   extern flash spi gpio
+    39  1   69  #GPIO_SPI_FLASH_CS
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    36  1   71  #GPIO_SPI_FLASH_MISO
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+
+    32  1   7   #GPIO_RS485_TXE
+    31  1   12  #GPIO_PM_CHARGE_EN
+    29  1   18  #GPIO_PA_ZC
+
+    30  1   8   #GPIO_IR_TXD
+    34  1   9   #GPIO_IR_RXD
+
+    35  1   121 #GPIO_RF_CLK
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+#   current serial port is not multiplexed, uart0(6\5) as download port reserved
+    1   1   3   #UART_IR_PORT
+    tx  30
+    rx  34
+
+    2   1   0   #UART_PRINT
+    tx  28
+
+    3   1   2   #UART_METER_PORT
+    tx  69
+    rx  68
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   6   #IOT_RS485_LED
+    ledout  1
+
+    1   1   7   #IOT_PLC_TR_LED
+    ledout  0
+
+    2   1   5   #IOT_PWR_LED
+    ledout  64
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    29
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#=================== 13.10.08.02(HW_VERSION_FLX_MASKCHIP_V1) ==================#
+# FLX IIC 覆膜HZ3211芯片 资源与FLX6711的一样
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      ext_flash_cs
+#   38  ext_flash_clk       36      ext_flash_miso      37      ext_flash_mosi
+#   34  ir_rx               32      485_ctr             31      charge_en
+#   30  ir_tx               29      zc_up               28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   0   sta_485_led         1       tx\rx_led           3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      pwr_led             65      adc_12v
+#   66  adc_3.3v            68      485_rxd             69      485_txd
+#   12  rf_spi_clk          35      rf_clk
+
+rc_hdr
+    hw_ver      0x0D0A0802  #13.10.08.02
+    mode        1
+    d_hw_ver    0x00000000
+
+#==================== 13.10.04.29(HW_VERSION_IIC_DM_LOAD_V1) ==================#
+# FLX IIC 带小负载 覆膜HZ3211芯片
+# overview: extern flash chip
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      ext_flash_cs
+#   38  ext_flash_clk       36      ext_flash_miso      37      ext_flash_mosi
+#   34  ir_rx               32      485_ctr             31      charge_en
+#   30  ir_tx               29      zc_up               28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   0   sta_485_led         1       tx\rx_led           3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      pwr_led             65      adc_12v
+#   66  adc_3.3v            68      485_rxd             69      485_txd
+#   12  rf_spi_clk          35      rf_clk              67      fz_send(load)
+
+rc_hdr
+    hw_ver      0x0D0A041D  #13.10.04.29
+    mode        1
+    d_hw_ver    0x0D0A0802
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    67  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO67和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
diff --git a/tools/oem/FLX6711STA03_OEM.ini b/tools/oem/FLX6711STA03_OEM.ini
new file mode 100644
index 0000000..fbbd259
--- /dev/null
+++ b/tools/oem/FLX6711STA03_OEM.ini
@@ -0,0 +1,233 @@
+# FLX6711 sta board, external rf chip, external pa chip.
+general
+    bid     69  #BOARD_FLXSTA03
+    mid     0   #MODULE_TYPE_STA
+    vid     PH
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   12  rf_spi_clk          42      rf_mclk             43      rf_fclk
+#   39  pa_lic_ctr          34      rf_clk              32      set(sta)
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc0_gnd)     65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(soft reset)   68      zc_a_up
+#   69  event
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    3   1   10  #GPIO_GEODE_OVT
+
+    32  1   17  #GPIO_GOLDEN_SET
+    29  1   1   #GPIO_STA_OUT
+    69  1   0   #GPIO_PLC_EVENT
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+    68  1   18  #GPIO_PA_ZC
+    39  1   120 #GPIO_LIC_CTRL
+
+    67  1   13  #GPIO_RST_CTRL
+    34  1   121 #GPIO_RF_CLK
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3211覆膜为FLX6711
+#   chip id: 0x1001     subid: 0x1021
+
+#=================== 13.10.08.02(HW_VERSION_FLX_MASKCHIP_V1) ==================#
+# FLX STA 覆膜HZ3211芯片 资源与FLX6711的一样
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   12  rf_spi_clk          42      rf_mclk             43      rf_fclk
+#   39  pa_lic_ctr          34      rf_clk              32      set(sta)
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc0_gnd)     65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(soft reset)   68      zc_a_up
+#   69  event               38      flash_spi_clk       37      flash_spi_mosi
+#   36  flash_spi_miso      35      flash_spi_cs
+
+rc_hdr
+    hw_ver      0x0D0A0802  #13.10.08.02
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+    36  1   71  #GPIO_SPI_FLASH_MISO
+    35  1   69  #GPIO_SPI_FLASH_CS
+
+#================== 13.10.01.29(HW_VERSION_STA_3PS_DM_LOAD_V1) ================#
+# FLX STA 带小负载 覆膜HZ3211芯片
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   12  rf_spi_clk          42      rf_mclk             43      rf_fclk
+#   39  pa_lic_ctr          34      rf_clk              32      set(sta)
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc0_gnd)     65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(soft reset)   68      zc_a_up
+#   69  event               30      fz_send(load)
+
+rc_hdr
+    hw_ver      0x0D0A011D  #13.10.1.29
+    mode        1
+    d_hw_ver    0x0D0A0802
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+#=============================== 13.10.01.12(HW_VERSION_STA_CKQ_DM_V1) ==============#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   12  rf_spi_clk          42      rf_mclk             43      rf_fclk
+#   39  pa_lic_ctr          34      nc                  32      set(sta)
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc0_gnd)     65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(soft reset)   68      zc_a_up
+#   69  event
+
+rc_hdr
+    hw_ver      0x0D0A010C  #13.10.01.12   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    34  255   255 #GPIO_SPI_RF_CLK
\ No newline at end of file
diff --git a/tools/oem/FLXCCO01_OEM.ini b/tools/oem/FLXCCO01_OEM.ini
new file mode 100644
index 0000000..ffb4207
--- /dev/null
+++ b/tools/oem/FLXCCO01_OEM.ini
@@ -0,0 +1,44 @@
+general
+ bid 4
+ mid 1
+ vid PH
+
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ log
+
+uart2
+ tx 0
+ rx 1
+ cli
+
+led
+ tx 32
+ rx 33
+ phase_a 34
+ phase_b 35
+ phase_c 36
+ 
+tx_e
+ phase_a 26
+ phase_b 24
+ phase_c 22
+
+rx_e
+ phase_a 27
+ phase_b 25
+ phase_c 23
+ 
+glna
+ phase_a 28
+ phase_b 20
+ phase_c 21
+
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/FLXIIC01_OEM.ini b/tools/oem/FLXIIC01_OEM.ini
new file mode 100644
index 0000000..3c19f95
--- /dev/null
+++ b/tools/oem/FLXIIC01_OEM.ini
@@ -0,0 +1,32 @@
+general
+ bid 6
+ mid 2
+ vid PH
+
+uart0
+ tx 30
+ rx 31
+ log
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ rx 9
+ rs485
+
+uart3
+ tx 22
+ rx 23
+ ir
+
+led
+ tx 36
+ rx 32
+ rs485 33
+
+zc
+ phase_a 47
diff --git a/tools/oem/FLXSTA01_OEM.ini b/tools/oem/FLXSTA01_OEM.ini
new file mode 100644
index 0000000..7b973a9
--- /dev/null
+++ b/tools/oem/FLXSTA01_OEM.ini
@@ -0,0 +1,29 @@
+general
+ bid 5
+ mid 0
+ vid PH
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ rx 9
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 32
+ rx 33
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 47
diff --git a/tools/oem/FPGACCO03_OEM.ini b/tools/oem/FPGACCO03_OEM.ini
new file mode 100644
index 0000000..25e5e71
--- /dev/null
+++ b/tools/oem/FPGACCO03_OEM.ini
@@ -0,0 +1,41 @@
+general
+    bid     53
+    mid     1
+    vid     HT
+    fver    1
+
+#================== default rc===================#
+rc_hdr
+    hw_ver      0x00000000
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio
+    # bbcup spi gpio, query by plc core
+    9   1   107
+    10  1   110
+    11  1   109
+    12  1   108
+    # plc event, J204-23
+    58  1   0
+
+uart
+    0   1   2
+    tx  6
+    rx  5
+
+    1   1   0
+    tx  8
+
+    2   0   0
+    tx  36
+
+    3   1   1
+    tx  35
+    rx  34
+
+    4   2   13
+    tx  9
+
+spi
+    1   2   0
diff --git a/tools/oem/FPGASTA03_OEM.ini b/tools/oem/FPGASTA03_OEM.ini
new file mode 100644
index 0000000..d5e06ac
--- /dev/null
+++ b/tools/oem/FPGASTA03_OEM.ini
@@ -0,0 +1,42 @@
+general
+    bid     52
+    mid     0
+    vid     HT
+    fver    1
+
+#================== default rc===================#
+rc_hdr
+    hw_ver      0x00000000
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio
+    # bbcup spi gpio, query by plc core
+    9   1   107
+    10  1   110
+    11  1   109
+    12  1   108
+    # plc event, J204-23
+    58  1   0
+
+uart
+    0   1   2
+    tx  6
+    rx  5
+
+    1   1   0
+    tx  8
+
+    2   0   0
+    tx  36
+
+    3   1   1
+    tx  35
+    rx  34
+
+    4   2   13
+    tx  9
+
+spi
+    1   2   0
+
diff --git a/tools/oem/GLDQCCO01_OEM.ini b/tools/oem/GLDQCCO01_OEM.ini
new file mode 100755
index 0000000..1ff016e
--- /dev/null
+++ b/tools/oem/GLDQCCO01_OEM.ini
@@ -0,0 +1,27 @@
+general
+ bid 10
+ mid 1
+
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ rx 9
+ log
+
+led
+ tx 32
+ rx 33
+ 
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/GLDQIIC01_OEM.ini b/tools/oem/GLDQIIC01_OEM.ini
new file mode 100755
index 0000000..d3e732b
--- /dev/null
+++ b/tools/oem/GLDQIIC01_OEM.ini
@@ -0,0 +1,24 @@
+general
+ bid 12
+ mid 2
+
+uart0
+ tx 30
+ rx 31
+
+uart1
+ tx 34
+ rx 35
+
+uart2
+ tx 8
+ rx 9
+
+led
+ tx 32
+ rx 33
+ 
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/GLDQSTA01_OEM.ini b/tools/oem/GLDQSTA01_OEM.ini
new file mode 100755
index 0000000..430b5d3
--- /dev/null
+++ b/tools/oem/GLDQSTA01_OEM.ini
@@ -0,0 +1,27 @@
+general
+ bid 11
+ mid 0
+
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ rx 9
+ log
+
+led
+ tx 32
+ rx 33
+ 
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/GOLDFINGER_17P03_AMPIOT_OEM.ini b/tools/oem/GOLDFINGER_17P03_AMPIOT_OEM.ini
new file mode 100644
index 0000000..0c8fdc0
--- /dev/null
+++ b/tools/oem/GOLDFINGER_17P03_AMPIOT_OEM.ini
@@ -0,0 +1,87 @@
+# kl3 goldfinger board
+
+general
+    bid     55  #BOARD_GOLDFINGER03
+    mid     0   #sta\cco
+    vid     HT
+    fver    1
+
+#===== 101.20.1.30(HW_VERSION_IOT_Q111N_ISC_KL3), yonglin\ozt, default rc =====#
+# overview
+# m_num     pin_name    func           |    m_num   pin_name    func
+#   3       gpio04      pwm0\gpio0     |    4       gpio02      rxd0
+#   5       gpio07      pwm3\gpio3     |    6       gpio03      txd0
+#   7       gpio31      gpio15         |    8       gpio26      pwm4\gpio4
+#   9       gpio08      pwm16\gpio16   |    11      adc3\gpio57 adc4
+#   12      adc4\gpio68 adc5           |    13      adc5\gpio69 adc6
+
+rc_hdr
+    hw_ver      0x6514011E  #101.20.1.30
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio
+    4   1   95  #GPIO_CUS_IO_0
+    7   1   97  #GPIO_CUS_IO_3
+    31  1   101 #GPIO_CUS_IO_15
+    26  1   98  #GPIO_CUS_IO_4
+    8   1   102 #GPIO_CUS_IO_16
+
+adc
+    3   1   13  #ADC_CUS_ADC_4
+    4   1   14  #ADC_CUS_ADC_5
+    5   1   15  #ADC_CUS_ADC_6
+
+uart
+    0   0   0   #UART_PRINT
+    tx  2       # 对应金手指底板上的RX1
+
+    1   1   0   #UART_PRINT
+    tx  3       # 对应金手指底板上的TX1
+
+    3   0   11  #UART_CUS_PORT_0
+    tx  6       # 对应金手指底板上的TX0
+    rx  5       # 对应金手指底板上的RX0
+
+    2   1   1   #UART_CLI_PORT
+    tx  33
+    rx  32
+
+    6   0   14  #UART_ICC_PORT
+    tx  11
+    rx  12
+
+    7   1   11  #UART_CUS_PORT_0
+    tx  12
+    rx  11
+
+ledc
+    0   1   7   #IOT_PLC_TR_LED
+
+# internal sealing one pa chips
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 80  #enlic_pad_0. Phase A Enable receiving
+    tx_en_0 81  #enlic_pad_1. Phase A Enable sending
+    gain_0  82  #glna_pad_0. Phase A gain control
+    gain_1  83  #glna_pad_1. Phase B gain control
+    gain_2  84  #glna_pad_2. Phase C gain control
+
+#======= 105.10.1.30(HW_VERSION_IOT_Q111N_ISG_KL3), huawei, default rc =======#
+# overview
+# m_num pin_name        func            m_num   pin_name        func
+#   9   adc3/gpio67     adc3/gpio67     10      adc4/gpio68     adc4/gpio68
+#   11  adc5/gpio69     adc5/gpio69     32      tdi/gpio02      gpio02
+#   31  tdo/gpio03      gpio03          40      gpio26          gpio26
+#   39  gpio08          gpio08          33      trst/gpio04     gpio04
+#   34  gpio07          gpio07          23      gpio31          gpio31
+#   37  uart0_tx/gpio06 uart0_tx/gpio06 38      uart0_rx/gpio05 uart0_rx/gpio05
+#   29  tms/gpio01      tx_led/gpio01   16      gpio38          gpio38
+#   18  gpio36          gpio36          19      gpio35          gpio35
+#   20  gpio34          gpio34          17      gpio37          gpio37
+#   15  gpio39          gpio39
+
+rc_hdr
+    hw_ver      0x690A011E  #105.10.1.30
+    mode        1
+    d_hw_ver    0x6514011E
+
diff --git a/tools/oem/GOLDFINGER_17P03_OEM.ini b/tools/oem/GOLDFINGER_17P03_OEM.ini
new file mode 100644
index 0000000..26d7b3b
--- /dev/null
+++ b/tools/oem/GOLDFINGER_17P03_OEM.ini
@@ -0,0 +1,76 @@
+# kl3 goldfinger board
+
+general
+    bid     55  #BOARD_GOLDFINGER03
+    mid     0   #sta\cco
+    vid     HT
+    fver    1
+
+#===== 101.20.1.30(HW_VERSION_IOT_Q111N_ISC_KL3), yonglin\ozt, default rc =====#
+# overview
+# m_num     pin_name    func           |    m_num   pin_name    func
+#   3       gpio04      pwm0\gpio0     |    4       gpio02      rxd0
+#   5       gpio07      pwm3\gpio3     |    6       gpio03      txd0
+#   7       gpio31      gpio15         |    8       gpio26      pwm4\gpio4
+#   9       gpio08      pwm16\gpio16   |    11      adc3\gpio57 adc4
+#   12      adc4\gpio68 adc5           |    13      adc5\gpio69 adc6
+
+rc_hdr
+    hw_ver      0x6514011E  #101.20.1.30
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio
+    4   1   95  #GPIO_CUS_IO_0
+    7   1   97  #GPIO_CUS_IO_3
+    31  1   101 #GPIO_CUS_IO_15
+    26  1   98  #GPIO_CUS_IO_4
+    8   1   102 #GPIO_CUS_IO_16
+
+adc
+    3   1   13  #ADC_CUS_ADC_4
+    4   1   14  #ADC_CUS_ADC_5
+    5   1   15  #ADC_CUS_ADC_6
+
+uart
+    0   1   0   #UART_PRINT
+    tx  6
+    rx  5
+
+    1   1   11  #UART_CUS_PORT_0
+    tx  3
+    rx  2
+
+    2   1   1   #UART_CLI_PORT
+    tx  33
+    rx  32
+
+ledc
+    0   1   7   #IOT_PLC_TR_LED
+
+# internal sealing one pa chips
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 80  #enlic_pad_0. Phase A Enable receiving
+    tx_en_0 81  #enlic_pad_1. Phase A Enable sending
+    gain_0  82  #glna_pad_0. Phase A gain control
+    gain_1  83  #glna_pad_1. Phase B gain control
+    gain_2  84  #glna_pad_2. Phase C gain control
+
+#======= 105.10.1.30(HW_VERSION_IOT_Q111N_ISG_KL3), huawei, default rc =======#
+# overview
+# m_num pin_name        func            m_num   pin_name        func
+#   9   adc3/gpio67     adc3/gpio67     10      adc4/gpio68     adc4/gpio68
+#   11  adc5/gpio69     adc5/gpio69     32      tdi/gpio02      gpio02
+#   31  tdo/gpio03      gpio03          40      gpio26          gpio26
+#   39  gpio08          gpio08          33      trst/gpio04     gpio04
+#   34  gpio07          gpio07          23      gpio31          gpio31
+#   37  uart0_tx/gpio06 uart0_tx/gpio06 38      uart0_rx/gpio05 uart0_rx/gpio05
+#   29  tms/gpio01      tx_led/gpio01   16      gpio38          gpio38
+#   18  gpio36          gpio36          19      gpio35          gpio35
+#   20  gpio34          gpio34          17      gpio37          gpio37
+#   15  gpio39          gpio39
+
+rc_hdr
+    hw_ver      0x690A011E  #105.10.1.30
+    mode        1
+    d_hw_ver    0x6514011E
\ No newline at end of file
diff --git a/tools/oem/GOLDFINGER_17P_OEM.ini b/tools/oem/GOLDFINGER_17P_OEM.ini
new file mode 100644
index 0000000..27809e4
--- /dev/null
+++ b/tools/oem/GOLDFINGER_17P_OEM.ini
@@ -0,0 +1,24 @@
+general
+ bid 42
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ log
+
+uart1
+ tx 34
+ rx 35
+ ext
+
+uart2
+ tx 8
+ rx 9
+ cli
+
+# led's option: tx
+led
+ tx 32
diff --git a/tools/oem/GPRSCCO01_OEM.ini b/tools/oem/GPRSCCO01_OEM.ini
new file mode 100644
index 0000000..040f22e
--- /dev/null
+++ b/tools/oem/GPRSCCO01_OEM.ini
@@ -0,0 +1,49 @@
+general
+ bid 18
+ mid 1
+ vid HT
+
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ log
+
+uart2
+ tx 0
+ rx 1
+ cli
+
+uart3
+ tx 2
+ rx 3
+ ir
+
+led
+ tx 33
+ rx 33
+ phase_a 34
+ phase_b 35
+ phase_c 36
+
+tx_e
+ phase_a 26
+ phase_b 24
+ phase_c 22
+
+rx_e
+ phase_a 27
+ phase_b 25
+ phase_c 23
+
+glna
+ phase_a 28
+ phase_b 20
+ phase_c 21
+
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/GX2001CCO03_OEM.ini b/tools/oem/GX2001CCO03_OEM.ini
new file mode 100644
index 0000000..374658d
--- /dev/null
+++ b/tools/oem/GX2001CCO03_OEM.ini
@@ -0,0 +1,181 @@
+# GX2001 cco board, external rf chip, external pa chip
+general
+    bid     82  #BOARD_GXCCO03
+    mid     1   #MODULE_TYPE_CCO
+    vid     GX
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio  function              gpio  function
+# 11    rf_spi_mosi         10    rf_spi_miso           9     rf_spi_cs
+# 42    rf_mclk             43    rf_fclk               39    zc_c
+# 38    zc_c_ext            37    zc_b                  36    zc_b_ext
+# 35    zc_a                34    pa_led\uart1_tx       33    pb_led\uart1_rx
+# 32    pc_led              30    pa_c_tx_en            14    nc
+# 29    pa_c_rx_en          28    uart2_tx              31    charge_en
+# 46    rf_agc_gain         45    rf_enable             44    rf_txnrx
+# 47    rf_dq0              48    rf_dq1                49    rf_dq2
+# 1     tx_led              0     rx_led                3     pa_testp(warning)
+# 2     pa_a_rx_en          4     pa_a_tx_en            7     pa_lan_gain_ctr0
+# 6     uart0_tx            5     uart0_rx              8     pa_lan_gain_ctr1
+# 26    pa_lan_gain_ctr2    50    rf_dq3                51    rf_dq4
+# 52    rf_dq5              53    rf_dq6                54    rf_dq7
+# 55    rf_dq8              56    rf_dq9                57    rf_dq10
+# 58    rf_dq11             59    rf_pd                 61    uart2_rx
+# 62    rf_channel_sw2(io)  64    m_sta(adc_gnd)        65    adc_12v
+# 66    adc_3.3v            67    pa_b_tx_en            68    zc_a_ext
+# 69    pa_b_rx_en          12    rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function(to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    9   1   108 #GPIO_SPI_RF_CS
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    12  1   107 #GPIO_SPI_RF_CLK
+
+    3   1   10  #GPIO_GEODE_OVT
+
+    35  1   18  #GPIO_PA_ZC
+    37  1   19  #GPIO_PB_ZC
+    39  1   20  #GPIO_PC_ZC
+    68  1   44  #GPIO_PA_ZC_EXT
+    36  1   45  #GPIO_PB_ZC_EXT
+    38  1   46  #GPIO_PC_ZC_EXT
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   1   #UART_CLI_PORT
+    tx  28
+    rx  61
+
+    1   1   0   #UART_PRINT
+    tx  34
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   2   #IOT_PLC_PHASE_A_LED
+    ledout  34
+
+    1   1   3   #IOT_PLC_PHASE_B_LED
+    ledout  33
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  32
+
+    3   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    4   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+#   up_0    35
+#   up_1    37
+#   up_2    39
+#   down_0  68
+#   down_1  36
+#   down_2  38
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    rx_en_1 69  #Phase B Enable receiving
+    tx_en_1 67  #Phase B Enable sending
+    rx_en_2 29  #Phase C Enable receiving
+    tx_en_2 30  #Phase C Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3201覆膜为GX2001
+#   chip id: 0x1003     subid: 0x1043
+
+#=================== 13.10.08.04(HW_VERSION_GX_MASKCHIP_V1) ===================#
+# GX CCO 覆膜HZ3201芯片 资源与GX2001的一样
+# overview
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_mosi         10    rf_spi_miso         9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    zc_c
+#   38  zc_c_ext            37    zc_b                36    zc_b_ext
+#   35  zc_a                34    pa_led\uart1_tx     33    pb_led\uart1_rx
+#   32  pc_led              31    charge_en           30    pa_c_tx_en
+#   29  pa_c_rx_en          28    uart2_tx            46    rf_agc_gain
+#   45  rf_enable           44    rf_txnrx            47    rf_dq0
+#   48  rf_dq1              49    rf_dq2              27    nc
+#   1   tx_led              0     rx_led              3     pa_testp(warning)
+#   2   pa_rx_en            4     pa_tx_en            7     pa_lan_gain_ctr0
+#   6   uart0_tx            5     uart0_rx            8     pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50    rf_dq3              51    rf_dq4
+#   52  rf_dq5              53    rf_dq6              54    rf_dq7
+#   55  rf_dq8              56    rf_dq9              57    rf_dq10
+#   58  rf_dq11             59    rf_pd               61    uart2_rx
+#   62  rf_channel_sw(io)   64    m_sta(adc_gnd)      65    adc_12v
+#   66  adc_3.3v            67    pa_b_tx_en          68    zc_a_ext
+#   69  pa_b_rx_en          12    rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0A0804  #13.10.08.04 Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
diff --git a/tools/oem/GX2001CKB03_OEM.ini b/tools/oem/GX2001CKB03_OEM.ini
new file mode 100644
index 0000000..dacaaaf
--- /dev/null
+++ b/tools/oem/GX2001CKB03_OEM.ini
@@ -0,0 +1,115 @@
+# GX2001 ckb board, external rf chip, external pa chip.
+general
+    bid     87  #BOARD_GXCKB03
+    mid     0   #MODULE_TYPE_STA
+    vid     GX
+    fver    1
+
+#=============================== default rc====================================#
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  nc                  37      nc                  36      nc
+#   35  nc                  34      rf_clk              32      set
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      m_sta(adc0)         65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(adc3)         68      zc_a_up(adc4)
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    39  1   120 #GPIO_LIC_CTRL
+    34  1   121 #GPIO_RF_CLK
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   12  #GPIO_PM_CHARGE_EN
+    29  1   1   #GPIO_STA_OUT
+    3   1   10  #GPIO_GEODE_OVT
+    67  1   13  #GPIO_RST_CTRL
+    68  1   18  #GPIO_PA_ZC
+    69  1   0   #GPIO_PLC_EVENT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
diff --git a/tools/oem/GX20113PS03_OEM.ini b/tools/oem/GX20113PS03_OEM.ini
new file mode 100644
index 0000000..b4c10eb
--- /dev/null
+++ b/tools/oem/GX20113PS03_OEM.ini
@@ -0,0 +1,208 @@
+# GX2011 3ps board, external rf chip, external pa chip.
+general
+    bid     81  #BOARD_GX3PS03
+    mid     4   #MODULE_TYPE_3_PHASE_STA
+    vid     GX
+    fver    1
+
+#===============================default rc====================================#
+# overview
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_mosi         10    rf_spi_miso         9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    nc
+#   38  nc                  37    nc                  36    zc_b
+#   35  zc_c                34    rf_clk              33    nc
+#   32  set(sta)            30    nc                  14    nc
+#   29  sta_out             28    uart2_tx            31    nc
+#   46  rf_agc_gain         45    rf_enable           44    rf_txnrx
+#   47  rf_dq0              48    rf_dq1              49    rf_dq2
+#   1   tx_led              0     rx_led              3     pa_testp(warning)
+#   2   pa_rx_en            4     pa_tx_en            7     pa_lan_gain_ctr0
+#   6   uart0_tx            5     uart0_rx            8     pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50    rf_dq3              51    rf_dq4
+#   52  rf_dq5              53    rf_dq6              54    rf_dq7
+#   55  rf_dq8              56    rf_dq9              57    rf_dq10
+#   58  rf_dq11             59    rf_pd               61    pa_lic_ctr
+#   62  rf_channel_sw2      64    m_sta(adc_gnd)      65    adc_12v
+#   66  adc_3.3v            67    d_rst(soft reset)   68    zc_a
+#   69  event               12    rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    34  1   121 #GPIO_RF_CLK
+    3   1   10  #GPIO_GEODE_OVT
+
+    32  1   17  #GPIO_GOLDEN_SET
+    29  1   1   #GPIO_STA_OUT
+    69  1   0   #GPIO_PLC_EVENT
+    67  1   13  #GPIO_RST_CTRL
+
+    68  1   18  #GPIO_PA_ZC
+    36  1   19  #GPIO_PB_ZC
+    35  1   20  #GPIO_PC_ZC
+    61  1   120 #GPIO_LIC_CTRL
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+#   up_1    36
+#   up_2    35
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3211覆膜为GX2011
+#   chip id: 0x1001     subid: 0x1041
+
+#==================== 13.10.08.04(HW_VERSION_GX_MASKCHIP_V1) ==================#
+# overview
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_mosi         10    rf_spi_miso         9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    flash_spi_clk
+#   38  flash_spi_mosi      37    flash_spi_miso      36    zc_b
+#   35  zc_c                34    rf_clk              33    flash_spi_cs
+#   32  set(sta)            31    charge_en           30    nc
+#   29  sta_out             28    uart2_tx            46    rf_agc_gain
+#   45  rf_enable           44    rf_txnrx            47    rf_dq0
+#   48  rf_dq1              49    rf_dq2              27    nc
+#   1   tx_led              0     rx_led              3     pa_testp(warning)
+#   2   pa_rx_en            4     pa_tx_en            7     pa_lan_gain_ctr0
+#   6   uart0_tx            5     uart0_rx            8     pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50    rf_dq3              51    rf_dq4
+#   52  rf_dq5              53    rf_dq6              54    rf_dq7
+#   55  rf_dq8              56    rf_dq9              57    rf_dq10
+#   58  rf_dq11             59    rf_pd               61    pa_lic_ctr
+#   62  rf_channel_sw2      64    m_sta(adc_gnd)      65    adc_12v
+#   66  adc_3.3v            67    d_rst(soft reset)   68    zc_a
+#   69  event               12    rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0A0804  #13.10.08.04   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    31  1   12  #GPIO_PM_CHARGE_EN
+    39  1   68  #GPIO_SPI_FLASH_CLK
+    38  1   70  #GPIO_SPI_FLASH_MOSI
+    37  1   71  #GPIO_SPI_FLASH_MISO
+    33  1   69  #GPIO_SPI_FLASH_CS
+
+#================== 13.10.01.29(HW_VERSION_STA_3PS_DM_LOAD_V1) ================#
+# QJ 3PS 带小负载 覆膜HZ3211芯片
+# overview
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_mosi         10    rf_spi_miso         9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    flash_spi_clk
+#   38  flash_spi_mosi      37    flash_spi_miso      36    zc_b
+#   35  zc_c                34    rf_clk              33    flash_spi_cs
+#   32  set(sta)            31    charge_en           30    load_send
+#   29  sta_out             28    uart2_tx            46    rf_agc_gain
+#   45  rf_enable           44    rf_txnrx            47    rf_dq0
+#   48  rf_dq1              49    rf_dq2              27    nc
+#   1   tx_led              0     rx_led              3     pa_testp(warning)
+#   2   pa_rx_en            4     pa_tx_en            7     pa_lan_gain_ctr0
+#   6   uart0_tx            5     uart0_rx            8     pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50    rf_dq3              51    rf_dq4
+#   52  rf_dq5              53    rf_dq6              54    rf_dq7
+#   55  rf_dq8              56    rf_dq9              57    rf_dq10
+#   58  rf_dq11             59    rf_pd               61    pa_lic_ctr
+#   62  rf_channel_sw2      64    m_sta(adc_gnd)      65    adc_12v
+#   66  adc_3.3v            67    d_rst(soft reset)   68    zc_a
+#   69  event               12    rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0A011D  #13.10.1.29
+    mode        1
+    d_hw_ver    0x0D0A0804
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   load send gpio
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
diff --git a/tools/oem/GX2011IIC03_OEM.ini b/tools/oem/GX2011IIC03_OEM.ini
new file mode 100644
index 0000000..6bcc29a
--- /dev/null
+++ b/tools/oem/GX2011IIC03_OEM.ini
@@ -0,0 +1,202 @@
+# GX2011 IIC board, external rf chip, external pa chip.
+general
+    bid     83  #BOARD_GXIIC03
+    mid     2   #MODULE_TYPE_COLLECTOR_II
+    vid     GX
+    fver    1
+
+#=============================== default rc====================================#
+# GX IIC 真实芯片无资源分配
+#===================================== 覆膜资源 ===============================#
+# HZ3211覆膜为GX2011
+#   chip id: 0x1001     subid: 0x1041
+
+#=============================== default rc====================================#
+# overview: extern flash chip
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_do           10    rf_spi_di           9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    flash_spi_cs
+#   38  flash_spi_clk       37    flash_spi_mosi      36    flash_spi_miso
+#   35  rf_clk              34    ir_rx               33    nc
+#   32  485_ctr             31    charge_en           30    ir_tx
+#   29  zc_rise             28    uart2_tx            46    rf_agc_gain
+#   45  rf_enable           44    rf_txnrx            47    rf_dq0
+#   48  rf_dq1              49    rf_dq2              27    nc
+#   1   485_led             0     sta led             3     pa_testp(warning)
+#   2   pa_rx_en            4     pa_tx_en            7     pa_lna_gain_ctr0
+#   6   uart0_tx            5     uart0_rx            8     pa_lna_gain_ctr1
+#   26  pa_lna_gain_ctr2    50    rf_dq3              51    rf_dq4
+#   52  rf_dq5              53    rf_dq6              54    rf_dq6
+#   55  rf_dq8              56    rf_dq9              57    rf_dq10
+#   58  rf_dq11             59    rf_pd               61    rf_channel_sw1
+#   62  rf_channel_sw2      64    pwr_led             65    adc_12v
+#   66  adc_3.3v            67    nc                  68    485_rxd
+#   69  485_txd             12    rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    39  1   69  #GPIO_SPI_FLASH_CS
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+    36  1   71  #GPIO_SPI_FLASH_MISO
+
+    35  1   121 #GPIO_RF_CLK
+    34  1   9   #GPIO_IR_RXD
+    32  1   7   #GPIO_RS485_TXE
+    31  1   12  #GPIO_PM_CHARGE_EN
+    30  1   8   #GPIO_IR_TXD
+    29  1   18  #GPIO_PA_ZC
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    1   1   3   #UART_IR_PORT
+    tx  30
+    rx  34
+
+    2   1   0   #UART_PRINT
+    tx  28
+
+    3   1   2   #UART_METER_PORT
+    tx  69
+    rx  68
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   6   #IOT_RS485_LED
+    ledout  1
+
+    1   1   7   #IOT_PLC_TR_LED
+    ledout  0
+
+    2   1   5   #IOT_PWR_LED
+    ledout  64
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    29
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#=================== 13.10.08.04(HW_VERSION_GX_MASKCHIP_V1) ===================#
+# GX IIC 覆膜HZ3211芯片 资源与GX2011一样
+# overview: extern flash chip
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_do           10    rf_spi_di           9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    flash_spi_cs
+#   38  flash_spi_clk       37    flash_spi_mosi      36    flash_spi_miso
+#   35  rf_clk              34    ir_rx               33    nc
+#   32  485_ctr             31    charge_en           30    ir_tx
+#   29  zc_rise             28    uart2_tx            46    rf_agc_gain
+#   45  rf_enable           44    rf_txnrx            47    rf_dq0
+#   48  rf_dq1              49    rf_dq2              27    nc
+#   1   485_led             0     sta led             3     pa_testp(warning)
+#   2   pa_rx_en            4     pa_tx_en            7     pa_lna_gain_ctr0
+#   6   uart0_tx            5     uart0_rx            8     pa_lna_gain_ctr1
+#   26  pa_lna_gain_ctr2    50    rf_dq3              51    rf_dq4
+#   52  rf_dq5              53    rf_dq6              54    rf_dq6
+#   55  rf_dq8              56    rf_dq9              57    rf_dq10
+#   58  rf_dq11             59    rf_pd               61    rf_channel_sw1
+#   62  rf_channel_sw2      64    pwr_led             65    adc_12v
+#   66  adc_3.3v            67    nc                  68    485_rxd
+#   69  485_txd             12    rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A0804  #13.10.08.04
+    mode        1
+    d_hw_ver    0x00000000
+
+#================== 13.10.04.29(HW_VERSION_IIC_DM_LOAD_V1) ====================#
+# GX IIC 带小负载覆膜HZ3211芯片
+# overview: extern flash chip, load send function
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_do           10    rf_spi_di           9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    flash_spi_cs
+#   38  flash_spi_clk       37    flash_spi_mosi      36    flash_spi_miso
+#   35  rf_clk              34    ir_rx               33    nc
+#   32  485_ctr             31    charge_en           30    ir_tx
+#   29  zc_rise             28    uart2_tx            46    rf_agc_gain
+#   45  rf_enable           44    rf_txnrx            47    rf_dq0
+#   48  rf_dq1              49    rf_dq2              27    nc
+#   1   485_led             0     sta led             3     pa_testp(warning)
+#   2   pa_rx_en            4     pa_tx_en            7     pa_lna_gain_ctr0
+#   6   uart0_tx            5     uart0_rx            8     pa_lna_gain_ctr1
+#   26  pa_lna_gain_ctr2    50    rf_dq3              51    rf_dq4
+#   52  rf_dq5              53    rf_dq6              54    rf_dq6
+#   55  rf_dq8              56    rf_dq9              57    rf_dq10
+#   58  rf_dq11             59    rf_pd               61    rf_channel_sw1
+#   62  rf_channel_sw2      64    pwr_led             65    adc_12v
+#   66  adc_3.3v            67    load_send           68    485_rxd
+#   69  485_txd             12    rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A041D  #13.10.04.29
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   load send gpio
+    67  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO67和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
diff --git a/tools/oem/GX2011STA03_OEM.ini b/tools/oem/GX2011STA03_OEM.ini
new file mode 100644
index 0000000..3f440c2
--- /dev/null
+++ b/tools/oem/GX2011STA03_OEM.ini
@@ -0,0 +1,240 @@
+# GX2011 sta board, external rf chip, external pa chip.
+general
+    bid     80  #BOARD_GXSTA03
+    mid     0   #MODULE_TYPE_STA
+    vid     GX
+    fver    1
+
+#=============================== default rc ====================================#
+# overview
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_do           10    rf_spi_di           9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    pa_lic_ctr
+#   38  nc                  37    nc                  36    nc
+#   35  nc                  34    rf_clk              32    set(sta)
+#   30  nc                  14    nc                  29    sta_out
+#   28  uart2_tx            31    nc                  46    rf_agc_gain
+#   45  rf_enable           44    rf_txnrx            47    rf_dq0
+#   48  rf_dq1              49    rf_dq2              1     tx_led
+#   0   rx_led              3     pa_testp(warning)   2     pa_rx_en
+#   4   pa_tx_en            7     pa_lna_gain_ctr0    6     uart0_tx
+#   5   uart0_rx            8     pa_lna_gain_ctr1    26    pa_lna_gain_ctr2
+#   50  rf_dq3              51    rf_dq4              52    rf_dq5
+#   53  rf_dq6              54    rf_dq7              55    rf_dq8
+#   56  rf_dq9              57    rf_dq10             58    rf_dq11
+#   59  rf_pd               61    rf_channel_sw1      62    rf_channel_sw2
+#   64  m_sta(adc_gnd)      65    adc_12v             66    nc
+#   67  d_rst(soft reset)   68    zc_a                69    event
+#   12  rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    39  1   120 #GPIO_LIC_CTRL
+
+    34  1   121 #GPIO_RF_CLK
+    32  1   17  #GPIO_GOLDEN_SET
+    29  1   1   #GPIO_STA_OUT
+    3   1   10  #GPIO_GEODE_OVT
+    5   1   24  #GPIO_GOLDEN_RXD0
+    6   1   34  #GPIO_GOLDEN_TXD0
+    67  1   13  #GPIO_RST_CTRL
+    68  1   18  #GPIO_PA_ZC
+    69  1   0   #GPIO_PLC_EVENT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3211覆膜为GX2011
+#   chip id: 0x1001     subid: 0x1041
+
+#=================== 13.10.08.04(HW_VERSION_GX_MASKCHIP_V1) ===================#
+# overview
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_do           10    rf_spi_di           9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    pa_lic_ctr
+#   38  flash_spi_clk       37    flash_spi_mosi      36    flash_spi_miso
+#   35  flash_spi_cs        34    rf_clk              32    set(sta)
+#   31  charge_en           30    nc                  29    sta_out
+#   28  uart2_tx            46    rf_agc_gain         45    rf_enable
+#   44  rf_txnrx            47    rf_dq0              48    rf_dq1
+#   49  rf_dq2              27    nc                  1     tx_led
+#   0   rx_led              3     pa_testp(warning)   2     pa_rx_en
+#   4   pa_tx_en            7     pa_lna_gain_ctr0    6     uart0_tx
+#   5   uart0_rx            8     pa_lna_gain_ctr1    26    pa_lna_gain_ctr2
+#   50  rf_dq3              51    rf_dq4              52    rf_dq5
+#   53  rf_dq6              54    rf_dq7              55    rf_dq8
+#   56  rf_dq9              57    rf_dq10             58    rf_dq11
+#   59  rf_pd               61    rf_channel_sw1      62    rf_channel_sw2
+#   64  m_sta(adc_gnd)      65    adc_12v             66    adc_3v3
+#   67  d_rst(soft reset)   68    zc_a                69    event
+#   12  rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A0804  #13.10.08.04   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+    36  1   71  #GPIO_SPI_FLASH_MISO
+    35  1   69  #GPIO_SPI_FLASH_CS
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+
+#================== 13.10.01.29(HW_VERSION_STA_3PS_DM_LOAD_V1) ================#
+# overview, external pa, external rf, load_send
+# gpio  function            gpio  function            gpio  function
+#   11  rf_spi_do           10    rf_spi_di           9     rf_spi_cs
+#   42  rf_mclk             43    rf_fclk             39    pa_lic_ctr
+#   38  flash_spi_clk       37    flash_spi_mosi      36    flash_spi_miso
+#   35  flash_spi_cs        34    rf_clk              32    set(sta)
+#   31  charge_en           30    load_send           29    sta_out
+#   28  uart2_tx            46    rf_agc_gain         45    rf_enable
+#   44  rf_txnrx            47    rf_dq0              48    rf_dq1
+#   49  rf_dq2              27    nc                  1     tx_led
+#   0   rx_led              3     pa_testp(warning)   2     pa_rx_en
+#   4   pa_tx_en            7     pa_lna_gain_ctr0    6     uart0_tx
+#   5   uart0_rx            8     pa_lna_gain_ctr1    26    pa_lna_gain_ctr2
+#   50  rf_dq3              51    rf_dq4              52    rf_dq5
+#   53  rf_dq6              54    rf_dq7              55    rf_dq8
+#   56  rf_dq9              57    rf_dq10             58    rf_dq11
+#   59  rf_pd               61    rf_channel_sw1      62    rf_channel_sw2
+#   64  m_sta(adc_gnd)      65    adc_12v             66    adc_3v3
+#   67  d_rst(soft reset)   68    zc_a                69    event
+#   12  rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A011D  #13.10.1.29
+    mode        1
+    d_hw_ver    0x0D0A0804
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   load send gpio
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+#=============================== 13.10.01.12(HW_VERSION_STA_CKQ_DM_V1) ==============#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   12  rf_spi_clk          42      rf_mclk             43      rf_fclk
+#   39  pa_lic_ctr          34      nc                  32      set(sta)
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc0_gnd)     65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(soft reset)   68      zc_a_up
+#   69  event
+
+rc_hdr
+    hw_ver      0x0D0A010C  #13.10.01.12   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    34  255   255 #GPIO_SPI_RF_CLK
\ No newline at end of file
diff --git a/tools/oem/HTR_OEM.ini b/tools/oem/HTR_OEM.ini
new file mode 100644
index 0000000..1dafc5f
--- /dev/null
+++ b/tools/oem/HTR_OEM.ini
@@ -0,0 +1,30 @@
+general
+ bid 105
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ rx 9
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 32
+ rx 33
+ rs485 23
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 47
diff --git a/tools/oem/HTZD3201BRMT03_OEM.ini b/tools/oem/HTZD3201BRMT03_OEM.ini
new file mode 100644
index 0000000..0f60d66
--- /dev/null
+++ b/tools/oem/HTZD3201BRMT03_OEM.ini
@@ -0,0 +1,133 @@
+# HZ3201 3C board, external pa chip
+general
+    bid     94  #BOARD_BRMTI3C03
+    mid     2   #MODULE_TYPE_COLLECTOR_II
+    vid     HT
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  att_spi_mosi        10      att_spi_miso        9       att_spi_cs
+#   42  kl2_sda             43      kl2_scl             39      pwr_det
+#   38  mo_clk_flash        37      mo_si_flash         36      mi_so_flash
+#   35  mo_cs_flash         34      4851_rxd            33      4851_txd
+#   32  bt_txd              31      bt_rxd              30      load_send
+#   29  charge_en           28      uart2_tx(log)       46      att_nrst
+#   45  4852_ctr            44      4851_ctr            47      zc_a
+#   48  zc_b                49      zc_c                27      bt_rst
+#   1   tx_led(485)         0       rx_led(plc)         3       pa_testp(warning)
+#   2   pa_a_rx_en          4       pa_a_tx_en          7       pa_lan_gain_ctr0
+#   6   (4852tx)uart0_tx    5       (4852rx)uart0_rx    8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      nc                  51      nc
+#   52  nc                  53      nc                  54      nc
+#   55  nc                  56      nc                  57      nc
+#   58  nc                  59      nc                  61      nc
+#   62  nc                  64      ia+                 65      ia-
+#   66  ib+                 67      ib-                 68      ic+
+#   69  ic-                 12      att_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function(to see iot_board_api.h about gpio type)
+#   A   B   C
+#   spi gpio query by meter chip
+    9   1   61  #GPIO_METER_CS_CTRL
+    11  1   64  #GPIO_METER_MOSI_CTRL
+    10  1   63  #GPIO_METER_MISO_CTRL
+    12  1   62  #GPIO_METER_CLK_CTRL
+    46  1   40  #GPIO_METER_RST_CTRL
+
+    42  1   84  #GPIO_EXT_RTC_I2C_SDA
+    43  1   83  #GPIO_EXT_RTC_I2C_SCL
+
+    39  1   123 #GPIO_P12V_DETECTION
+
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+    36  1   71  #GPIO_SPI_FLASH_MISO
+    35  1   69  #GPIO_SPI_FLASH_CS
+
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+    29  1   12  #GPIO_PM_CHARGE_EN
+
+    45  1   111 #GPIO_RS485_TXE_2
+
+    44  1   7   #GPIO_RS485_TXE
+
+    47  1   18  #GPIO_PA_ZC
+    48  1   19  #GPIO_PB_ZC
+    49  1   20  #GPIO_PC_ZC
+
+    27  1   58  #GPIO_BT_RST_CTRL
+
+    3   1   10  #GPIO_GEODE_OVT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    3   1   2   #UART_METER_PORT
+    tx  33
+    rx  34
+
+    1   1   6   #UART_EXT_BT_PORT
+    tx  32
+    rx  31
+
+    2   1   0   #UART_PRINT
+    tx  28
+
+    0   1   10  #UART_RS485_PORT_2
+    tx  6
+    rx  5
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   6   #IOT_RS485_LED
+    ledout  1
+
+    1   1   7   #IOT_PLC_TR_LED
+    ledout  0
+
+#zc     # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+#   up_0    47
+#   up_1    48
+#   up_2    49
+
+pa      # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+pwm     #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
\ No newline at end of file
diff --git a/tools/oem/HTZD3201BSRM03_OEM.ini b/tools/oem/HTZD3201BSRM03_OEM.ini
new file mode 100644
index 0000000..bd7ac6f
--- /dev/null
+++ b/tools/oem/HTZD3201BSRM03_OEM.ini
@@ -0,0 +1,198 @@
+# HZ3201 bsrm board, external rf chip, external pa chip
+general
+    bid     90  #BOARD_HTZDBSRM03
+    mid     0   #MODULE_TYPE_STA
+    vid     HT
+    fver    1
+
+#=============================== default rc(CHINT) ===============================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      zc_a
+#   38  uart1_tx            37      uart1_rx            36      pwr_det
+#   35  event               34      rf_clk              33      nc
+#   32  nc                  31      nc                  30      nc
+#   29  nc                  28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp(warning)   2       pa_a_rx_en
+#   4   pa_a_tx_en          7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      pa_lic_ctr          62      rf_channel_sw2
+#   64  adc0_a+             65      adc1_a-             66      adc2_b+
+#   67  adc3_b-             68      adc4_c+             69      adc5_c-
+#   12  rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function(to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    9   1   108 #GPIO_SPI_RF_CS
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    12  1   107 #GPIO_SPI_RF_CLK
+
+    39  1   18  #GPIO_PA_ZC
+    36  1   123 #GPIO_P12V_DETECTION
+    35  1   0   #GPIO_PLC_EVENT
+    34  1   121 #GPIO_RF_CLK
+    61  1   120 #GPIO_LIC_CTRL
+
+    3   1   10  #GPIO_GEODE_OVT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28
+
+    1   1   2   #UART_METER_PORT
+    tx  38
+    rx  37
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    39
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#================== 13.10.01.29(HW_VERSION_STA_3PS_DM_LOAD_V1) ================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      zc_a
+#   38  uart1_tx            37      uart1_rx            36      pwr_det
+#   35  event               34      rf_clk              33      nc
+#   32  nc                  31      nc                  30      send
+#   29  nc                  28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp(warning)   2       pa_a_rx_en
+#   4   pa_a_tx_en          7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      pa_lic_ctr          62      rf_channel_sw2
+#   64  adc0_a+             65      adc1_a-             66      adc2_b+
+#   67  adc3_b-             68      adc4_c+             69      adc5_c-
+#   12  rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A011D  #13.10.1.29
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   load send gpio
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+#=================== 13.10.01.10(HW_VERSION_BSRM_DM_V1) ======================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  uart1_tx            37      uart1_rx            36      nc
+#   35  event               34      rf_clk              33      nc
+#   32  zc_a                31      nc                  30      nc
+#   29  nc                  28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp(warning)   2       pa_a_rx_en
+#   4   pa_a_tx_en          7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      rf_channel_sw1      62      rf_channel_sw2
+#   64  pwr_det             65      adc_test            66      nc
+#   67  nc                  68      nc                  69      nc
+#   12  rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A010A  #13.10.01.10
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    39  1   120 #GPIO_LIC_CTRL
+    36  255 255 #GPIO_NO_VALID
+    32  1   18  #GPIO_PA_ZC
+    61  255 255 #GPIO_NO_VALID
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   0   #ADC_PM_12V  (Temporary annotation)
diff --git a/tools/oem/HTZD3201CCO03_AMPSG_OEM.ini b/tools/oem/HTZD3201CCO03_AMPSG_OEM.ini
new file mode 100644
index 0000000..eba40e1
--- /dev/null
+++ b/tools/oem/HTZD3201CCO03_AMPSG_OEM.ini
@@ -0,0 +1,166 @@
+# HZ3201 cco amp board, external rf chip, external pa chip
+# Use the same board ID of HZ3201 cco
+general
+    bid     45  #BOARD_HTZDCCO03
+    mid     1   #MODULE_TYPE_CCO
+    vid     HT
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      zc_c_2
+#   38  zc_c_1              37      zc_b_2              36      zc_b_1
+#   35  zc_a_2              34      pa_led\uart1_tx     33      pb_led\uart1_rx
+#   32  pc_led              31      charge_en           30      pa_c_tx_en
+#   29  pa_c_rx_en          28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp(warning)   2       pa_a_rx_en
+#   4   pa_a_tx_en          7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      uart2_rx            62      rf_channel_sw2(io)
+#   64  m_sta(adc_gnd)      65      adc_12v             66      adc_3.3v
+#   67  pa_b_tx_en          68      zc_a_1              69      pa_b_rx_en
+#   12  rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function(to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    9   1   108 #GPIO_SPI_RF_CS
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    12  1   107 #GPIO_SPI_RF_CLK
+
+    3   1   10  #GPIO_GEODE_OVT
+
+    35  1   18  #GPIO_PA_ZC
+    37  1   19  #GPIO_PB_ZC
+    39  1   20  #GPIO_PC_ZC
+    68  1   44  #GPIO_PA_ZC_EXT
+    36  1   45  #GPIO_PB_ZC_EXT
+    38  1   46  #GPIO_PC_ZC_EXT
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    3   1   1   #UART_CLI_PORT
+    #tx  28
+    rx  61
+
+    1   1   0   #UART_PRINT
+    tx  34
+
+    2   0   0   #UART_PRINT
+    tx  28
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+    6   0   14  #UART_ICC_PORT  #kernel 0 use uart port 6
+    tx  60      #Unelicited internal GPIO60
+    rx  63      #Unelicited internal GPIO63
+    rts 40      #Unelicited internal GPIO40
+    cts 14      #Unelicited internal GPIO14
+
+    7   1   14  #UART_ICC_PORT  #kernel 1 use uart port 7
+    tx  63      #Unelicited internal GPIO63
+    rx  60      #Unelicited internal GPIO60
+    rts 14      #Unelicited internal GPIO14
+    cts 40      #Unelicited internal GPIO40
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   2   #IOT_PLC_PHASE_A_LED
+    ledout  34
+
+    1   1   3   #IOT_PLC_PHASE_B_LED
+    ledout  33
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  32
+
+    3   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    4   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+#   up_0    35
+#   up_1    37
+#   up_2    39
+#   down_0  68
+#   down_1  36
+#   down_2  38
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    rx_en_1 69  #Phase B Enable receiving
+    tx_en_1 67  #Phase B Enable sending
+    rx_en_2 29  #Phase C Enable receiving
+    tx_en_2 30  #Phase C Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
diff --git a/tools/oem/HTZD3201CCO03_OEM.bin b/tools/oem/HTZD3201CCO03_OEM.bin
new file mode 100644
index 0000000..6e053b1
Binary files /dev/null and b/tools/oem/HTZD3201CCO03_OEM.bin differ
diff --git a/tools/oem/HTZD3201CCO03_OEM.ini b/tools/oem/HTZD3201CCO03_OEM.ini
new file mode 100644
index 0000000..441e14f
--- /dev/null
+++ b/tools/oem/HTZD3201CCO03_OEM.ini
@@ -0,0 +1,346 @@
+# HZ3201 cco board, external rf chip, external pa chip
+general
+    bid     45  #BOARD_HTZDCCO03
+    mid     1   #MODULE_TYPE_CCO
+    vid     HT
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      zc_c_2
+#   38  zc_c_1              37      zc_b_2              36      zc_b_1
+#   35  zc_a_2              34      pa_led\uart1_tx     33      pb_led\uart1_rx
+#   32  pc_led              31      charge_en           30      pa_c_tx_en
+#   29  pa_c_rx_en          28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp(warning)   2       pa_a_rx_en
+#   4   pa_a_tx_en          7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      uart2_rx            62      rf_channel_sw2(io)
+#   64  m_sta(adc_gnd)      65      adc_12v             66      adc_3.3v
+#   67  pa_b_tx_en          68      zc_a_1              69      pa_b_rx_en
+#   12  rf_spi_clk          27      set(mac,for cco 09 version)
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function(to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    9   1   108 #GPIO_SPI_RF_CS
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    12  1   107 #GPIO_SPI_RF_CLK
+
+    3   1   10  #GPIO_GEODE_OVT
+
+    35  1   18  #GPIO_PA_ZC
+    37  1   19  #GPIO_PB_ZC
+    39  1   20  #GPIO_PC_ZC
+    68  1   44  #GPIO_PA_ZC_EXT
+    36  1   45  #GPIO_PB_ZC_EXT
+    38  1   46  #GPIO_PC_ZC_EXT
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+    27  1   76  #GPIO_MAC_SET
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   1   #UART_CLI_PORT
+    tx  28
+    rx  61
+
+    1   1   0   #UART_PRINT
+    tx  34
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   2   #IOT_PLC_PHASE_A_LED
+    ledout  34
+
+    1   1   3   #IOT_PLC_PHASE_B_LED
+    ledout  33
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  32
+
+    3   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    4   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+#   up_0    35
+#   up_1    37
+#   up_2    39
+#   down_0  68
+#   down_1  36
+#   down_2  38
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    rx_en_1 69  #Phase B Enable receiving
+    tx_en_1 67  #Phase B Enable sending
+    rx_en_2 29  #Phase C Enable receiving
+    tx_en_2 30  #Phase C Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#================= 31.20.02.00(HW_VERSION_CCO_USB_V2) =========================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      zc_c_2
+#   38  zc_c_1              37      zc_b_2              36      zc_b_1
+#   35  zc_a_2              34      uart1_tx            33      run_led
+#   32  uart3_tx            31      uart3_rx            30      pa_c_tx_en
+#   29  pa_c_rx_en          28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp(warning)   2       pa_a_rx_en
+#   4   pa_a_tx_en          7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      uart2_rx            62      rf_channel_sw2(io)
+#   64  adc_cal             65      adc_12v             66      boot0(gd32)
+#   67  pa_b_tx_en          68      zc_a_1              69      pa_b_rx_en
+#   12  rf_spi_clk          27      rst(gd32)
+
+rc_hdr
+    hw_ver      0x1F140200  #31.20.02.00   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function(to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    32   255   255
+    31   255   255
+    34   255   255
+    66   1   74 #GPIO_VC_EXT_CHIP_BOOT
+    27   1   75 #GPIO_VC_EXT_CHIP_RST
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    3   1   5   #UART_EXT_CHIP
+    tx  32
+    rx  31
+
+# disable uart0 meter port function
+    0   255   255
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+    2   1   5   #IOT_PWR_LED
+    ledout  33
+
+    3   255   255   #IOT_LED_TYPE_INVALID
+    4   255   255   #IOT_LED_TYPE_INVALID
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    2   255   255   #ADC_TYPE_INVALID
+
+#===============================13.10.08.11(HW_VERSION_CCO_DM_V2)====================================#
+# overview, for hx oversea
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      nc
+#   38  zc_c_1              37      nc                  36      zc_b_1
+#   35  nc                  34      plc_led\uart1_tx    33      rf_led\uart1_rx
+#   32  nc                  31      charge_en           30      pa_c_tx_en
+#   29  pa_c_rx_en          28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp(warning)   2       pa_a_rx_en
+#   4   pa_a_tx_en          7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      uart2_rx            62      rf_channel_sw2(io)
+#   64  m_sta(adc_gnd)      65      adc_12v             66      adc_3.3v
+#   67  pa_b_tx_en          68      zc_a_1              69      pa_b_rx_en
+#   12  rf_spi_clk          27      nc
+
+rc_hdr
+    hw_ver      0x0D0A080B  #13.10.08.11   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function(to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    35  255 255  #GPIO_NO_VALID
+    37  255 255  #GPIO_NO_VALID
+    39  255 255  #GPIO_NO_VALID
+    32  255 255  #GPIO_NO_VALID
+    68  1   18   #GPIO_PA_ZC
+    36  1   19   #GPIO_PB_ZC
+    38  1   20   #GPIO_PC_ZC
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   2   #IOT_PLC_PHASE_A_LED
+    ledout  34
+
+    1   1   10  #IOT_RF_LED
+    ledout  33
+
+    2   1   0   #IOT_PLC_TX_LED
+    ledout  0
+
+    3   1   1   #IOT_PLC_RX_LED
+    ledout  1
+
+    4   255 255
+
+#===============================13.10.08.12(HW_VERSION_CCO_DM_V3)====================================#
+# overview, for hx and kx oversea
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      rf_channel_sw1(io)
+#   38  zc_c_1              37      csd                 36      zc_b_1
+#   35  nc                  34      plc_led\uart1_tx    33      rf_led\uart1_rx
+#   32  pc_led              31      charge_en           30      pa_c_tx_en
+#   29  pa_c_rx_en          28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              27      nc
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_a_rx_en          4       pa_a_tx_en          7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      uart2_rx
+#   62  rf_channel_sw2(io)  64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      pa_b_tx_en          68      zc_a_1
+#   69  pa_b_rx_en          12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A080C  #13.10.08.12   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function(to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    35  255 255  #GPIO_NO_VALID
+    39  255 255  #GPIO_NO_VALID
+    37  1   133  #GPIO_RF_PA_CSD
+    62  1   134  #GPIO_RF_PA_CTX
+    68  1   18   #GPIO_PA_ZC
+    36  1   19   #GPIO_PB_ZC
+    38  1   20   #GPIO_PC_ZC
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   2   #IOT_PLC_PHASE_A_LED
+    ledout  34
+
+    1   1   10  #IOT_RF_LED
+    ledout  33
+
+    2   1   0   #IOT_PLC_TX_LED
+    ledout  0
+
+    3   1   1   #IOT_PLC_RX_LED
+    ledout  1
+
+    4   255 255
\ No newline at end of file
diff --git a/tools/oem/HTZD3201CKB03_OEM.ini b/tools/oem/HTZD3201CKB03_OEM.ini
new file mode 100644
index 0000000..774554e
--- /dev/null
+++ b/tools/oem/HTZD3201CKB03_OEM.ini
@@ -0,0 +1,115 @@
+# HZ3201 ckb board, external rf chip, external pa chip.
+general
+    bid     73  #BOARD_HTZDCKB03
+    mid     0   #MODULE_TYPE_STA
+    vid     HT
+    fver    1
+
+#=============================== default rc====================================#
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  nc                  37      nc                  36      nc
+#   35  nc                  34      rf_clk              32      set
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      m_sta(adc0)         65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(adc3)         68      zc_a_up(adc4)
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    39  1   120 #GPIO_LIC_CTRL
+    34  1   121 #GPIO_RF_CLK
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   12  #GPIO_PM_CHARGE_EN
+    29  1   1   #GPIO_STA_OUT
+    3   1   10  #GPIO_GEODE_OVT
+    67  1   13  #GPIO_RST_CTRL
+    68  1   18  #GPIO_PA_ZC
+    69  1   0   #GPIO_PLC_EVENT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
diff --git a/tools/oem/HTZD32113PS03_OEM.bin b/tools/oem/HTZD32113PS03_OEM.bin
new file mode 100755
index 0000000..aa94acd
Binary files /dev/null and b/tools/oem/HTZD32113PS03_OEM.bin differ
diff --git a/tools/oem/HTZD32113PS03_OEM.ini b/tools/oem/HTZD32113PS03_OEM.ini
new file mode 100644
index 0000000..404e599
--- /dev/null
+++ b/tools/oem/HTZD32113PS03_OEM.ini
@@ -0,0 +1,472 @@
+# HZ3211 3ps board, external rf chip, external pa chip.
+general
+    bid     51  #BOARD_HTZD3PS03
+    mid     4   #MODULE_TYPE_3_PHASE_STA
+    vid     HT
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             32      set(sta)
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk          36      zc_b
+#   35  zc_c                39      pa_lic_ctr          34      rf_clk
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    3   1   10  #GPIO_GEODE_OVT
+
+    32  1   17  #GPIO_GOLDEN_SET
+    29  1   1   #GPIO_STA_OUT
+    69  1   0   #GPIO_PLC_EVENT
+    67  1   13  #GPIO_RST_CTRL
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+    68  1   18  #GPIO_PA_ZC
+    36  1   19  #GPIO_PB_ZC
+    35  1   20  #GPIO_PC_ZC
+
+    39  1   120 #GPIO_LIC_CTRL
+    34  1   121 #GPIO_RF_CLK
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+#   up_1    36
+#   up_2    35
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#================== 13.10.01.29(HW_VERSION_STA_3PS_DM_LOAD_V1) ================#
+# overview, external pa, external rf, load_send
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             32      set(sta)
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk          36      zc_b
+#   35  zc_c                39      pa_lic_ctr          30      load_send
+rc_hdr
+    hw_ver      0x0D0A011D  #13.10.1.29
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   load send gpio
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+#================== 13.15.1.9(HW_VERSION_STA_3PS_DM_FLASH_EXT_V1) ================#
+# overview
+# add: 61 pa_lic_ctr, 39 38 37 33 flash spi
+# remove: 61 rf_channel_sw(io)
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             32      set(sta)
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      pa_lic_ctr
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk          36      zc_b
+#   35  zc_c                39      flash_spi_clk       34      rf_clk
+#   30  nc                  38      flash_spi_mosi      37      flash_spi_miso
+#   33  flash_spi_cs
+rc_hdr
+    hw_ver      0x0D0F0109  #13.15.1.9
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    39  1   68  #GPIO_SPI_FLASH_CLK
+    38  1   70  #GPIO_SPI_FLASH_MOSI
+    37  1   71  #GPIO_SPI_FLASH_MISO
+    33  1   69  #GPIO_SPI_FLASH_CS
+
+    61  1   120 #GPIO_LIC_CTRL
+
+#================== 13.10.02.11(HW_VERSION_STA_3PS_DM_V2) ================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  tx/rx_switch_a      43      rf_fclk             39      flash_spi_clk
+#   38  flash_spi_mosi      37      flash_spi_miso      36      zc_b
+#   35  zc_c                34      rf_clk              33      flash_spi_cs
+#   32  set(sta)            31      charge_en           30      nc
+#   29  sta_out             28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              27      tx/rx_switch_b
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      tx/rx_switch_c
+#   62  rf_channel_sw2(io)  64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A020B  #13.10.02.11   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    42  1   124 #GPIO_TXRX_SWITCH_A
+    39  1   68  #GPIO_SPI_FLASH_CLK
+    38  1   70  #GPIO_SPI_FLASH_MOSI
+    37  1   71  #GPIO_SPI_FLASH_MISO
+    33  1   69  #GPIO_SPI_FLASH_CS
+    27  1   125 #GPIO_TXRX_SWITCH_B
+    61  1   126 #GPIO_TXRX_SWITCH_C
+
+#================== 13.10.2.12(HW_VERSION_STA_3PS_DM_V3) ================#
+# overview, for sumsung oversea
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             32      nc
+#   31  charge_en           29      nc                  28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  nc                  12      rf_spi_clk          36      zc_b
+#   35  zc_c                39      pa_lic_ctr          34      rf_clk
+#   38  net_led
+
+rc_hdr
+    hw_ver      0x0D0A020C  #13.10.2.12
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    32  255 255  #GPIO_NO_VALID
+    29  255 255  #GPIO_NO_VALID
+    69  255 255  #GPIO_NO_VALID
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    2   1   8   #IOT_PLC_NET_LED
+    ledout  38
+
+#============= 13.40.02.13(HW_VERSION_3PS_LOAD_FLASH_EXT_V3) ==========#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  nc                  10      nc                  9       nc
+#   42  nc                  43      nc                  39      mo_clk_flash
+#   38  mo_si_flash         37      mi_so_flash         36      zc_b_up
+#   35  zc_c_up             34      nc                  33      mo_cs_flash
+#   32  set                 31      charge_en           30      load_send
+#   29  sta_out             28      uart2_tx            46      nc
+#   45  nc                  44      nc                  47      nc
+#   48  nc                  49      nc                  27      multi
+#   1   tx_led              0       rx_led              3       pa_testp
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      nc                  51      nc
+#   52  nc                  53      nc                  54      nc
+#   55  nc                  56      nc                  57      nc
+#   58  nc                  59      nc                  61      pa_lic_crt
+#   62  nc                  64      m_sta(adc_0)        65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a_up
+#   69  event               12      nc
+
+rc_hdr
+    hw_ver      0x0D28020D  #13.40.02.13
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  255 255 #GPIO_SPI_RF_CLK
+    11  255 255 #GPIO_SPI_RF_MOSI
+    10  255 255 #GPIO_SPI_RF_MISO
+    9   255 255 #GPIO_SPI_RF_CS
+
+    39  1   68  #GPIO_SPI_FLASH_CLK
+    38  1   70  #GPIO_SPI_FLASH_MOSI
+    37  1   71  #GPIO_SPI_FLASH_MISO
+    33  1   69  #GPIO_SPI_FLASH_CS
+
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+    27  1   127 #GPIO_MULTI_PULSE
+
+    34  255 255 #GPIO_RF_CLK
+
+    61  1   120 #GPIO_LIC_CTRL
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+#================== 13.15.1.13(HW_VERSION_STA_3PS_DM_LOAD_FLASH_EXT_V2) ================#
+# overview
+# add: load_send
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             32      set(sta)
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      pa_lic_ctr
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk          36      zc_b
+#   35  zc_c                39      flash_spi_clk       34      rf_clk
+#   30  load_send           38      flash_spi_mosi      37      flash_spi_miso
+#   33  flash_spi_cs
+rc_hdr
+    hw_ver      0x0D0F010D  #13.15.1.13
+    mode        1
+    d_hw_ver    0x0D0F0109
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   load send gpio
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+#================== 13.10.2.14(HW_VERSION_STA_3PS_DM_V4) ================#
+# overview, for hx oversea
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  charge_en           37      nc                  36      zc_b
+#   35  zc_c                34      rf_clk              33      nc
+#   32  nc                  31      nc                  30      nc
+#   29  nc                  28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              27      nc
+#   1   tx/rx led           0       net_led             3       testp
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0A020E  #13.10.2.14
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    31  255 255  #GPIO_NO_VALID
+    32  255 255  #GPIO_NO_VALID
+    29  255 255  #GPIO_NO_VALID
+    38  1    12  #GPIO_PM_CHARGE_EN
+
+#================== 13.10.02.16(HW_VERSION_3PS_SPG_DM_FLASH_EXT_V1) ================#
+# overview
+# add: 61 pa_lic_ctr, 39 38 37 33 flash spi,27 multi
+# remove: 61 rf_channel_sw(io)
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      flash_spi_clk
+#   38  flash_spi_mosi      37      flash_spi_miso      36      zc_b
+#   35  zc_c                34      rf_clk              33      flash_spi_cs
+#   32  set(sta)            31      charge_en           30      nc
+#   29  sta_out             28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              27      multi
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      pa_lic_ctr
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0A0210  #13.10.02.16
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    39  1   68  #GPIO_SPI_FLASH_CLK
+    38  1   70  #GPIO_SPI_FLASH_MOSI
+    37  1   71  #GPIO_SPI_FLASH_MISO
+    33  1   69  #GPIO_SPI_FLASH_CS
+
+    61  1   120 #GPIO_LIC_CTRL
+    27  1   127 #GPIO_MULTI_PULSE
\ No newline at end of file
diff --git a/tools/oem/HTZD3211IIC03_OEM.bin b/tools/oem/HTZD3211IIC03_OEM.bin
new file mode 100755
index 0000000..771ddbb
Binary files /dev/null and b/tools/oem/HTZD3211IIC03_OEM.bin differ
diff --git a/tools/oem/HTZD3211IIC03_OEM.ini b/tools/oem/HTZD3211IIC03_OEM.ini
new file mode 100644
index 0000000..8720022
--- /dev/null
+++ b/tools/oem/HTZD3211IIC03_OEM.ini
@@ -0,0 +1,168 @@
+# see KL3_EXAMPLE_OEM.ini for file format description
+# HZ3211 3ps board, external rf chip, external pa chip.
+general
+    bid     56  #BOARD_HTZDIIC03
+    mid     2   #MODULE_TYPE_COLLECTOR_II
+    vid     HT
+    fver    1
+
+#=============================== default rc====================================#
+# overview: extern flash chip
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      ext_flash_cs
+#   38  ext_flash_clk       36      ext_flash_do        37      ext_flash_di
+#   34  ir_rx               32      485_ctr             31      charge_en
+#   30  ir_tx               29      zc_up               28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   0   sta led             1       tx\rx led           3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      pwr_led             65      adc_12v
+#   66  adc_3.3v            68      485_rxd             69      485_txd
+#   12  rf_spi_clk          35      rf_clk
+
+rc_hdr
+#   the first version of each product line defaults to 0
+    hw_ver      0x00000000
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+#   extern flash spi gpio
+    39  1   69  #GPIO_SPI_FLASH_CS
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    36  1   71  #GPIO_SPI_FLASH_MISO
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+
+    32  1   7   #GPIO_RS485_TXE
+    31  1   12  #GPIO_PM_CHARGE_EN
+    29  1   18  #GPIO_PA_ZC
+
+    30  1   8   #GPIO_IR_TXD
+    34  1   9   #GPIO_IR_RXD
+
+    35  1   121 #GPIO_RF_CLK
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+#   current serial port is not multiplexed, uart0(6\5) as download port reserved
+    1   1   3   #UART_IR_PORT
+    tx  30
+    rx  34
+
+    2   1   0   #UART_PRINT
+    tx  28
+
+    3   1   2   #UART_METER_PORT
+    tx  69
+    rx  68
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   6   #IOT_RS485_LED
+    ledout  1
+
+    1   1   7   #IOT_PLC_TR_LED
+    ledout  0
+
+    2   1   5   #IOT_PWR_LED
+    ledout  64
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    29
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#============================ 13.10.04.29 rc ==================================#
+# overview: extern flash chip, load send function
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      ext_flash_cs
+#   38  ext_flash_clk       36      ext_flash_do        37      ext_flash_di
+#   34  ir_rx               32      485_ctr             31      charge_en
+#   30  ir_tx               29      zc_up               28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   0   sta led             1       tx\rx led           3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      pwr_led             65      adc_12v
+#   66  adc_3.3v            67      load_send(H)        68      485_rxd
+#   69  485_txd             12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A041D  #13.10.04.29
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    67  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO67和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
diff --git a/tools/oem/HTZD3211PT03_OEM.ini b/tools/oem/HTZD3211PT03_OEM.ini
new file mode 100644
index 0000000..5b074cd
--- /dev/null
+++ b/tools/oem/HTZD3211PT03_OEM.ini
@@ -0,0 +1,152 @@
+# HZ3211 sta board, external rf chip, external pa chip.
+general
+    bid     99  #BOARD_HTZDPT03
+    mid     0   #MODULE_TYPE_STA
+    vid     HT
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# pin_num  pin_name          function
+#   1      GPIO11            JIG_DET
+#   2      GPIO10            NC
+#   3      GPIO9             NC
+#   4      GPIO42            NC
+#   5      GPIO43            NC
+#   8      GPIO39            sda
+#   9      GPIO38            sck
+#   10     GPIO37            NC
+#   11     GPIO36            NC
+#   12     GPIO35            NC
+#   13     GPIO34            NC
+#   14     GPIO33            NC
+#   15     GPIO32            NC
+#   16     GPIO31            NC
+#   18     GPIO30            NC
+#   19     GPIO29            NC
+#   20     GPIO28            tx2_bug
+#   24     GPIO46            reserved
+#   25     GPIO45            reserved
+#   26     GPIO44            reserved
+#   27     GPIO47            reserved
+#   28     GPIO48            reserved
+#   29     GPIO49            reserved
+#   30     GPIO27            NC
+#   31     GPIO01/TMS        NC
+#   32     GPIO00/TCK        relay_en
+#   33     GPIO03/TDO        adc_ctrl1
+#   34     GPIO02/TDI        adc_ctrl2
+#   35     GPIO04/TRST       pwr_ctrl
+#   36     GPIO07            relay_hplc
+#   39     GPIO06/UART0_TX   tx0
+#   40     GPIO05/UART0_RX   rx0
+#   41     GPIO08            NC
+#   42     GPIO26            NC
+#   51     GPIO50            multi_dut
+#   52     GPIO51            set_dut
+#   53     GPIO52            rst_dut
+#   54     GPIO53            sta_dut
+#   55     GPIO54            event_dut
+#   56     GPIO55            gnd_det(spg21 sta pin12)
+#   57     GPIO56            reserved
+#   58     GPIO57            tx2(reserved)
+#   59     GPIO58            rx2(reserved)
+#   60     GPIO59            tx1(reserved)
+#   61     GPIO61            rx1(reserved)
+#   62     GPIO62            NC
+#   68     ADC0/GPIO64       vcore_dut
+#   69     ADC1/GPIO65       3v3_dut
+#   70     ADC2/GPIO66       12v
+#   71     ADC3/GPIO67       iout
+#   72     ADC4/GPIO68       ch1_a+
+#   73     ADC5/GPIO69       ch1_a-
+#   76     GPIO12            NC
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+
+    11  1   23   #GPIO_PT_JIG_DET
+    39  1   114  #GPIO_EX_IO_I2C_SDA
+    38  1   113  #GPIO_EX_IO_I2C_SCL
+    0   1   128  #GPIO_PT_RELAY_EN
+    3   1   130  #GPIO_PT_ADC_CTRL1
+    2   1   131  #GPIO_PT_ADC_CTRL2
+    4   1   22   #GPIO_PT_PWR_CTRL
+    7   1   129  #GPIO_PT_RELAY_HPLC
+    50  1   127  #GPIO_MULTI_PULSE
+    51  1   76   #GPIO_MAC_SET
+    52  1   13   #GPIO_RST_CTRL
+    53  1   1    #GPIO_STA_OUT
+    54  1   0    #GPIO_PLC_EVENT
+    55  1   132  #GPIO_PT_GND_DET
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    #5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+#ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+#    0   1   0   #IOT_PLC_TX_LED
+#    ledout  1
+
+#    1   1   1   #IOT_PLC_RX_LED
+#    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   16   #ADC_PT_DUT_VCORE
+    1   1   17   #ADC_PT_DUT_3V
+    2   1   18   #ADC_PT_DUT_12V
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+#pa  # (PARTICULAR RESOURCE)
+#    rx_en_0 2   #Phase A Enable receiving
+#    tx_en_0 4   #Phase A Enable sending
+#    gain_0  7   #Phase A gain control
+#    gain_1  8   #Phase B gain control
+#    gain_2  26  #Phase C gain control
\ No newline at end of file
diff --git a/tools/oem/HTZD3211STA03_OEM.bin b/tools/oem/HTZD3211STA03_OEM.bin
new file mode 100755
index 0000000..08a3635
Binary files /dev/null and b/tools/oem/HTZD3211STA03_OEM.bin differ
diff --git a/tools/oem/HTZD3211STA03_OEM.ini b/tools/oem/HTZD3211STA03_OEM.ini
new file mode 100644
index 0000000..cb906e8
--- /dev/null
+++ b/tools/oem/HTZD3211STA03_OEM.ini
@@ -0,0 +1,531 @@
+# HZ3211 sta board, external rf chip, external pa chip.
+general
+    bid     44  #BOARD_HTZDSTA03
+    mid     0   #MODULE_TYPE_STA
+    vid     HT
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             32      set(sta)
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk          39      pa_lic_ctr
+#   34  rf_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    3   1   10  #GPIO_GEODE_OVT
+
+    32  1   17  #GPIO_GOLDEN_SET
+    5   1   24  #GPIO_GOLDEN_RXD0
+    6   1   34  #GPIO_GOLDEN_TXD0
+    29  1   1   #GPIO_STA_OUT
+    69  1   0   #GPIO_PLC_EVENT
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+    68  1   18  #GPIO_PA_ZC
+    39  1   120 #GPIO_LIC_CTRL
+
+    67  1   13  #GPIO_RST_CTRL
+    34  1   121 #GPIO_RF_CLK
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#================== 13.10.01.29(HW_VERSION_STA_3PS_DM_LOAD_V1) ================#
+# overview, external pa, external rf, load_send
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             32      set(sta)
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk          39      pa_lic_ctr
+#   30  load_send
+rc_hdr
+    hw_ver      0x0D0A011D  #13.10.1.29
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   load send gpio
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+#================== 13.15.1.9(HW_VERSION_STA_3PS_DM_FLASH_EXT_V1) ================#
+# overview
+# add: 38 37 36 35 flash spi
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             32      set(sta)
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk          39      pa_lic_ctr
+#   30  nc                  38      flash_spi_clk       37      flash_spi_mosi
+#   36  flash_spi_miso      35      flash_spi_cs
+rc_hdr
+    hw_ver      0x0D0F0109  #13.15.1.9
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+    36  1   71  #GPIO_SPI_FLASH_MISO
+    35  1   69  #GPIO_SPI_FLASH_CS
+
+#================== 13.10.2.12(HW_VERSION_STA_3PS_DM_V3) ================#
+# overview, for sumsung oversea
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             32      nc
+#   31  charge_en           29      nc                  28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  nc                  12      rf_spi_clk          39      pa_lic_ctr
+#   34  rf_clk              38      net_led
+
+rc_hdr
+    hw_ver      0x0D0A020C  #13.10.2.12
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    32  255 255  #GPIO_NO_VALID
+    29  255 255  #GPIO_NO_VALID
+    69  255 255  #GPIO_NO_VALID
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    2   1   8   #IOT_PLC_NET_LED
+    ledout  38
+
+#==================== 13.40.01.11(HW_VERSION_STA_LOAD_V3) ==================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  nc                  10      nc                  9       nc
+#   42  nc                  43      nc                  39      pa_lic_ctr
+#   38  nc                  37      nc                  36      nc
+#   35  nc                  34      nc                  33      nc
+#   32  set                 31      charge_en           30      load_send
+#   29  sta_out             28      uart2_tx            46      nc
+#   45  nc                  44      nc                  47      nc
+#   48  nc                  49      nc                  27      multi
+#   1   tx_led              0       rx_led              3       pa_testp
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      nc                  51      nc
+#   52  nc                  53      nc                  54      nc
+#   55  nc                  56      nc                  57      nc
+#   58  nc                  59      nc                  61      nc
+#   62  nc                  64      m_sta(adc_0)        65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a_up
+#   69  event               12      nc
+
+rc_hdr
+    hw_ver      0x0D28010B  #13.40.01.11
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  255 255 #GPIO_SPI_RF_CLK
+    11  255 255 #GPIO_SPI_RF_MOSI
+    10  255 255 #GPIO_SPI_RF_MISO
+    9   255 255 #GPIO_SPI_RF_CS
+
+    34  255 255 #GPIO_RF_CLK
+
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+    27  1   127 #GPIO_MULTI_PULSE
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+#=============================== 13.10.01.12(HW_VERSION_STA_CKQ_DM_V1) ==============#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             32      set(sta)
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk          39      pa_lic_ctr
+#   34  nc
+
+rc_hdr
+    hw_ver      0x0D0A010C  #13.10.01.12   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    34  255   255 #GPIO_SPI_RF_CLK
+
+#================== 13.15.1.13(HW_VERSION_STA_3PS_DM_LOAD_FLASH_EXT_V2) ================#
+# overview
+# add: load_send
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             32      set(sta)
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk          39      pa_lic_ctr
+#   30  load_send           38      flash_spi_clk       37      flash_spi_mosi
+#   36  flash_spi_miso      35      flash_spi_cs
+rc_hdr
+    hw_ver      0x0D0F010D  #13.15.1.13
+    mode        1
+    d_hw_ver    0x0D0F0109
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   load send gpio
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+#================== 13.10.2.13(HW_VERSION_STA_DM_V4) ================#
+# overview, for hx oversea
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  charge_en           37      nc                  36      nc
+#   35  nc                  34      rf_clk              33      nc
+#   32  nc                  31      nc                  30      nc
+#   29  nc                  28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              27      nc
+#   1   tx/rx led           0       net_led             3       testp
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  event               67      d_rst(soft reset)   68      zc_a
+#   69  adc_3.3v            12      rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0A020D  #13.10.2.13
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    31  255 255  #GPIO_NO_VALID
+    32  255 255  #GPIO_NO_VALID
+    29  255 255  #GPIO_NO_VALID
+    69  255 255  #GPIO_NO_VALID
+    66  1    0   #GPIO_PLC_EVENT
+    38  1    12  #GPIO_PM_CHARGE_EN
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    2   255   255
+    5   1     1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#================== 13.10.2.14(HW_VERSION_STA_3PS_DM_V4) ================#
+# overview, for hx oversea
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  charge_en           37      nc                  36      nc
+#   35  nc                  34      rf_clk              33      nc
+#   32  nc                  31      nc                  30      nc
+#   29  nc                  28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              27      nc
+#   1   tx/rx led           0       net_led             3       testp
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0A020E  #13.10.2.14
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    31  255 255  #GPIO_NO_VALID
+    32  255 255  #GPIO_NO_VALID
+    29  255 255  #GPIO_NO_VALID
+    38  1    12  #GPIO_PM_CHARGE_EN
+
+#================== 13.10.2.15(HW_VERSION_STA_DM_V5) ================#
+# overview, for hx oversea
+# gpio  function               gpio    function            gpio    function
+#   11  rf_spi_di              10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk                43      rf_fclk             39      pa_lic_ctr
+#   38  charge_en              37      csd                 36      nc
+#   35  nc                     34      rf_clk              33      nc
+#   32  nc                     31      nc                  30      nc
+#   29  nc                     28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable              44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1                 49      rf_dq2              27      nc
+#   1   tx/rx led              0       net_led             3       testp
+#   2   pa_rx_en               4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx               5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2       50      rf_dq3              51      rf_dq4
+#   52  rf_dq5                 53      rf_dq6              54      rf_dq7
+#   55  rf_dq8                 56      rf_dq9              57      rf_dq10
+#   58  rf_dq11                59      rf_pd               61      rf_channel_sw_cps(io)
+#   62  rf_channel_sw_ctx(io)  64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v               67      d_rst(soft reset)   68      zc_a
+#   69  event                  12      rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0A020F  #13.10.2.15
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    31  255 255  #GPIO_NO_VALID
+    32  255 255  #GPIO_NO_VALID
+    29  255 255  #GPIO_NO_VALID
+    38  1   12   #GPIO_PM_CHARGE_EN
+    37  1   133  #GPIO_RF_PA_CSD
+    62  1   134  #GPIO_RF_PA_CTX
+
+#================== 13.10.01.13(HW_VERSION_STA_SPG_DM_FLASH_EXT_V1) ================#
+# overview
+# add: 27 multi, 38 37 36 35 flash spi
+# gpio  function                gpio    function            gpio    function
+#   11  rf_spi_di               10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk                 43      rf_fclk             39      pa_lic_ctr
+#   38  flash_spi_clk           37      flash_spi_mosi      36      flash_spi_miso
+#   35  flash_spi_cs            34      rf_clk              33      nc
+#   32  set(sta)                31      charge_en           30      nc
+#   29  sta_out                 28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable               44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1                  49      rf_dq2              27      multi
+#   1   tx_led                  0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en                4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx                5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2        50      rf_dq3              51      rf_dq4
+#   52  rf_dq5                  53      rf_dq6              54      rf_dq7
+#   55  rf_dq8                  56      rf_dq9              57      rf_dq10
+#   58  rf_dq11                 59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)       64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v                67      d_rst(soft reset)   68      zc_a
+#   69  event                   12      rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0A010D  #13.10.01.13
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+    36  1   71  #GPIO_SPI_FLASH_MISO
+    35  1   69  #GPIO_SPI_FLASH_CS
+
+    27  1   127 #GPIO_MULTI_PULSE
\ No newline at end of file
diff --git a/tools/oem/HTZD3PS01_OEM.ini b/tools/oem/HTZD3PS01_OEM.ini
new file mode 100755
index 0000000..983c3d4
--- /dev/null
+++ b/tools/oem/HTZD3PS01_OEM.ini
@@ -0,0 +1,31 @@
+general
+ bid 5
+ mid 4
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+#uart1
+# tx 34
+# rx 35
+# cli
+
+uart2
+ tx 8
+ rx 9
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 32
+ rx 33
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 47
+ phase_b 34
+ phase_c 35
diff --git a/tools/oem/HTZDCCO01_OEM.bin b/tools/oem/HTZDCCO01_OEM.bin
new file mode 100644
index 0000000..8617062
Binary files /dev/null and b/tools/oem/HTZDCCO01_OEM.bin differ
diff --git a/tools/oem/HTZDCCO01_OEM.ini b/tools/oem/HTZDCCO01_OEM.ini
new file mode 100755
index 0000000..3e5280e
--- /dev/null
+++ b/tools/oem/HTZDCCO01_OEM.ini
@@ -0,0 +1,44 @@
+general
+ bid 4
+ mid 1
+ vid HT
+
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ log
+
+uart2
+ tx 0
+ rx 1
+ cli
+
+led
+ tx 32
+ rx 33
+ phase_a 34
+ phase_b 35
+ phase_c 36
+ 
+tx_e
+ phase_a 26
+ phase_b 24
+ phase_c 22
+
+rx_e
+ phase_a 27
+ phase_b 25
+ phase_c 23
+ 
+glna
+ phase_a 28
+ phase_b 20
+ phase_c 21
+
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/HTZDIIC01_OEM.ini b/tools/oem/HTZDIIC01_OEM.ini
new file mode 100755
index 0000000..1cdb1f7
--- /dev/null
+++ b/tools/oem/HTZDIIC01_OEM.ini
@@ -0,0 +1,32 @@
+general
+ bid 6
+ mid 2
+ vid HT
+
+uart0
+ tx 30
+ rx 31
+ log
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ rx 9
+ rs485
+
+uart3
+ tx 22
+ rx 23
+ ir
+
+led
+ tx 36
+ rx 32
+ rs485 33
+
+zc
+ phase_a 47
diff --git a/tools/oem/HTZDSTA01_OEM.ini b/tools/oem/HTZDSTA01_OEM.ini
new file mode 100755
index 0000000..d1033a3
--- /dev/null
+++ b/tools/oem/HTZDSTA01_OEM.ini
@@ -0,0 +1,29 @@
+general
+ bid 5
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ rx 9
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 32
+ rx 33
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 47
diff --git a/tools/oem/HTZDSTA02_OEM.ini b/tools/oem/HTZDSTA02_OEM.ini
new file mode 100755
index 0000000..abac9d0
--- /dev/null
+++ b/tools/oem/HTZDSTA02_OEM.ini
@@ -0,0 +1,25 @@
+general
+ bid 19
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ meter
+
+uart1
+ tx 41
+ rx 40
+ cli
+
+uart2
+ tx 39
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 43
+ rx 42
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 38
diff --git a/tools/oem/IOTIICCCO01_OEM.ini b/tools/oem/IOTIICCCO01_OEM.ini
new file mode 100644
index 0000000..02dcecf
--- /dev/null
+++ b/tools/oem/IOTIICCCO01_OEM.ini
@@ -0,0 +1,32 @@
+general
+ bid 29
+ mid 1
+ vid HT
+
+uart0
+ tx 30
+ rx 31
+ log
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ rx 9
+ rs485
+
+uart3
+ tx 22
+ rx 23
+ ir
+
+led
+ tx 36
+ rx 32
+ rs485 33
+
+zc
+ phase_a 47
diff --git a/tools/oem/IOTIICSTA01_OEM.ini b/tools/oem/IOTIICSTA01_OEM.ini
new file mode 100644
index 0000000..1cdb1f7
--- /dev/null
+++ b/tools/oem/IOTIICSTA01_OEM.ini
@@ -0,0 +1,32 @@
+general
+ bid 6
+ mid 2
+ vid HT
+
+uart0
+ tx 30
+ rx 31
+ log
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ rx 9
+ rs485
+
+uart3
+ tx 22
+ rx 23
+ ir
+
+led
+ tx 36
+ rx 32
+ rs485 33
+
+zc
+ phase_a 47
diff --git a/tools/oem/JSMT3PS01_OEM.ini b/tools/oem/JSMT3PS01_OEM.ini
new file mode 100755
index 0000000..dbf53c0
--- /dev/null
+++ b/tools/oem/JSMT3PS01_OEM.ini
@@ -0,0 +1,42 @@
+general
+ bid 8
+ mid 4
+ vid MT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 0
+ rx 1
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 32
+ rx 33
+
+tx_e
+ phase_a 26
+
+rx_e
+ phase_a 27
+
+glna
+ phase_a 28
+ phase_b 20
+ phase_c 21
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/JSMTCCO01_OEM.ini b/tools/oem/JSMTCCO01_OEM.ini
new file mode 100644
index 0000000..781bd08
--- /dev/null
+++ b/tools/oem/JSMTCCO01_OEM.ini
@@ -0,0 +1,49 @@
+general
+ bid 7
+ vid MT
+ mid 1
+
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ log
+
+uart2
+ tx 0
+ rx 1
+ cli
+
+uart3
+ tx 9
+ rx 10
+ rs485
+
+led
+ tx 32
+ rx 33
+ phase_a 34
+ phase_b 35
+ phase_c 36
+
+tx_e
+ phase_a 26
+ phase_b 24
+ phase_c 22
+
+rx_e
+ phase_a 27
+ phase_b 25
+ phase_c 23
+
+glna
+ phase_a 28
+ phase_b 20
+ phase_c 21
+
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/JSMTIIC01_OEM.ini b/tools/oem/JSMTIIC01_OEM.ini
new file mode 100755
index 0000000..ce4ec69
--- /dev/null
+++ b/tools/oem/JSMTIIC01_OEM.ini
@@ -0,0 +1,44 @@
+general
+ bid 9
+ vid MT
+ mid 2
+
+uart0
+ tx 30
+ rx 31
+ log
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 0
+ rx 1
+ rs485 
+
+uart3
+ tx 2
+ rx 3
+ ir
+
+led
+ tx 33
+ rx 36
+ rs485 32
+
+tx_e
+ phase_a 26
+
+rx_e
+ phase_a 27
+
+glna
+ phase_a 28
+ phase_b 20
+ phase_c 21
+
+zc
+ phase_a 47
+ phase_b 48
diff --git a/tools/oem/JSMTSTA01_OEM.ini b/tools/oem/JSMTSTA01_OEM.ini
new file mode 100755
index 0000000..2f943e0
--- /dev/null
+++ b/tools/oem/JSMTSTA01_OEM.ini
@@ -0,0 +1,40 @@
+general
+ bid 8
+ vid MT
+ mid 0
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 0
+ rx 1
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 32
+ rx 33
+
+tx_e
+ phase_a 26
+
+rx_e
+ phase_a 27
+
+glna
+ phase_a 28
+ phase_b 20
+ phase_c 21
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 47
diff --git a/tools/oem/KL2AI01_OEM.ini b/tools/oem/KL2AI01_OEM.ini
new file mode 100755
index 0000000..4feabf4
--- /dev/null
+++ b/tools/oem/KL2AI01_OEM.ini
@@ -0,0 +1,3 @@
+general
+ bid 16
+ mid 0
diff --git a/tools/oem/KL2CCO01_OEM.ini b/tools/oem/KL2CCO01_OEM.ini
new file mode 100755
index 0000000..a566547
--- /dev/null
+++ b/tools/oem/KL2CCO01_OEM.ini
@@ -0,0 +1,11 @@
+general
+ bid 13
+ mid 1
+
+uart1
+ tx 43
+ rx 44
+
+uart2
+ tx 39
+ rx 40
diff --git a/tools/oem/KL3_EXAMPLE_OEM.ini b/tools/oem/KL3_EXAMPLE_OEM.ini
new file mode 100644
index 0000000..fd0d3c9
--- /dev/null
+++ b/tools/oem/KL3_EXAMPLE_OEM.ini
@@ -0,0 +1,156 @@
+general
+    bid     44
+    mid     0
+    vid     HT
+    fver    1   #oem结构体版本号，1对应V1版本结构体
+
+#本文件仅为了测试kl3 oem功能以及说明ini文件编写规则存在
+#各行后面的#表示对该行的说明信息，实际编写ini文件时请忽略
+#如果存在信号绑定，则需要在外设下方指定信号类型和gpio编号
+
+#================== default rc===================#
+rc_hdr #不同版本之间header信息
+    hw_ver      0x00000000  #硬件识别码，用于匹配资源分配表，十六进制
+    mode        0           #是否为差分模式，1表示差分
+    d_hw_ver    0xffffffff  #用于比较的资源表对应的硬件识别码，十六进制
+
+#通用资源，需要应用层通过api获取资源分配，并初始化获取的资源
+gpio    #gpio资源分配
+    0   0   0   #gpio编号，所属core，用途（见iot_board_api.h中GPIO_XXX）
+    1   1   1
+
+uart    #uart资源分配
+    0   1   1   #uart编号    所属core 用途（见iot_uart_api.h中UART_XXX）
+    tx  2       #uart tx信号对应的gpio编号
+    rx  3       #uart rx信号对应的gpio编号
+
+    1   1   0
+    tx  4
+
+    2   0   11
+    tx  5
+
+    3   1   2
+    tx  6
+    rx  7
+
+    4   2   13
+    tx  8
+
+pwm        #pwm资源分配
+    1   2   3   #pwm编号，所属core，用途（见iot_pwm_api.h中的IOT_PWM_CHANNEL_XXX）
+    pwma    9   #pwm默认互补输出，pwma指常规通道输出
+    pwmb    10  #pwm互补通道输出
+
+adc        #adc资源分配
+    1   2   3   #adc通道编号，所属core，用途（见iot_board_api.h中ADC_XXX）
+
+ledc    #ledc资源分配
+    1   2   3   #ledc通道，所属core，用途
+    ledout  11  #ledc的输出信号(ledc仅一个信号，因此统一为ledout)，gpio编号
+
+spi        #spi资源分配
+    1   2   3   #spi编号，所属core，用途
+    cs      12  #spi cs信号，cs信号对应的gpio
+    clk     13  #spi clk信号，clk信号对应的gpio
+    miso    14  #spi miso信号，miso信号对应的gpio
+    mosi    15  #spi mosi信号，mosi信号对应的gpio
+
+i2c        #i2c资源分配
+    1   2   3   #i2c编号，所属core，用途
+    scl 16      #i2c scl信号，scl信号对应的gpio
+    sda 17      #i2c sda信号，sda信号对应的gpio
+
+#internal resource
+spinlock
+dma
+gptimer
+mailbox
+wdg
+
+#特定资源，无需应用层通过api获取资源分配，初始化模块即可使用，需要底层绑定信号
+#由于oem_tool限制，特定资源需要放到通用资源后面
+zc  #芯片级过零检测资源分配
+    up_0    20  #过零检测上升沿输入通道0，默认对应phase a上升沿过零电路
+    up_1    21  #过零检测上升沿输入通道1，默认对应phase b上升沿过零电路
+    up_2    22  #过零检测上升沿输入通道2，默认对应phase c上升沿过零电路
+    down_0  23  #过零检测下降沿输入通道0，默认对应phase a下降沿过零电路
+    down_1  24  #过零检测下降沿输入通道1，默认对应phase b下降沿过零电路
+    down_2  25  #过零检测下降沿输入通道2，默认对应phase c下降沿过零电路
+
+pa
+    tx_en_0 26  #phase a发送使能
+    rx_en_0 27  #phase a接收使能
+    tx_en_1 28  #phase b发送使能
+    rx_en_1 29  #phase b接收使能
+    tx_en_2 30  #phase c发送使能
+    rx_en_2 31  #phase c接收使能
+    gain_0  32  #phase a增益控制
+    gain_1  33  #phase b增益控制
+    gain_2  34  #phase c增益控制
+
+#由于oem中最多只能存放62个gpio的资源分配，rf绑定信号需要占用16个，因此将rf的信号
+#放在代码中固定，详见board_special_signal_mtx_binding函数。
+#rf
+#    mclk    35
+#    fclk    36
+#    gain    37
+#    enable  38
+#    txnrx   39
+#    pd      40
+#    dq0     41
+#    dq1     42
+#    dq2     43
+#    dq3     44
+#    dq4     45
+#    dq5     46
+#    dq6     47
+#    dq7     48
+#    dq8     49
+#    dq9     50
+#    dq10    51
+#    dq11    52
+
+#================== hw version 1 ===================#
+#差分方式定义，header信息必备，其他仅描述不同处即可，但是必须带上资源编号
+rc_hdr
+    hw_ver      0x00000001
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+    0   1   2
+    1   255 255
+
+uart
+    0   1   1
+    tx  6
+    rx  7
+
+    3   1   2
+    tx  2
+    rx  3
+
+#================== hw version 2 ===================#
+#差分方式定义，header信息必备，其他仅描述不同处即可，但是必须带上资源编号
+rc_hdr
+    hw_ver      0x00000002
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio
+    0   255 255
+    1   2   3
+
+#================== hw version 3 ===================#
+#差分方式定义，header信息必备，其他仅描述不同处即可，但是必须带上资源编号
+rc_hdr
+    hw_ver      0x00000003
+    mode        1
+    d_hw_ver    0x00000002
+
+gpio
+    0   1   2
+    1   2   3
+
+
diff --git a/tools/oem/LEDC03_OEM.ini b/tools/oem/LEDC03_OEM.ini
new file mode 100644
index 0000000..eb70135
--- /dev/null
+++ b/tools/oem/LEDC03_OEM.ini
@@ -0,0 +1,64 @@
+# kl3 ledc2.0 board
+
+general
+    bid     54  #BOARD_LEDCSTA03
+    mid     0   #sta
+    vid     HT
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# module_pin    pin_num     pin_name    func_default            func_2
+#   5           9           adc3\gpio67 adc3                    \
+#   6           10          adc4\gpio68 adc4                    \
+#   8           11          adc5\gpio69 adc5                    \
+#   9           32          tdi\gpio02  uart1_rx                \
+#   10          31          tdo\gpio03  uart1_tx                \
+#   11          26          gpio26      pwm1                    \
+#   12          39          gpio08      pwm2                    \
+#   14          33          trst\gpio04 pwm3                    \
+#   15          34          gpio07      pwm4                    \
+#   16          23          gpio31      pwm5                    gpio
+#   18          37      uart0_tx\gpio06 uart0_tx                \
+#   19          38      uart0_rx\gpio05 uart0_rx                \
+
+rc_hdr
+    hw_ver      0x00000000  #0x690A0100     #105.10.01.00, Q111N_ISG
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio
+    4   1   95  #GPIO_CUS_IO_0
+    7   1   97  #GPIO_CUS_IO_3
+    31  1   101 #GPIO_CUS_IO_15
+
+adc
+    5   1   14  #ADC_CUS_ADC_5
+
+uart
+    0   1   11  #UART_CUS_PORT_0
+    tx  6
+    rx  5
+
+    1   1   1   #UART_CLI_PORT
+    tx  3
+    rx  2
+
+    2   1   0   #UART_PRINT
+    tx  33
+    rx  32
+
+ledc
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+# internal sealing one pa chips
+pa
+    rx_en_0 80  #enlic_pad_0
+    tx_en_0 81  #enlic_pad_1
+    gain_0  82  #glna_pad_0
+    gain_1  83  #glna_pad_1
+    gain_2  84  #glna_pad_2
\ No newline at end of file
diff --git a/tools/oem/LEDCCCO01_OEM.ini b/tools/oem/LEDCCCO01_OEM.ini
new file mode 100644
index 0000000..13b7f8b
--- /dev/null
+++ b/tools/oem/LEDCCCO01_OEM.ini
@@ -0,0 +1,25 @@
+general
+ bid 25
+ mid 1
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ rx 9
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 32
+ rx 33
diff --git a/tools/oem/LEDCSTA01_OEM.ini b/tools/oem/LEDCSTA01_OEM.ini
new file mode 100644
index 0000000..1914d0e
--- /dev/null
+++ b/tools/oem/LEDCSTA01_OEM.ini
@@ -0,0 +1,25 @@
+general
+ bid 17
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ rx 9
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 32
+ rx 33
diff --git a/tools/oem/LEDCSTA03_OEM.ini b/tools/oem/LEDCSTA03_OEM.ini
new file mode 100644
index 0000000..8c58370
--- /dev/null
+++ b/tools/oem/LEDCSTA03_OEM.ini
@@ -0,0 +1,42 @@
+# see KL3_EXAMPLE_OEM.ini for file format description
+general
+    bid     54  #BOARD_LEDCSTA03
+    mid     0   #sta\cco
+    vid     HT
+    fver    1
+#=============== 106.10.1.30(HW_VERSION_IOT_LEDC_V2_0_P_KL3) ===============#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   05  uart0_rx              06    uart0_tx              04    staout
+#   07  set                   69    zc_in                 31    event
+#   27  tx_led                01    rx_led                03    uart1_tx
+#   02  uart1_rx              33    uart2_tx              32    uart2_rx
+
+rc_hdr
+    hw_ver      0x6A0A011E  #106.10.1.30
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+    04  1   1   #GPIO_STA_OUT
+
+uart    #UART resource allocation
+    # current serial port is not multiplexed, uart0(6\5) as download port reserved
+    0   1   0   #UART_PRINT
+    tx  6
+    rx  5
+
+    1   1   11  #UART_CUS_PORT_0
+    tx  3
+    rx  2
+
+    2   1   1   #UART_CLI_PORT
+    tx  33
+    rx  32
+
+ledc
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  27
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  1
+
diff --git a/tools/oem/LEDC_3P0CCO01_OEM.ini b/tools/oem/LEDC_3P0CCO01_OEM.ini
new file mode 100644
index 0000000..04351ce
--- /dev/null
+++ b/tools/oem/LEDC_3P0CCO01_OEM.ini
@@ -0,0 +1,24 @@
+general
+ bid 47
+ mid 1
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ log
+
+# led's option: tx
+led
+ tx 32
+ rs485 33
diff --git a/tools/oem/LEDC_3P0CCO03_OEM.ini b/tools/oem/LEDC_3P0CCO03_OEM.ini
new file mode 100644
index 0000000..5c59c71
--- /dev/null
+++ b/tools/oem/LEDC_3P0CCO03_OEM.ini
@@ -0,0 +1,47 @@
+# see KL3_EXAMPLE_OEM.ini for file format description
+general
+    bid     59  #BOARD_LEDC3P003
+    mid     1   #cco
+    vid     HT
+    fver    1
+
+#============ 108.10.1.30(HW_VERSION_IOT_LEDC_V3_0_JY_KL3), ziyan ============#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   66  adc1                67      adc0                69      adc4
+#   33  uart2_tx            32      monitor             31      signal_led
+#   1   plc_led             0       485_led             3       485_tx
+#   2   485_rx              4       485_ctr             7       wdi
+#   6   uart0_tx            5       uart0_rx            8       en_outv12
+#   26  en_outv3p3
+
+rc_hdr
+    hw_ver      0x6C0A011E  #108.10.1.30
+    mode        0
+    d_hw_ver    0xffffffff
+
+uart
+    0   1   0   #UART_PRINT
+    tx  6
+    rx  5
+
+    2   1   11  #UART_CUS_PORT_0
+    tx  33
+
+    1   1   4   #UART_RS485_PORT
+    tx  3
+    rx  2
+
+ledc
+    0   1   7   #IOT_PLC_TR_LED
+    ledout  1
+
+    1   1   6   #IOT_RS485_LED
+    ledout  0
+
+adc
+    0   1   1   #ADC_PM_3V
+    #1   1   #
+    4   1   0   #ADC_PM_12V
+
+
diff --git a/tools/oem/LEDC_3P0STA01_OEM.ini b/tools/oem/LEDC_3P0STA01_OEM.ini
new file mode 100644
index 0000000..ecbbf17
--- /dev/null
+++ b/tools/oem/LEDC_3P0STA01_OEM.ini
@@ -0,0 +1,24 @@
+general
+ bid 47
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 34
+ rx 35
+ rs485
+
+uart2
+ tx 8
+ log
+
+# led's option: tx
+led
+ tx 32
+ rs485 33
diff --git a/tools/oem/MPPT_OEM.ini b/tools/oem/MPPT_OEM.ini
new file mode 100644
index 0000000..50a8df6
--- /dev/null
+++ b/tools/oem/MPPT_OEM.ini
@@ -0,0 +1,24 @@
+general
+ bid 96
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ log
+
+uart1
+ tx 41
+ rx 40
+ ext
+
+uart2
+ tx 8
+ rx 9
+ cli
+
+# led's option: tx
+led
+ tx 32
diff --git a/tools/oem/QJ5580DCCO03_OEM.bin b/tools/oem/QJ5580DCCO03_OEM.bin
new file mode 100755
index 0000000..62ca1d9
Binary files /dev/null and b/tools/oem/QJ5580DCCO03_OEM.bin differ
diff --git a/tools/oem/QJ5580DCCO03_OEM.ini b/tools/oem/QJ5580DCCO03_OEM.ini
new file mode 100644
index 0000000..4400ec9
--- /dev/null
+++ b/tools/oem/QJ5580DCCO03_OEM.ini
@@ -0,0 +1,263 @@
+# QJ5580D cco board
+general
+    bid     63  #BOARD_QJCCO03
+    mid     1   #MODULE_TYPE_CCO
+    vid     QJ
+    fver    1
+
+#================================= default rc =================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      zc_c_up
+#   38  zc_c_down           37      zc_b_up             36      zc_b_down
+#   35  zc_a_up             34      pa_led\uart1_tx     33      pb_led\uart1_rx
+#   32  pc_led              30      pa_c_tx_en          29      pa_c_rx_en
+#   28  uart2_tx            31      charge_en           46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            12      rf_spi_clk
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      uart2_rx(cli)
+#   62  rf_channel_sw(io)   64      m_sta(adc_0)        65      adc_12v
+#   66  adc_3.3v            67      pa_b_tx_en          68      zc_a_down
+#   69  pa_b_rx_en
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    3   1   10  #GPIO_GEODE_OVT
+
+    32  1   6   #GPIO_PC_LED
+    0   1   3   #GPIO_RX_LED
+    1   1   2   #GPIO_TX_LED
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+
+    35  1   18  #GPIO_PA_ZC
+    37  1   19  #GPIO_PB_ZC
+    39  1   20  #GPIO_PC_ZC
+    68  1   44  #GPIO_PA_ZC_EXT
+    36  1   45  #GPIO_PB_ZC_EXT
+    38  1   46  #GPIO_PC_ZC_EXT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   1   #UART_CLI_PORT
+    tx  28
+    rx  61
+
+    1   1   0   #UART_PRINT
+    tx  34
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   2   #IOT_PLC_PHASE_A_LED
+    ledout  34
+
+    1   1   3   #IOT_PLC_PHASE_B_LED
+    ledout  33
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  32
+
+    3   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    4   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND
+    1   1   0   #ADC_PM_12V
+    2   1   1   #ADC_PM_3V
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+#   up_0    35
+#   up_1    37
+#   up_2    39
+#   down_0  68
+#   down_1  36
+#   down_2  38
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    tx_en_1 67  #Phase B Enable sending
+    rx_en_1 69  #Phase B Enable receiving
+    tx_en_2 30  #Phase C Enable sending
+    rx_en_2 29  #Phase C Enable receiving
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3201覆膜为QJ5580D
+#   chip id: 0x1003     subid: 0x1013
+
+#=================== 13.10.08.01(HW_VERSION_QJ_MASKCHIP_V1) ===================#
+# QJ CCO 覆膜HZ3201芯片 资源与QJ5580D的一样
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      zc_c_up
+#   38  zc_c_down           37      zc_b_up             36      zc_b_down
+#   35  zc_a_up             34      pa_led\uart1_tx     33      pb_led\uart1_rx
+#   32  pc_led              30      pa_c_tx_en          29      pa_c_rx_en
+#   28  uart2_tx            31      charge_en           46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            12      rf_spi_clk
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      uart2_rx(cli)
+#   62  rf_channel_sw(io)   64      m_sta(adc_0)        65      adc_12v
+#   66  adc_3.3v            67      pa_b_tx_en          68      zc_a_down
+#   69  pa_b_rx_en
+
+rc_hdr
+    hw_ver      0x0D0A0801  #13.10.08.01 Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+#================= 31.20.02.00(HW_VERSION_CCO_USB_V2) =========================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      zc_c_2
+#   38  zc_c_1              37      zc_b_2              36      zc_b_1
+#   35  zc_a_2              34      uart1_tx(log)       33      run_led
+#   32  uart3_tx            31      uart3_rx            30      pa_c_tx_en
+#   29  pa_c_rx_en          28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp(warning)   2       pa_a_rx_en
+#   4   pa_a_tx_en          7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      uart2_rx            62      rf_channel_sw2(io)
+#   64  adc_cal             65      adc_12v             66      boot0(gd32)
+#   67  pa_b_tx_en          68      zc_a_1              69      pa_b_rx_en
+#   12  rf_spi_clk          27      rst(gd32)
+
+rc_hdr
+    hw_ver      0x1F140200  #31.20.02.00   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function(to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    32   255   255
+    31   255   255
+    34   255   255
+    66   1   74 #GPIO_VC_EXT_CHIP_BOOT
+    27   1   75 #GPIO_VC_EXT_CHIP_RST
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    3   1   5   #UART_EXT_CHIP
+    tx  32
+    rx  31
+
+# disable uart0 meter port function
+    0   255   255
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+    2   1   5   #IOT_PWR_LED
+    ledout  33
+
+    3   255   255   #IOT_LED_TYPE_INVALID
+    4   255   255   #IOT_LED_TYPE_INVALID
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    2   255   255   #ADC_TYPE_INVALID
diff --git a/tools/oem/QJ5580DCKB03_OEM.ini b/tools/oem/QJ5580DCKB03_OEM.ini
new file mode 100644
index 0000000..299adc6
--- /dev/null
+++ b/tools/oem/QJ5580DCKB03_OEM.ini
@@ -0,0 +1,115 @@
+# QJ5580D ckb board, external rf chip, external pa chip.
+general
+    bid     88  #BOARD_QJCKB03
+    mid     0   #MODULE_TYPE_STA
+    vid     QJ
+    fver    1
+
+#=============================== default rc====================================#
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  nc                  37      nc                  36      nc
+#   35  nc                  34      rf_clk              32      set
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      m_sta(adc0)         65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(adc3)         68      zc_a_up(adc4)
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    39  1   120 #GPIO_LIC_CTRL
+    34  1   121 #GPIO_RF_CLK
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   12  #GPIO_PM_CHARGE_EN
+    29  1   1   #GPIO_STA_OUT
+    3   1   10  #GPIO_GEODE_OVT
+    67  1   13  #GPIO_RST_CTRL
+    68  1   18  #GPIO_PA_ZC
+    69  1   0   #GPIO_PLC_EVENT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
diff --git a/tools/oem/QJ5582D3PS03_OEM.bin b/tools/oem/QJ5582D3PS03_OEM.bin
new file mode 100755
index 0000000..293acd9
Binary files /dev/null and b/tools/oem/QJ5582D3PS03_OEM.bin differ
diff --git a/tools/oem/QJ5582D3PS03_OEM.ini b/tools/oem/QJ5582D3PS03_OEM.ini
new file mode 100644
index 0000000..0afc7c9
--- /dev/null
+++ b/tools/oem/QJ5582D3PS03_OEM.ini
@@ -0,0 +1,277 @@
+# QJ5582D 3ps board
+general
+    bid     62  #BOARD_QJ3PS03
+    mid     4   #MODULE_TYPE_3_PHASE_STA
+    vid     QJ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_crt
+#   36  zc_b_up             35      zc_c_up             34      rf_clk
+#   32  set                 31      charge_en           29      sta_out
+#   28  uart2_tx            46      rf_agc_gain         45      rf_enable
+#   44  rf_txnrx            47      rf_dq0              48      rf_dq1
+#   49  rf_dq2              1       tx_led              0       rx_led
+#   3   pa_testp            2       pa_rx_en            4       pa_tx_en
+#   7   pa_lan_gain_ctr0    6       uart0_tx            5       uart0_rx
+#   8   pa_lan_gain_ctr1    26      pa_lan_gain_ctr2    50      rf_dq3
+#   51  rf_dq4              52      rf_dq5              53      rf_dq6
+#   54  rf_dq7              55      rf_dq8              56      rf_dq9
+#   57  rf_dq10             58      rf_dq11             59      rf_pd
+#   61  rf_channel_sw(io)   62      rf_channel_sw(io)   64      m_sta(adc_0)
+#   65  adc_12v             66      adc_3.3v            67      d_rst(soft reset)
+#   68  zc_a_up             69      event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    3   1   10  #GPIO_GEODE_OVT
+    32  1   17  #GPIO_GOLDEN_SET
+
+    29  1   1   #GPIO_STA_OUT
+
+    69  1   0   #GPIO_PLC_EVENT
+    39  1   120 #GPIO_LIC_CTRL
+
+    0   1   3   #GPIO_RX_LED
+    1   1   2   #GPIO_TX_LED
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+
+    68  1   18  #GPIO_PA_ZC
+    36  1   19  #GPIO_PB_ZC
+    35  1   20  #GPIO_PC_ZC
+
+    67  1   13  #GPIO_RST_CTRL
+    34  1   121 #GPIO_RF_CLK
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND
+    1   1   0   #ADC_PM_12V
+    2   1   1   #ADC_PM_3V
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+#   up_1    36
+#   up_2    35
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3211覆膜为QJ5582D
+#   chip id: 0x1001     subid: 0x1011
+
+#==================== 13.10.08.01(HW_VERSION_QJ_MASKCHIP_V1) ==================#
+# QJ 3PS 覆膜HZ3211芯片 资源与QJ5582D的一样
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_crt
+#   36  zc_b_up             35      zc_c_up             34      rf_clk
+#   32  set                 31      charge_en           29      sta_out
+#   28  uart2_tx            46      rf_agc_gain         45      rf_enable
+#   44  rf_txnrx            47      rf_dq0              48      rf_dq1
+#   49  rf_dq2              1       tx_led              0       rx_led
+#   3   pa_testp            2       pa_rx_en            4       pa_tx_en
+#   7   pa_lan_gain_ctr0    6       uart0_tx            5       uart0_rx
+#   8   pa_lan_gain_ctr1    26      pa_lan_gain_ctr2    50      rf_dq3
+#   51  rf_dq4              52      rf_dq5              53      rf_dq6
+#   54  rf_dq7              55      rf_dq8              56      rf_dq9
+#   57  rf_dq10             58      rf_dq11             59      rf_pd
+#   61  rf_channel_sw(io)   62      rf_channel_sw(io)   64      m_sta(adc_0)
+#   65  adc_12v             66      adc_3.3v            67      d_rst(soft reset)
+#   68  zc_a_up             69      event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A0801  #13.10.08.01   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+#================= 13.10.01.29(HW_VERSION_STA_3PS_DM_LOAD_V1) =================#
+# QJ 3PS 带小负载 覆膜HZ3211芯片
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_crt
+#   36  zc_b_up             35      zc_c_up             34      rf_clk
+#   32  set                 31      charge_en           29      sta_out
+#   28  uart2_tx            46      rf_agc_gain         45      rf_enable
+#   44  rf_txnrx            47      rf_dq0              48      rf_dq1
+#   49  rf_dq2              1       tx_led              0       rx_led
+#   3   pa_testp            2       pa_rx_en            4       pa_tx_en
+#   7   pa_lan_gain_ctr0    6       uart0_tx            5       uart0_rx
+#   8   pa_lan_gain_ctr1    26      pa_lan_gain_ctr2    50      rf_dq3
+#   51  rf_dq4              52      rf_dq5              53      rf_dq6
+#   54  rf_dq7              55      rf_dq8              56      rf_dq9
+#   57  rf_dq10             58      rf_dq11             59      rf_pd
+#   61  rf_channel_sw(io)   62      rf_channel_sw(io)   64      m_sta(adc_0)
+#   65  adc_12v             66      adc_3.3v            67      d_rst(soft reset)
+#   68  zc_a_up             69      event               12      rf_spi_clk
+#   30  load_send
+rc_hdr
+    hw_ver      0x0D0A011D  #13.10.01.29
+    mode        1
+    d_hw_ver    0x0D0A0801
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   load send gpio
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+#==================== 13.10.02.21(HW_VERSION_STA_QJ_3PS_DM_V1) ==================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      mo_clk_flash
+#   38  mo_si_flash         37      mi_so_flash         36      zc_b_up
+#   35  zc_c_up             34      rf_clk              33      mo_cs_flash
+#   32  set                 31      charge_en           30      nc
+#   29  sta_out             28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp            2       pa_rx_en
+#   4   pa_tx_en            7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      pa_lic_crt          62      rf_channel_sw(io)
+#   64  m_sta(adc_0)        65      adc_12v             66      adc_3.3v
+#   67  d_rst(soft reset)   68      zc_a_up             69      event
+#   12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A0215  #13.10.02.21   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    39  1   68  #GPIO_SPI_FLASH_CLK
+    38  1   70  #GPIO_SPI_FLASH_MOSI
+    37  1   71  #GPIO_SPI_FLASH_MISO
+    33  1   69  #GPIO_SPI_FLASH_CS
+
+    61  1   120 #GPIO_LIC_CTRL
+
+#================== 13.10.02.22(HW_VERSION_QJ_3PS_SPG_DM_V1) ================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_crt
+#   38  nc                  37      nc                  36      zc_b_up
+#   35  zc_c_up             34      rf_clk              33      nc
+#   32  set                 31      charge_en           30      nc
+#   29  sta_out             28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              27      multi
+#   1   tx_led              0       rx_led              3       pa_testp
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_0)        65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a_up
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A0216  #13.10.02.22
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    27  1   127 #GPIO_MULTI_PULSE
diff --git a/tools/oem/QJ5582DIIC03_OEM.bin b/tools/oem/QJ5582DIIC03_OEM.bin
new file mode 100755
index 0000000..eb48399
Binary files /dev/null and b/tools/oem/QJ5582DIIC03_OEM.bin differ
diff --git a/tools/oem/QJ5582DIIC03_OEM.ini b/tools/oem/QJ5582DIIC03_OEM.ini
new file mode 100644
index 0000000..8445f87
--- /dev/null
+++ b/tools/oem/QJ5582DIIC03_OEM.ini
@@ -0,0 +1,203 @@
+# see KL3_EXAMPLE_OEM.ini for file format description
+# QJ5582D iic board, external rf chip, external pa chip.
+general
+    bid     72  #BOARD_QJIIC03
+    mid     2   #MODULE_TYPE_COLLECTOR_II
+    vid     QJ
+    fver    1
+
+#=============================== default rc====================================#
+# QJ IIC 真实芯片无资源分配
+
+#===================================覆膜资源===================================#
+# HZ3211覆膜为QJ5582D
+#   chip id: 0x1001     subid: 0x1011
+
+#=============================== default rc====================================#
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      ext_flash_cs
+#   38  ext_flash_clk       36      ext_flash_miso      37      ext_flash_mosi
+#   34  ir_rx               32      485_ctr             31      charge_en
+#   30  ir_tx               29      zc_up               28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   0   sta_485_led         1       tx\rx_led           3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      pwr_led             65      adc_12v
+#   66  adc_3.3v            68      485_rxd             69      485_txd
+#   12  rf_spi_clk          35      rf_clk
+
+rc_hdr
+    hw_ver      0x00000000
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+#   extern flash spi gpio
+    39  1   69  #GPIO_SPI_FLASH_CS
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    36  1   71  #GPIO_SPI_FLASH_MISO
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+
+    32  1   7   #GPIO_RS485_TXE
+    31  1   12  #GPIO_PM_CHARGE_EN
+    29  1   18  #GPIO_PA_ZC
+
+    30  1   8   #GPIO_IR_TXD
+    34  1   9   #GPIO_IR_RXD
+
+    35  1   121 #GPIO_RF_CLK
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   current serial port is not multiplexed, uart0(6\5) as download port reserved
+    1   1   3   #UART_IR_PORT
+    tx  30
+    rx  34
+
+    2   1   0   #UART_PRINT
+    tx  28
+
+    3   1   2   #UART_METER_PORT
+    tx  69
+    rx  68
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   6   #IOT_RS485_LED
+    ledout  1
+
+    1   1   7   #IOT_PLC_TR_LED
+    ledout  0
+
+    2   1   5   #IOT_PWR_LED
+    ledout  64
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    29
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#==================== 13.10.08.01(HW_VERSION_QJ_MASKCHIP_V1) ==================#
+# QJ IIC 覆膜HZ3211芯片 资源与QJ5582D的一样
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      ext_flash_cs
+#   38  ext_flash_clk       36      ext_flash_miso      37      ext_flash_mosi
+#   34  ir_rx               32      485_ctr             31      charge_en
+#   30  ir_tx               29      zc_up               28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   0   sta_485_led         1       tx\rx_led           3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      pwr_led             65      adc_12v
+#   66  adc_3.3v            68      485_rxd             69      485_txd
+#   12  rf_spi_clk          35      rf_clk
+
+rc_hdr
+    hw_ver      0x0D0A0801  #13.10.08.01
+    mode        1
+    d_hw_ver    0x00000000
+
+#================== 13.10.04.29(HW_VERSION_IIC_DM_LOAD_V1) ====================#
+# QJ IIC 带小负载覆膜HZ3211芯片
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      ext_flash_cs
+#   38  ext_flash_clk       36      ext_flash_miso      37      ext_flash_mosi
+#   34  ir_rx               32      485_ctr             31      charge_en
+#   30  ir_tx               29      zc_up               28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   0   sta led             1       tx\rx led           3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      pwr_led             65      adc_12v
+#   66  adc_3.3v            68      485_rxd             69      485_txd
+#   12  rf_spi_clk          35      rf_clk              67      load_send
+
+rc_hdr
+    hw_ver      0x0D0A041D  #13.10.04.29
+    mode        1
+    d_hw_ver    0x0D0A0801
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   load send gpio
+    67  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO67和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
diff --git a/tools/oem/QJ5582DSTA03_OEM.bin b/tools/oem/QJ5582DSTA03_OEM.bin
new file mode 100755
index 0000000..dc49799
Binary files /dev/null and b/tools/oem/QJ5582DSTA03_OEM.bin differ
diff --git a/tools/oem/QJ5582DSTA03_OEM.ini b/tools/oem/QJ5582DSTA03_OEM.ini
new file mode 100644
index 0000000..db7bc2e
--- /dev/null
+++ b/tools/oem/QJ5582DSTA03_OEM.ini
@@ -0,0 +1,303 @@
+# QJ5582D sta board
+general
+    bid     61  #BOARD_QJSTA03
+    mid     0   #MODULE_TYPE_STA
+    vid     QJ
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_crt
+#   34  rf_clk              32      set                 31      charge_en
+#   12  rf_spi_clk          29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_0)        65      adc_12v(adc_1)
+#   66  adc_3.3v(adc_2)     67      d_rst(soft reset)   68      zc_a_up
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    3   1   10  #GPIO_GEODE_OVT
+    32  1   17  #GPIO_GOLDEN_SET
+
+    29  1   1   #GPIO_STA_OUT
+
+    69  1   0   #GPIO_PLC_EVENT
+    39  1   120 #GPIO_LIC_CTRL
+
+    0   1   3   #GPIO_RX_LED
+    1   1   2   #GPIO_TX_LED
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+
+    68  1   18  #GPIO_PA_ZC
+
+    67  1   13  #GPIO_RST_CTRL
+    34  1   121 #GPIO_RF_CLK
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND
+    1   1   0   #ADC_PM_12V
+    2   1   1   #ADC_PM_3V
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3211覆膜为QJ5582D
+#   chip id: 0x1001     subid: 0x1011
+
+#=================== 13.10.08.01(HW_VERSION_QJ_MASKCHIP_V1) ===================#
+# QJ STA 覆膜HZ3211芯片 资源与QJ5582D的一样
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_crt
+#   34  rf_clk              32      set                 31      charge_en
+#   12  rf_spi_clk          29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_0)        65      adc_12v(adc_1)
+#   66  adc_3.3v(adc_2)     67      d_rst(soft reset)   68      zc_a_up
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A0801  #13.10.08.01   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+#================== 13.10.01.29(HW_VERSION_STA_3PS_DM_LOAD_V1) ================#
+# QJ STA 带小负载 覆膜HZ3211芯片
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_crt
+#   34  rf_clk              32      set                 31      charge_en
+#   12  rf_spi_clk          29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_0)        65      adc_12v(adc_1)
+#   66  adc_3.3v(adc_2)     67      d_rst(soft reset)   68      zc_a_up
+#   69  event               12      rf_spi_clk          30      load_send
+
+rc_hdr
+    hw_ver      0x0D0A011D  #13.10.01.29
+    mode        1
+    d_hw_ver    0x0D0A0801
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   load send gpio
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+#=============================== 13.10.01.12(HW_VERSION_STA_CKQ_DM_V1) ==============#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_crt
+#   34  nc                  32      set                 31      charge_en
+#   12  rf_spi_clk          29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_0)        65      adc_12v(adc_1)
+#   66  adc_3.3v(adc_2)     67      d_rst(soft reset)   68      zc_a_up
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A010C  #13.10.01.12   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    34  255   255 #GPIO_SPI_RF_CLK
+
+#=================== 13.10.01.21(HW_VERSION_QJ_STA_DM_FLASH_EXT_V1) ===================#
+# QJ STA 覆膜HZ3211芯片 资源与QJ5582D的一样
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  mo_clk_flash        37      mo_si_flash         36      mi_so_flash
+#   35  mo_cs_flash         34      rf_clk              33      nc
+#   32  set                 31      charge_en           30      nc
+#   29  sta_out             28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              27      nc
+#   1   tx_led              0       rx_led              3       pa_testp
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_0)        65      adc_12v(adc_1)
+#   66  adc_3.3v(adc_2)     67      d_rst(soft reset)   68      zc_a_up
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A0115  #13.10.01.21   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+    36  1   71  #GPIO_SPI_FLASH_MISO
+    35  1   69  #GPIO_SPI_FLASH_CS
+
+#=============================== 13.10.01.22(HW_VERSION_QJ_STA_SPG_DM_V1) ====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_crt
+#   38  nc                  37      nc                  36      nc
+#   35  nc                  34      rf_clk              33      nc
+#   32  set                 31      charge_en           30      nc
+#   29  sta_out             28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              27      multi
+#   1   tx_led              0       rx_led              3       pa_testp
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_0)        65      adc_12v(adc_1)
+#   66  adc_3.3v(adc_2)     67      d_rst(soft reset)   68      zc_a_up
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A0116  #13.10.01.22   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    27  1   127 #GPIO_MULTI_PULSE
\ No newline at end of file
diff --git a/tools/oem/SI301X_30P_OEM.ini b/tools/oem/SI301X_30P_OEM.ini
new file mode 100644
index 0000000..ae1a872
--- /dev/null
+++ b/tools/oem/SI301X_30P_OEM.ini
@@ -0,0 +1,23 @@
+general
+ bid 46
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ log
+
+uart1
+ tx 34
+ rx 35
+ ext
+
+uart2
+ tx 8
+ rx 9
+ cli
+
+# led's option: tx
+led
+ tx 32
diff --git a/tools/oem/SI303X_30P_OEM.ini b/tools/oem/SI303X_30P_OEM.ini
new file mode 100644
index 0000000..4941554
--- /dev/null
+++ b/tools/oem/SI303X_30P_OEM.ini
@@ -0,0 +1,48 @@
+# see KL3_EXAMPLE_OEM.ini for file format description
+general
+    bid     58  #BOARD_SI303X_30P
+    mid     0   #sta\cco
+    vid     HT
+    fver    1
+
+#======== 107.10.1.30(HW_VERSION_IOT_CUS_SI303X_KL3), siqi, default rc ========#
+# overview
+# gpio  function        gpio    function        gpio    function
+#   34  gpio34          35      gpio35          36      gpio36
+#   37  gpio37          38      gpio38          39      gpio39
+#   0   gpio00          4       gpio04          7       gpio07
+#   2   uart1_rx        3       uart1_tx        67      adc3/gpio67
+#   68  adc4/gpio68     69      adc5/gpio69     8       pwm2/gpio08
+#   26  pwm1/gpio26     5       uart0_rx        6       uart0_tx
+#   31  gpio31          1       led_trx         32      uart2_rx
+#   33  uart2_tx
+
+rc_hdr
+    hw_ver      0x6B0A011E  #107.10.1.30
+    mode        0
+    d_hw_ver    0xffffffff
+
+uart
+    0   1   0   #UART_PRINT
+    tx  6
+    rx  5
+
+    1   1   11  #UART_CUS_PORT_0
+    tx  3
+    rx  2
+
+    2   1   1  #UART_CLI_PORT
+    tx  33
+    rx  32
+
+adc #ADC resource allocation
+    #3   1  #
+    4   1   12   #ADC_CUS_ADC
+    #5   1
+
+ledc
+    0   1   7   #IOT_PLC_TR_LED
+    ledout  1
+
+
+
diff --git a/tools/oem/SOLRCCO01_OEM.ini b/tools/oem/SOLRCCO01_OEM.ini
new file mode 100755
index 0000000..8e889c5
--- /dev/null
+++ b/tools/oem/SOLRCCO01_OEM.ini
@@ -0,0 +1,44 @@
+general
+ bid 4
+ mid 1
+ vid HT
+
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ log
+
+uart2
+ tx 0
+ rx 1
+ cli
+
+led
+ tx 32
+ rx 33
+ phase_a 34
+ phase_b 35
+ phase_c 36
+
+tx_e
+ phase_a 26
+ phase_b 24
+ phase_c 22
+
+rx_e
+ phase_a 27
+ phase_b 25
+ phase_c 23
+
+glna
+ phase_a 28
+ phase_b 20
+ phase_c 21
+
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/SOLRSTA01_OEM.ini b/tools/oem/SOLRSTA01_OEM.ini
new file mode 100755
index 0000000..3e395c7
--- /dev/null
+++ b/tools/oem/SOLRSTA01_OEM.ini
@@ -0,0 +1,26 @@
+general
+ bid 36
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 34
+ rx 35
+ cli
+
+uart2
+ tx 8
+ rx 9
+ log
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 32
+ rx 33
+
diff --git a/tools/oem/SPE73013PS03_OEM.ini b/tools/oem/SPE73013PS03_OEM.ini
new file mode 100644
index 0000000..fa5ae9e
--- /dev/null
+++ b/tools/oem/SPE73013PS03_OEM.ini
@@ -0,0 +1,222 @@
+# SPE7301 3ps board, external rf chip, external pa chip.
+general
+    bid     76  #BOARD_SPE3PS03
+    mid     4   #MODULE_TYPE_3_PHASE_STA
+    vid     PE
+    fver    1
+
+#===================================== 真实资源 ===============================#
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      ext_flash_clk
+#   38  ext_flash_mosi      37      ext_flash_miso      36      zc_b_up
+#   35  zc_c_up             34      rf_clk              33      ext_flash_cs
+#   32  set(sta)            31      charge_en           29      sta_out
+#   28  uart2_tx            46      rf_agc_gain         45      rf_enable
+#   44  rf_txnrx            47      rf_dq0              48      rf_dq1
+#   49  rf_dq2              1       tx_led              0       rx_led
+#   3   pa_testp(warning)   2       pa_rx_en            4       pa_tx_en
+#   7   pa_lan_gain_ctr0    6       uart0_tx            5       uart0_rx
+#   8   pa_lan_gain_ctr1    26      pa_lan_gain_ctr2    50      rf_dq3
+#   51  rf_dq4              52      rf_dq5              53      rf_dq6
+#   54  rf_dq7              55      rf_dq8              56      rf_dq9
+#   57  rf_dq10             58      rf_dq11             59      rf_pd
+#   61  pa_lic_ctr          62      rf_channel_sw(io)   64      m_sta(adc0_gnd)
+#   65  adc1_12v            66      adc2_3.3v           67      d_rst(soft reset)
+#   68  zc_a_up             69      event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+#   no extern flash spi gpio
+
+    36  1   19  #GPIO_PB_ZC
+    35  1   20  #GPIO_PC_ZC
+    68  1   18  #GPIO_PA_ZC
+
+    34  1   121 #GPIO_RF_CLK
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   12  #GPIO_PM_CHARGE_EN
+    29  1   1   #GPIO_STA_OUT
+    3   1   10  #GPIO_GEODE_OVT
+    61  1   120 #GPIO_LIC_CTRL
+    67  1   13  #GPIO_RST_CTRL
+    69  1   0   #GPIO_PLC_EVENT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+#   up_1    36
+#   up_2    35
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3211覆膜为SPE7301
+#   chip id: 0x1001     subid: 0x1031
+
+#==================== 13.10.08.03(HW_VERSION_SPE_MASKCHIP_V1) =================#
+# SPE 3PS 覆膜 不带小负载
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      ext_flash_clk
+#   38  ext_flash_mosi      37      ext_flash_miso      36      zc_b_up
+#   35  zc_c_up             34      rf_clk              33      ext_flash_cs
+#   32  set(sta)            31      charge_en           29      sta_out
+#   28  uart2_tx            46      rf_agc_gain         45      rf_enable
+#   44  rf_txnrx            47      rf_dq0              48      rf_dq1
+#   49  rf_dq2              1       tx_led              0       rx_led
+#   3   pa_testp(warning)   2       pa_rx_en            4       pa_tx_en
+#   7   pa_lan_gain_ctr0    6       uart0_tx            5       uart0_rx
+#   8   pa_lan_gain_ctr1    26      pa_lan_gain_ctr2    50      rf_dq3
+#   51  rf_dq4              52      rf_dq5              53      rf_dq6
+#   54  rf_dq7              55      rf_dq8              56      rf_dq9
+#   57  rf_dq10             58      rf_dq11             59      rf_pd
+#   61  pa_lic_ctr          62      rf_channel_sw(io)   64      m_sta(adc0_gnd)
+#   65  adc1_12v            66      adc2_3.3v           67      d_rst(soft reset)
+#   68  zc_a_up             69      event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A0803  #13.10.08.03   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+
+#   extern flash spi gpio
+    33  1   69  #GPIO_SPI_FLASH_CS
+    39  1   68  #GPIO_SPI_FLASH_CLK
+    37  1   71  #GPIO_SPI_FLASH_MISO
+    38  1   70  #GPIO_SPI_FLASH_MOSI
+
+#================== 13.10.01.29(HW_VERSION_STA_3PS_DM_LOAD_V1) ================#
+# SPE 3PS 覆膜 带小负载
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      ext_flash_clk
+#   38  ext_flash_mosi      37      ext_flash_miso      36      zc_b_up
+#   35  zc_c_up             34      rf_clk              33      ext_flash_cs
+#   32  set(sta)            31      charge_en           29      sta_out
+#   28  uart2_tx            46      rf_agc_gain         45      rf_enable
+#   44  rf_txnrx            47      rf_dq0              48      rf_dq1
+#   49  rf_dq2              1       tx_led              0       rx_led
+#   3   pa_testp(warning)   2       pa_rx_en            4       pa_tx_en
+#   7   pa_lan_gain_ctr0    6       uart0_tx            5       uart0_rx
+#   8   pa_lan_gain_ctr1    26      pa_lan_gain_ctr2    50      rf_dq3
+#   51  rf_dq4              52      rf_dq5              53      rf_dq6
+#   54  rf_dq7              55      rf_dq8              56      rf_dq9
+#   57  rf_dq10             58      rf_dq11             59      rf_pd
+#   61  pa_lic_ctr          62      rf_channel_sw(io)   64      m_sta(adc0_gnd)
+#   65  adc1_12v            66      adc2_3.3v           67      d_rst(soft reset)
+#   68  zc_a_up             69      event               12      rf_spi_clk
+#   30  fz_send(load)
+
+rc_hdr
+    hw_ver      0x0D0A011D  #13.10.01.29   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x0D0A0803
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+
+#   no extern flash spi gpio
+    33  1   255
+    39  1   255
+    37  1   255
+    38  1   255
+
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
diff --git a/tools/oem/SPE7301IIC03_OEM.ini b/tools/oem/SPE7301IIC03_OEM.ini
new file mode 100644
index 0000000..2204a00
--- /dev/null
+++ b/tools/oem/SPE7301IIC03_OEM.ini
@@ -0,0 +1,206 @@
+# see KL3_EXAMPLE_OEM.ini for file format description
+# SPE7301 IIC board, external rf chip, external pa chip.
+general
+    bid     74  #BOARD_SPEIIC03
+    mid     2   #MODULE_TYPE_COLLECTOR_II
+    vid     PE
+    fver    1
+
+#===================================== 真实资源 ===============================#
+# NONE
+
+#===================================== 覆膜资源 ===============================#
+# HZ3211覆膜为SPE7301
+#   chip id: 0x1001     subid: 0x1031
+
+#================================= default rc =================================#
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      ext_flash_cs
+#   38  ext_flash_clk       36      ext_flash_miso      37      ext_flash_mosi
+#   34  ir_rx               32      485_ctr             31      charge_en
+#   30  ir_tx               29      zc_up               28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   0   sta_485_led         1       tx\rx_led           3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      pwr_led             65      adc_12v
+#   66  adc_3.3v            68      485_rxd             69      485_txd
+#   12  rf_spi_clk          35      rf_clk
+
+rc_hdr
+    hw_ver      0x00000000
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+#   extern flash spi gpio
+    39  1   69  #GPIO_SPI_FLASH_CS
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    36  1   71  #GPIO_SPI_FLASH_MISO
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+
+    32  1   7   #GPIO_RS485_TXE
+    31  1   12  #GPIO_PM_CHARGE_EN
+    30  1   8   #GPIO_IR_TXD
+    34  1   9   #GPIO_IR_RXD
+    29  1   18  #GPIO_PA_ZC
+    35  1   121 #GPIO_RF_CLK
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+#   current serial port is not multiplexed, uart0(6\5) as download port reserved
+    1   1   3   #UART_IR_PORT
+    tx  30
+    rx  34
+
+    2   1   0   #UART_PRINT
+    tx  28
+
+    3   1   2   #UART_METER_PORT
+    tx  69
+    rx  68
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   6   #IOT_RS485_LED
+    ledout  1
+
+    1   1   7   #IOT_PLC_TR_LED
+    ledout  0
+
+    2   1   5   #IOT_PWR_LED
+    ledout  64
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    29
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#=================== 13.10.08.03(HW_VERSION_SPE_MASKCHIP_V1) ==================#
+# SPE IIC 覆膜 不带小负载
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      ext_flash_cs
+#   38  ext_flash_clk       36      ext_flash_miso      37      ext_flash_mosi
+#   34  ir_rx               32      485_ctr             31      charge_en
+#   30  ir_tx               29      zc_up               28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   0   sta_485_led         1       tx\rx_led           3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      pwr_led             65      adc_12v
+#   66  adc_3.3v            68      485_rxd             69      485_txd
+#   12  rf_spi_clk          35      rf_clk
+
+rc_hdr
+    hw_ver      0x0D0A0803  #13.10.08.03
+    mode        1
+    d_hw_ver    0x00000000
+
+#=================== 13.10.04.29(HW_VERSION_IIC_DM_LOAD_V1) ===================#
+# SPE IIC 覆膜 带小负载
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             35      rf_clk
+#   34  ir_rx               32      485_ctr             31      charge_en
+#   30  ir_tx               29      zc_up               28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   0   sta_485_led         1       tx\rx_led           3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      pwr_led             65      adc_12v
+#   66  adc_3.3v            68      485_rxd             69      485_txd
+#   12  rf_spi_clk          67      fz_send(load)
+
+rc_hdr
+    hw_ver      0x0D0A041D  #13.10.04.29
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   no extern flash spi gpio
+    39  1   255
+    38  1   255
+    36  1   255
+    37  1   255
+
+    67  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO67和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
diff --git a/tools/oem/SPE7301STA03_OEM.ini b/tools/oem/SPE7301STA03_OEM.ini
new file mode 100644
index 0000000..9429990
--- /dev/null
+++ b/tools/oem/SPE7301STA03_OEM.ini
@@ -0,0 +1,245 @@
+# SPE7301 sta board, external rf chip, external pa chip.
+general
+    bid     75  #BOARD_SPESTA03
+    mid     0   #MODULE_TYPE_STA
+    vid     PE
+    fver    1
+
+#===================================== 真实资源 ===============================#
+
+#=============================== default rc====================================#
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  ext_flash_clk       37      ext_flash_mosi      36      ext_flash_miso
+#   35  ext_flash_cs        34      rf_clk              32      set
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      m_sta(adc0)         65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(adc3)         68      zc_a_up(adc4)
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+#   no extern flash spi gpio
+
+    39  1   120 #GPIO_LIC_CTRL
+    34  1   121 #GPIO_RF_CLK
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   12  #GPIO_PM_CHARGE_EN
+    29  1   1   #GPIO_STA_OUT
+    3   1   10  #GPIO_GEODE_OVT
+    67  1   13  #GPIO_RST_CTRL
+    68  1   18  #GPIO_PA_ZC
+    69  1   0   #GPIO_PLC_EVENT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3211覆膜为SPE7301
+#   chip id: 0x1001     subid: 0x1031
+
+#=================== 13.10.08.03(HW_VERSION_SPE_MASKCHIP_V1) ==================#
+# SPE STA 覆膜 不带小负载
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  ext_flash_clk       37      ext_flash_mosi      36      ext_flash_miso
+#   35  ext_flash_cs        34      rf_clk              32      set
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      m_sta(adc0)         65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(adc3)         68      zc_a_up(adc4)
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A0803  #13.10.08.03
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   extern flash spi gpio
+    35  1   69  #GPIO_SPI_FLASH_CS
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    36  1   71  #GPIO_SPI_FLASH_MISO
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+
+#================== 13.10.01.29(HW_VERSION_STA_3PS_DM_LOAD_V1) ================#
+# SPE STA 覆膜 带小负载
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  ext_flash_clk       37      ext_flash_mosi      36      ext_flash_miso
+#   35  ext_flash_cs        34      rf_clk              32      set
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      m_sta(adc0)         65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(adc3)         68      zc_a_up(adc4)
+#   69  event               12      rf_spi_clk          30      fz_send(load)
+
+rc_hdr
+    hw_ver      0x0D0A011D  #13.10.01.29
+    mode        1
+    d_hw_ver    0x0D0A0803
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   no extern flash spi gpio
+    35  1   255
+    38  1   255
+    36  1   255
+    37  1   255
+
+    30  1   82  #GPIO_TSFM_LOAD_TRIGGER
+
+pwm    #pwm resource allocation
+#  A:pwm channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about pwm type)
+#   A   B   C
+#   小负载流程中，
+#   获取GPIO30和PWM（PWM_CH_TYPE_TSFM_LOAD_CTRL）通道，
+#   然后软件主动绑定。
+    1   1   3   #PWM_CH_TYPE_TSFM_LOAD_CTRL
+
+#=============================== 13.10.01.12(HW_VERSION_STA_CKQ_DM_V1) ==============#
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  ext_flash_clk       37      ext_flash_mosi      36      ext_flash_miso
+#   35  ext_flash_cs        34      nc                  32      set
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      m_sta(adc0)         65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(adc3)         68      zc_a_up(adc4)
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A010C  #13.10.01.12   Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    34  255   255 #GPIO_SPI_RF_CLK
diff --git a/tools/oem/SPE7303CCO03_OEM.ini b/tools/oem/SPE7303CCO03_OEM.ini
new file mode 100644
index 0000000..6c4eb6a
--- /dev/null
+++ b/tools/oem/SPE7303CCO03_OEM.ini
@@ -0,0 +1,191 @@
+# SPE7303 cco board
+general
+    bid     77  #BOARD_SPECCO03
+    mid     1   #MODULE_TYPE_CCO
+    vid     PE
+    fver    1
+
+#===================================== 真实资源 ===============================#
+
+#================================= default rc =================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      zc_c_up
+#   38  zc_c_down           37      zc_b_up             36      zc_b_down
+#   35  zc_a_up             34      pa_led\uart1_tx     33      pb_led\uart1_rx
+#   32  pc_led              31      charge_en           30      pa_c_tx_en
+#   29  pa_c_rx_en          28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp            2       pa_rx_en
+#   4   pa_tx_en            7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      uart2_rx(cli)       62      rf_channel_sw(io)
+#   64  m_sta(adc_0)        65      adc_12v             66      adc_3.3v
+#   67  pa_b_tx_en          68      zc_a_down           69      pa_b_rx_en
+#   12  rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    3   1   10  #GPIO_GEODE_OVT
+
+    32  1   6   #GPIO_PC_LED
+    0   1   3   #GPIO_RX_LED
+    1   1   2   #GPIO_TX_LED
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+
+    35  1   18  #GPIO_PA_ZC
+    37  1   19  #GPIO_PB_ZC
+    39  1   20  #GPIO_PC_ZC
+    68  1   44  #GPIO_PA_ZC_EXT
+    36  1   45  #GPIO_PB_ZC_EXT
+    38  1   46  #GPIO_PC_ZC_EXT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   1   #UART_CLI_PORT
+    tx  28
+    rx  61
+
+    1   1   0   #UART_PRINT
+    tx  34
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   2   #IOT_PLC_PHASE_A_LED
+    ledout  34
+
+    1   1   3   #IOT_PLC_PHASE_B_LED
+    ledout  33
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  32
+
+    3   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    4   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND
+    1   1   0   #ADC_PM_12V
+    2   1   1   #ADC_PM_3V
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+#   up_0    35
+#   up_1    37
+#   up_2    39
+#   down_0  68
+#   down_1  36
+#   down_2  38
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    tx_en_1 67  #Phase B Enable sending
+    rx_en_1 69  #Phase B Enable receiving
+    tx_en_2 30  #Phase C Enable sending
+    rx_en_2 29  #Phase C Enable receiving
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#===================================== 覆膜资源 ===============================#
+# HZ3201覆膜为SPE7303
+#   chip id: 0x1003     subid: 0x1033
+
+#================== 13.10.08.03(HW_VERSION_SPE_MASKCHIP_V1) ===================#
+# SPE CCO 覆膜HZ3201芯片 资源与SPE7303的一样
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      zc_c_up
+#   38  zc_c_down           37      zc_b_up             36      zc_b_down
+#   35  zc_a_up             34      pa_led\uart1_tx     33      pb_led\uart1_rx
+#   32  pc_led              31      charge_en           30      pa_c_tx_en
+#   29  pa_c_rx_en          28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              1       tx_led
+#   0   rx_led              3       pa_testp            2       pa_rx_en
+#   4   pa_tx_en            7       pa_lan_gain_ctr0    6       uart0_tx
+#   5   uart0_rx            8       pa_lan_gain_ctr1    26      pa_lan_gain_ctr2
+#   50  rf_dq3              51      rf_dq4              52      rf_dq5
+#   53  rf_dq6              54      rf_dq7              55      rf_dq8
+#   56  rf_dq9              57      rf_dq10             58      rf_dq11
+#   59  rf_pd               61      uart2_rx(cli)       62      rf_channel_sw(io)
+#   64  m_sta(adc_0)        65      adc_12v             66      adc_3.3v
+#   67  pa_b_tx_en          68      zc_a_down           69      pa_b_rx_en
+#   12  rf_spi_clk
+
+rc_hdr
+    hw_ver      0x0D0A0803  #13.10.08.03 Hardware identification, HEX
+    mode        1
+    d_hw_ver    0x00000000
+
diff --git a/tools/oem/SPE7303CKB03_OEM.ini b/tools/oem/SPE7303CKB03_OEM.ini
new file mode 100644
index 0000000..aa3c171
--- /dev/null
+++ b/tools/oem/SPE7303CKB03_OEM.ini
@@ -0,0 +1,115 @@
+# SPE7303 ckb board, external rf chip, external pa chip.
+general
+    bid     89  #BOARD_SPECKB03
+    mid     0   #MODULE_TYPE_STA
+    vid     PE
+    fver    1
+
+#=============================== default rc====================================#
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  nc                  37      nc                  36      nc
+#   35  nc                  34      rf_clk              32      set
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      m_sta(adc0)         65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(adc3)         68      zc_a_up(adc4)
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    39  1   120 #GPIO_LIC_CTRL
+    34  1   121 #GPIO_RF_CLK
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   12  #GPIO_PM_CHARGE_EN
+    29  1   1   #GPIO_STA_OUT
+    3   1   10  #GPIO_GEODE_OVT
+    67  1   13  #GPIO_RST_CTRL
+    68  1   18  #GPIO_PA_ZC
+    69  1   0   #GPIO_PLC_EVENT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
diff --git a/tools/oem/STAMP03_OEM.ini b/tools/oem/STAMP03_OEM.ini
new file mode 100644
index 0000000..d4813b0
--- /dev/null
+++ b/tools/oem/STAMP03_OEM.ini
@@ -0,0 +1,122 @@
+# see KL3_EXAMPLE_OEM.ini for file format description
+# HZ3031 iot stamp board, internal pa chip.
+# iot module are allocated resources by app, oem is only binding signal.
+general
+    bid     57  #BOARD_STAMP03
+    mid     0   #sta\cco
+    vid     HT
+    fver    1
+
+#========= 100.11.1.30(HW_VERSION_IOT_Y001S_KL3), yonglin, default rc =========#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   69  adc5/gpio69         05      uart0_rx            06      uart0_tx
+#   26  pwm1/io0            39      io1                 38      io18
+#   37  io19                36      io20                35      io12
+#   31  io11                08      pwm/io4             07      pwm/io3
+#   04  pwm/io15            01      io16                00      io17
+#   02  uart1-rx/io9        03      uart1-tx/io10       33      uart2-tx
+#   32  uart2-rx            34      tx\rx led
+
+rc_hdr
+    hw_ver      0x640B011E  #100.11.1.30
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+    26  1   95  #GPIO_CUS_IO_0
+    39  1   96  #GPIO_CUS_IO_1
+    38  1   104 #GPIO_CUS_IO_18
+    37  1   105 #GPIO_CUS_IO_19
+    36  1   106 #GPIO_CUS_IO_20
+    35  1   100 #GPIO_CUS_IO_12
+    31  1   99  #GPIO_CUS_IO_11
+    8   1   98  #GPIO_CUS_IO_4
+    7   1   97  #GPIO_CUS_IO_3
+    4   1   101 #GPIO_CUS_IO_15
+    1   1   102 #GPIO_CUS_IO_16
+    0   1   103 #GPIO_CUS_IO_17
+
+uart    #UART resource allocation
+    # current serial port is not multiplexed, uart0(6\5) as download port reserved
+    0   1   0   #UART_PRINT
+    tx  6
+    rx  5
+
+    1   1   11  #UART_CUS_PORT_0
+    tx  3
+    rx  2
+
+    2   1   1   #UART_CLI_PORT
+    tx  33
+    rx  32
+
+ledc
+    0   1   7   #IOT_PLC_TR_LED
+    ledout  34
+
+adc #ADC resource allocation
+    5   1   12   #ADC_CUS_ADC
+
+# internal sealing one pa chips
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 80  #enlic_pad_0. Phase A Enable receiving
+    tx_en_0 81  #enlic_pad_1. Phase A Enable sending
+    gain_0  82  #glna_pad_0. Phase A gain control
+    gain_1  83  #glna_pad_1. Phase B gain control
+    gain_2  84  #glna_pad_2. Phase C gain control
+
+#============ 102.10.1.30(HW_VERSION_IOT_Q111N_ISF_KL3), ouzitong =============#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   02  uart1-rx\io9        03      uart1-tx\io10       00      io15
+#   07  io3\spi_di          04      io1\spi_clk         26      io0\pwm0
+#   31  io2\spi_cs          39      io20                37      io12
+#   34  io4\spi_do          35      io16                36      io18
+#   06  uart0-tx\io14       05      uart0-rx\io13       69      vin4(adc5)
+#   38  io17                08      io5\pwm1            33      uart2-tx
+#   32  uart2-rx            01      tx\rx led
+rc_hdr
+    hw_ver      0x660A011E  #102.10.1.30
+    mode        1
+    d_hw_ver    0x640B011E
+gpio    #GPIO resource allocation
+    34  255 255 #cancel
+ledc
+    0   1   7   #IOT_PLC_TR_LED
+    ledout  01
+
+#============= 103.10.1.30(HW_VERSION_IOT_Q111N_H_KL3), ouzitong ==============#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   03  uart1-tx\io10       02      uart1-rx\io9        26      io0\pwm0
+#   08  io5\pwm1            04      io9                 06      uart0-tx
+#   05  uart0-rx            33      uart2-tx            32      uart2-rx
+#   01  led
+rc_hdr
+    hw_ver      0x670A011E  #103.10.1.30
+    mode        1
+    d_hw_ver    0x640B011E
+gpio    #GPIO resource allocation
+    34  255 255 #cancel
+ledc
+    0   1   7   #IOT_PLC_TR_LED
+    ledout  01
+
+#============= 104.10.1.30(HW_VERSION_IOT_Q111N_HS_KL3), ouzitong =============#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   26  pwm1\io23           02      uart1-rx            04      io36
+#   03  uart1-tx            08      pwm2\io22           05      uart0-rx
+#   06  uart0-tx            33      uart2-tx            32      uart2-rx
+#   01  led
+rc_hdr
+    hw_ver      0x680A011E  #104.10.1.30
+    mode        1
+    d_hw_ver    0x640B011E
+gpio    #GPIO resource allocation
+    34  255 255 #cancel
+ledc
+    0   1   7   #IOT_PLC_TR_LED
+    ledout  01
+
diff --git a/tools/oem/STAMP_22P_OEM.ini b/tools/oem/STAMP_22P_OEM.ini
new file mode 100644
index 0000000..74a90cd
--- /dev/null
+++ b/tools/oem/STAMP_22P_OEM.ini
@@ -0,0 +1,27 @@
+general
+ bid 41
+ mid 0
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ log
+
+uart1
+ tx 34
+ rx 35
+ ext
+
+uart2
+ tx 8
+ rx 9
+ cli
+
+# led's option: tx
+# ISF and YY01 common oem file, ISF tx is gpio32, YY01 tx is gpio42,
+# not binding pin function in oem loading, it always error for another board
+# if open this setting.
+# solution: disable it in oem file and binding this pin in led init.
+#led
+# tx 42
diff --git a/tools/oem/TFMTI3C02_OEM.ini b/tools/oem/TFMTI3C02_OEM.ini
new file mode 100755
index 0000000..11e9175
--- /dev/null
+++ b/tools/oem/TFMTI3C02_OEM.ini
@@ -0,0 +1,43 @@
+general
+ bid 31
+ mid 2
+ vid HT
+
+# uart's option: tx/rx
+uart0
+ ext
+
+uart1
+ tx 20
+ rx 21
+ ir
+
+uart2
+ tx 28
+ log
+
+#uart3
+# ext
+# tx 20
+# rx 21
+
+# led's option: tx/rx/rs485/phase_a/phase_b/phase_c
+led
+ tx 27
+ rx 26
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 23
+ phase_b 18
+ phase_c 19
+
+spi
+ clk 41
+ mosi 42
+ miso 43
+
+#use iic0
+iic
+ sda 24
+ scl 25
diff --git a/tools/oem/WQRDCCO01_OEM.ini b/tools/oem/WQRDCCO01_OEM.ini
new file mode 100755
index 0000000..da1a230
--- /dev/null
+++ b/tools/oem/WQRDCCO01_OEM.ini
@@ -0,0 +1,43 @@
+general
+ bid 1
+ vid WQ
+ mid 1
+
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 0
+ rx 1
+ log
+
+uart2
+ tx 18
+ rx 19
+ cli
+
+uart3
+ tx 2
+ rx 3
+
+tx_e
+ phase_a 26
+ phase_b 24
+ phase_c 22
+
+rx_e
+ phase_a 27
+ phase_b 25
+ phase_c 23
+ 
+glna
+ phase_a 28
+ phase_b 20
+ phase_c 21
+
+zc
+ phase_a 47
+ phase_b 48
+ phase_c 45
diff --git a/tools/oem/WQRDCCO02_OEM.ini b/tools/oem/WQRDCCO02_OEM.ini
new file mode 100644
index 0000000..a566547
--- /dev/null
+++ b/tools/oem/WQRDCCO02_OEM.ini
@@ -0,0 +1,11 @@
+general
+ bid 13
+ mid 1
+
+uart1
+ tx 43
+ rx 44
+
+uart2
+ tx 39
+ rx 40
diff --git a/tools/oem/WQRDIIC01_OEM.ini b/tools/oem/WQRDIIC01_OEM.ini
new file mode 100755
index 0000000..5a6f3a0
--- /dev/null
+++ b/tools/oem/WQRDIIC01_OEM.ini
@@ -0,0 +1,22 @@
+general
+ bid 3
+ vid WQ
+ mid 2
+
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 22
+ rx 23
+ cli
+
+uart2
+ tx 8
+ rx 9
+ log
+
+zc
+ phase_a 47
diff --git a/tools/oem/WQRDSTA01_OEM.ini b/tools/oem/WQRDSTA01_OEM.ini
new file mode 100755
index 0000000..bbadfc1
--- /dev/null
+++ b/tools/oem/WQRDSTA01_OEM.ini
@@ -0,0 +1,24 @@
+general
+ bid 2
+ vid WQ
+ mid 0
+
+# uart's option: tx/rx
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1
+ tx 22
+ rx 23
+ cli
+
+uart2
+ tx 8
+ rx 9
+ log
+
+# zc's option: phase_a/phase_b/phase_c
+zc
+ phase_a 47
diff --git a/tools/oem/WQRDSTA02_OEM.ini b/tools/oem/WQRDSTA02_OEM.ini
new file mode 100755
index 0000000..3ec2a44
--- /dev/null
+++ b/tools/oem/WQRDSTA02_OEM.ini
@@ -0,0 +1,11 @@
+general
+ bid 14
+ mid 0
+
+uart1
+ tx 43
+ rx 44
+
+uart2
+ tx 39
+ rx 40
diff --git a/tools/oem/YP8801CCO03_OEM.ini b/tools/oem/YP8801CCO03_OEM.ini
new file mode 100644
index 0000000..29ec0a4
--- /dev/null
+++ b/tools/oem/YP8801CCO03_OEM.ini
@@ -0,0 +1,150 @@
+# YP8801 cco board, external rf chip, external pa chip
+general
+    bid     102  #BOARD_YPCCO03
+    mid     1    #MODULE_TYPE_CCO
+    vid     YP
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      zc_c_2
+#   38  zc_c_1              37      zc_b_2              36      zc_b_1
+#   35  zc_a_2              34      pa_led\uart1_tx     33      pb_led\uart1_rx
+#   32  pc_led              31      charge_en           30      pa_c_tx_en
+#   29  pa_c_rx_en          28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              27      nc
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_a_rx_en          4       pa_a_tx_en          7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      uart2_rx
+#   62  rf_channel_sw2(io)  64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      pa_b_tx_en          68      zc_a_1
+#   69  pa_b_rx_en          12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function(to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    9   1   108 #GPIO_SPI_RF_CS
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    12  1   107 #GPIO_SPI_RF_CLK
+
+    3   1   10  #GPIO_GEODE_OVT
+
+    35  1   18  #GPIO_PA_ZC
+    37  1   19  #GPIO_PB_ZC
+    39  1   20  #GPIO_PC_ZC
+    68  1   44  #GPIO_PA_ZC_EXT
+    36  1   45  #GPIO_PB_ZC_EXT
+    38  1   46  #GPIO_PC_ZC_EXT
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   1   #UART_CLI_PORT
+    tx  28
+    rx  61
+
+    1   1   0   #UART_PRINT
+    tx  34
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   2   #IOT_PLC_PHASE_A_LED
+    ledout  34
+
+    1   1   3   #IOT_PLC_PHASE_B_LED
+    ledout  33
+
+    2   1   4   #IOT_PLC_PHASE_C_LED
+    ledout  32
+
+    3   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    4   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+# down_0: Zero-crossing detection descending edge input channel 0,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase A descending edge
+# down_1: Zero-crossing detection descending edge input channel 1,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase B descending edge
+# down_2: Zero-crossing detection descending edge input channel 2,
+#         which by default corresponds to the zero-crossing circuit
+#         of phase C descending edge
+#   up_0    35
+#   up_1    37
+#   up_2    39
+#   down_0  68
+#   down_1  36
+#   down_2  38
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    rx_en_1 69  #Phase B Enable receiving
+    tx_en_1 67  #Phase B Enable sending
+    rx_en_2 29  #Phase C Enable receiving
+    tx_en_2 30  #Phase C Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
\ No newline at end of file
diff --git a/tools/oem/YP8801CKB03_OEM.ini b/tools/oem/YP8801CKB03_OEM.ini
new file mode 100644
index 0000000..bb382a3
--- /dev/null
+++ b/tools/oem/YP8801CKB03_OEM.ini
@@ -0,0 +1,115 @@
+# YP8801 ckb board, external rf chip, external pa chip.
+general
+    bid     103  #BOARD_YPCKB03
+    mid     0    #MODULE_TYPE_STA
+    vid     YP
+    fver    1
+
+#=============================== default rc====================================#
+# overview:
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_mosi         10      rf_spi_miso         9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  nc                  37      nc                  36      nc
+#   35  nc                  34      rf_clk              32      set
+#   31  charge_en           29      sta_out             28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      m_sta(adc0)         65      adc1_12v
+#   66  adc2_3.3v           67      d_rst(adc3)         68      zc_a_up(adc4)
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    39  1   120 #GPIO_LIC_CTRL
+    34  1   121 #GPIO_RF_CLK
+    32  1   17  #GPIO_GOLDEN_SET
+    31  1   12  #GPIO_PM_CHARGE_EN
+    29  1   1   #GPIO_STA_OUT
+    3   1   10  #GPIO_GEODE_OVT
+    67  1   13  #GPIO_RST_CTRL
+    68  1   18  #GPIO_PA_ZC
+    69  1   0   #GPIO_PLC_EVENT
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
\ No newline at end of file
diff --git a/tools/oem/YP88113PS03_OEM.ini b/tools/oem/YP88113PS03_OEM.ini
new file mode 100644
index 0000000..c693b52
--- /dev/null
+++ b/tools/oem/YP88113PS03_OEM.ini
@@ -0,0 +1,166 @@
+# YP8811 3ps board, external rf chip, external pa chip.
+general
+    bid     101  #BOARD_YP3PS03
+    mid     4    #MODULE_TYPE_3_PHASE_STA
+    vid     YP
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      flash_spi_clk
+#   38  flash_spi_mosi      37      flash_spi_miso      36      zc_b
+#   35  zc_c                34      rf_clk              33      mo_cs_flash
+#   32  set(sta)            31      charge_en           30      nc
+#   29  sta_out             28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              27      nc
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      pa_lic_ctr
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    3   1   10  #GPIO_GEODE_OVT
+
+    32  1   17  #GPIO_GOLDEN_SET
+    29  1   1   #GPIO_STA_OUT
+    69  1   0   #GPIO_PLC_EVENT
+    67  1   13  #GPIO_RST_CTRL
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+    68  1   18  #GPIO_PA_ZC
+    36  1   19  #GPIO_PB_ZC
+    35  1   20  #GPIO_PC_ZC
+
+    39  1   120 #GPIO_LIC_CTRL
+    34  1   121 #GPIO_RF_CLK
+
+    39  1   68  #GPIO_SPI_FLASH_CLK
+    38  1   70  #GPIO_SPI_FLASH_MOSI
+    37  1   71  #GPIO_SPI_FLASH_MISO
+    33  1   69  #GPIO_SPI_FLASH_CS
+
+    61  1   120 #GPIO_LIC_CTRL
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28
+
+    0   1   2   #UART_METER_PORT
+    tx  6
+    rx  5
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+# up_1: Zero-crossing detection rising edge input channel 1,
+#       which corresponds to phase B rising edge zero-crossing
+#       circuit by default
+# up_2: Zero-crossing detection rising edge input channel 2,
+#       which corresponds to phase C rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+#   up_1    36
+#   up_2    35
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#================== 13.10.02.71(HW_VERSION_YP_3PS_DM_V1) ================#
+# overview
+# add:27 multi
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      flash_spi_clk
+#   38  flash_spi_mosi      37      flash_spi_miso      36      zc_b
+#   35  zc_c                34      rf_clk              33      flash_spi_cs
+#   32  set(sta)            31      charge_en           30      nc
+#   29  sta_out             28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              27      multi
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      pa_lic_ctr
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0A0247  #13.10.02.71
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    27  1   127 #GPIO_MULTI_PULSE
diff --git a/tools/oem/YP8811IIC03_OEM.ini b/tools/oem/YP8811IIC03_OEM.ini
new file mode 100644
index 0000000..ce1454d
--- /dev/null
+++ b/tools/oem/YP8811IIC03_OEM.ini
@@ -0,0 +1,124 @@
+# YP8811 iic board, external rf chip, external pa chip.
+general
+    bid     106  #BOARD_YPIIC03
+    mid     2   #MODULE_TYPE_COLLECTOR_II
+    vid     YP
+    fver    1
+
+#=============================== default rc====================================#
+# overview: extern flash chip
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_do           10      rf_spi_di           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      ext_flash_cs
+#   38  ext_flash_clk       36      ext_flash_do        37      ext_flash_di
+#   34  ir_rx               32      485_ctr             31      charge_en
+#   30  ir_tx               29      zc_up               28      uart2_tx
+#   46  rf_agc_gain         45      rf_enable           44      rf_txnrx
+#   47  rf_dq0              48      rf_dq1              49      rf_dq2
+#   0   sta led             1       tx\rx led           3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq6
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw1
+#   62  rf_channel_sw2      64      pwr_led             65      adc_12v
+#   66  adc_3.3v            68      485_rxd             69      485_txd
+#   12  rf_spi_clk          35      rf_clk
+
+rc_hdr
+#   the first version of each product line defaults to 0
+    hw_ver      0x00000000
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio    #GPIO resource allocation
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+#   bbcpu spi gpio, query by plc core
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+#   extern flash spi gpio
+    39  1   69  #GPIO_SPI_FLASH_CS
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    36  1   71  #GPIO_SPI_FLASH_MISO
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+
+    32  1   7   #GPIO_RS485_TXE
+    31  1   12  #GPIO_PM_CHARGE_EN
+    29  1   18  #GPIO_PA_ZC
+
+    30  1   8   #GPIO_IR_TXD
+    34  1   9   #GPIO_IR_RXD
+
+    35  1   121 #GPIO_RF_CLK
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+#   current serial port is not multiplexed, uart0(6\5) as download port reserved
+    1   1   3   #UART_IR_PORT
+    tx  30
+    rx  34
+
+    2   1   0   #UART_PRINT
+    tx  28
+
+    3   1   2   #UART_METER_PORT
+    tx  69
+    rx  68
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+    0   1   6   #IOT_RS485_LED
+    ledout  1
+
+    1   1   7   #IOT_PLC_TR_LED
+    ledout  0
+
+    2   1   5   #IOT_PWR_LED
+    ledout  64
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    29
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
diff --git a/tools/oem/YP8811STA03_OEM.ini b/tools/oem/YP8811STA03_OEM.ini
new file mode 100644
index 0000000..9532398
--- /dev/null
+++ b/tools/oem/YP8811STA03_OEM.ini
@@ -0,0 +1,159 @@
+# YP8811 sta board, external rf chip, external pa chip.
+general
+    bid     100  #BOARD_YPSTA03
+    mid     0    #MODULE_TYPE_STA
+    vid     YP
+    fver    1
+
+#=============================== default rc====================================#
+# overview
+# gpio  function            gpio    function            gpio    function
+#   11  rf_spi_di           10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk             43      rf_fclk             39      pa_lic_ctr
+#   38  flash_spi_clk       37      flash_spi_mosi      36      flash_spi_miso
+#   35  flash_spi_cs        34      rf_clk              33      nc
+#   32  set(sta)            31      charge_en           30      nc
+#   29  sta_out             28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable           44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1              49      rf_dq2              27      nc
+#   1   tx_led              0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en            4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx            5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2    50      rf_dq3              51      rf_dq4
+#   52  rf_dq5              53      rf_dq6              54      rf_dq7
+#   55  rf_dq8              56      rf_dq9              57      rf_dq10
+#   58  rf_dq11             59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)   64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v            67      d_rst(soft reset)   68      zc_a
+#   69  event               12      rf_spi_clk
+
+rc_hdr
+    hw_ver      0x00000000  #00.00.00.00   Hardware identification, HEX
+    mode        0
+    d_hw_ver    0xffffffff
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    12  1   107 #GPIO_SPI_RF_CLK
+    11  1   110 #GPIO_SPI_RF_MOSI
+    10  1   109 #GPIO_SPI_RF_MISO
+    9   1   108 #GPIO_SPI_RF_CS
+
+    3   1   10  #GPIO_GEODE_OVT
+
+    32  1   17  #GPIO_GOLDEN_SET
+    5   1   24  #GPIO_GOLDEN_RXD0
+    6   1   34  #GPIO_GOLDEN_TXD0
+    29  1   1   #GPIO_STA_OUT
+    69  1   0   #GPIO_PLC_EVENT
+
+    31  1   12  #GPIO_PM_CHARGE_EN
+    68  1   18  #GPIO_PA_ZC
+    39  1   120 #GPIO_LIC_CTRL
+
+    67  1   13  #GPIO_RST_CTRL
+    34  1   121 #GPIO_RF_CLK
+
+    38  1   68  #GPIO_SPI_FLASH_CLK
+    37  1   70  #GPIO_SPI_FLASH_MOSI
+    36  1   71  #GPIO_SPI_FLASH_MISO
+    35  1   69  #GPIO_SPI_FLASH_CS
+
+uart    #UART resource allocation
+#  A:uart number;
+#  B:belongs to the core;
+#  C:function (to see iot_uart_api.h about uart type)
+#   A   B   C
+    2   1   0   #UART_PRINT
+    tx  28      #gpio number corresponding to uart TX signal
+
+    0   1   2   #UART_METER_PORT
+    tx  6       #gpio number corresponding to uart TX signal
+    rx  5       #gpio number corresponding to uart RX signal
+
+    5   1   1   #UART_CLI_PORT
+
+#spi     #SPI resource allocation, controlled by gpio resource now.
+#  A:spi number;
+#  B:belongs to the core;
+#  C:function
+#   A   B   C
+#   bbcpu use spi1 to connect external rf chip, fixed value used now.
+#   1   2   0   #SPI_PORT_TYPE_PYH_RF
+#   cs  9
+#   clk 12
+#   miso 10
+#   mosi 11
+
+ledc    #LEDC resource allocation
+#  A:ledc channel;
+#  B:belongs to the core;
+#  C:function
+#  ledout:The GPIO number corresponding to the output signal of LEDC
+#         (LEDC has only one signal, so it is unified ledOUT)
+#   A   B   C
+    0   1   0   #IOT_PLC_TX_LED
+    ledout  1
+
+    1   1   1   #IOT_PLC_RX_LED
+    ledout  0
+
+adc #ADC resource allocation
+#  A:adc channel;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about adc type)
+#   A   B   C
+    0   1   2   #ADC_PM_GND  (Temporary annotation)
+    1   1   0   #ADC_PM_12V  (Temporary annotation)
+    2   1   1   #ADC_PM_3V   (Temporary annotation: Shielded supercapacitor)
+
+#zc  # (PARTICULAR RESOURCE) Chip level zero crossing detection resource
+#      allocation, controlled by gpio resource now.
+# up_0: Zero-crossing detection rising edge input channel 0,
+#       which corresponds to phase A rising edge zero-crossing
+#       circuit by default
+#   up_0    68
+
+pa  # (PARTICULAR RESOURCE)
+    rx_en_0 2   #Phase A Enable receiving
+    tx_en_0 4   #Phase A Enable sending
+    gain_0  7   #Phase A gain control
+    gain_1  8   #Phase B gain control
+    gain_2  26  #Phase C gain control
+
+#================== 13.10.01.71(HW_VERSION_YP_STA_DM_V1) ================#
+# overview
+# add: 27 multi
+# gpio  function                gpio    function            gpio    function
+#   11  rf_spi_di               10      rf_spi_do           9       rf_spi_cs
+#   42  rf_mclk                 43      rf_fclk             39      pa_lic_ctr
+#   38  flash_spi_clk           37      flash_spi_mosi      36      flash_spi_miso
+#   35  flash_spi_cs            34      rf_clk              33      nc
+#   32  set(sta)                31      charge_en           30      nc
+#   29  sta_out                 28      uart2_tx            46      rf_agc_gain
+#   45  rf_enable               44      rf_txnrx            47      rf_dq0
+#   48  rf_dq1                  49      rf_dq2              27      multi
+#   1   tx_led                  0       rx_led              3       pa_testp(warning)
+#   2   pa_rx_en                4       pa_tx_en            7       pa_lan_gain_ctr0
+#   6   uart0_tx                5       uart0_rx            8       pa_lan_gain_ctr1
+#   26  pa_lan_gain_ctr2        50      rf_dq3              51      rf_dq4
+#   52  rf_dq5                  53      rf_dq6              54      rf_dq7
+#   55  rf_dq8                  56      rf_dq9              57      rf_dq10
+#   58  rf_dq11                 59      rf_pd               61      rf_channel_sw(io)
+#   62  rf_channel_sw(io)       64      m_sta(adc_gnd)      65      adc_12v
+#   66  adc_3.3v                67      d_rst(soft reset)   68      zc_a
+#   69  event                   12      rf_spi_clk
+rc_hdr
+    hw_ver      0x0D0A0147  #13.10.01.71
+    mode        1
+    d_hw_ver    0x00000000
+
+gpio
+#  A:gpio number;
+#  B:belongs to the core;
+#  C:function (to see iot_board_api.h about gpio type)
+#   A   B   C
+    27  1   127 #GPIO_MULTI_PULSE
\ No newline at end of file
diff --git a/tools/oem/oem.ini b/tools/oem/oem.ini
new file mode 100755
index 0000000..b77db59
--- /dev/null
+++ b/tools/oem/oem.ini
@@ -0,0 +1,21 @@
+general
+ bid 5
+
+uart0
+ tx 30
+ rx 31
+ meter
+
+uart1 cli
+ tx 34
+ rx 35
+ cli
+
+uart2 log
+ tx 8
+ rx 9
+ log
+
+led
+ tx 32
+ rx 33
diff --git a/tools/openocd/modify_jtag_register.patch b/tools/openocd/modify_jtag_register.patch
new file mode 100644
index 0000000..0050ff8
--- /dev/null
+++ b/tools/openocd/modify_jtag_register.patch
@@ -0,0 +1,40 @@
+diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c
+index c7bfe15..b1e9453 100755
+--- a/src/target/riscv/riscv-011.c
++++ b/src/target/riscv/riscv-011.c
+@@ -1437,6 +1437,7 @@ static int soft_reset_halt(struct target *target)
+ {
+ 	jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+ 	dbus_write(target, DMCONTROL, DMCONTROL_NDRESET);
++	//dbus_write(target, DMCONTROL, DMCONTROL_FULLRESET);
+ 	
+ 	return halt(target);
+ }
+@@ -2428,15 +2429,15 @@ static int setup_write_memory(struct target *target, uint32_t size)
+ {
+ 	switch (size) {
+ 		case 1:
+-			cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
++			cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 20));
+ 			cache_set32(target, 1, sb(S0, T0, 0));
+ 			break;
+ 		case 2:
+-			cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
++			cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 20));
+ 			cache_set32(target, 1, sh(S0, T0, 0));
+ 			break;
+ 		case 4:
+-			cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
++			cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 20));
+ 			cache_set32(target, 1, sw(S0, T0, 0));
+ 			break;
+ 		default:
+@@ -2507,7 +2508,7 @@ static int write_memory(struct target *target, uint32_t address,
+ 						goto error;
+ 				}
+ 
+-				scans_add_write32(scans, 4, value, true);
++				scans_add_write32(scans, 5, value, true);
+ 			}
+ 		}
+ 
diff --git a/tools/openocd/multi_task_debug_for_riscv_openocd.patch b/tools/openocd/multi_task_debug_for_riscv_openocd.patch
new file mode 100755
index 0000000..964a84e
--- /dev/null
+++ b/tools/openocd/multi_task_debug_for_riscv_openocd.patch
@@ -0,0 +1,441 @@
+diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c
+--- a/src/rtos/FreeRTOS.c
++++ b/src/rtos/FreeRTOS.c
+@@ -53,6 +53,22 @@ struct FreeRTOS_params {
+ };
+ 
+ static const struct FreeRTOS_params FreeRTOS_params_list[] = {
++#if 1
++	{
++	"riscv",			/* target_name */
++	4,						/* thread_count_width; */
++	4,						/* pointer_width; */
++	16,						/* list_next_offset; */
++	20,						/* list_width; */
++	8,						/* list_elem_next_offset; */
++	12,						/* list_elem_content_offset */
++	0,						/* thread_stack_offset; */
++	52,						/* thread_name_offset; */
++	&rtos_standard_RiscV32I_stacking,	/* stacking_info */
++	NULL,
++	NULL,
++	},
++#endif
+ 	{
+ 	"cortex_m",			/* target_name */
+ 	4,						/* thread_count_width; */
+@@ -553,3 +569,118 @@ static int FreeRTOS_create(struct target *target)
+ 	target->rtos->rtos_specific_params = (void *) &FreeRTOS_params_list[i];
+ 	return 0;
+ }
++
++int FreeRTOS_get_thread_reg(struct rtos *rtos, int64_t thread_id, char **hex_reg_list, int index)
++{
++	int retval, i;
++	const struct FreeRTOS_params *param= (const struct FreeRTOS_params *) rtos->rtos_specific_params;
++	int64_t stack_ptr = 0;
++	struct rtos_register_stacking *stack;
++	*hex_reg_list = NULL;
++	if (rtos == NULL)
++		return -1;
++
++	if (thread_id == 0)
++		return -2;
++
++	if (rtos->rtos_specific_params == NULL)
++		return -1;
++
++
++	/* Read the stack pointer */
++	retval = target_read_buffer(rtos->target,
++			thread_id + param->thread_stack_offset,
++			param->pointer_width,
++			(uint8_t *)&stack_ptr);
++	if (retval != ERROR_OK) {
++		LOG_ERROR("Error reading stack frame from FreeRTOS thread");
++		return retval;
++	}
++	LOG_DEBUG("FreeRTOS: Read stack pointer at 0x%" PRIx64 ", value 0x%" PRIx64 "\r\n",
++										thread_id + param->thread_stack_offset,
++										stack_ptr);
++
++	/* Check for armv7m with *enabled* FPU, i.e. a Cortex-M4F */
++	int cm4_fpu_enabled = 0;
++	struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target);
++	if (is_armv7m(armv7m_target)) {
++		if (armv7m_target->fp_feature == FPv4_SP) {
++			/* Found ARM v7m target which includes a FPU */
++			uint32_t cpacr;
++
++			retval = target_read_u32(rtos->target, FPU_CPACR, &cpacr);
++			if (retval != ERROR_OK) {
++				LOG_ERROR("Could not read CPACR register to check FPU state");
++				return -1;
++			}
++
++			/* Check if CP10 and CP11 are set to full access. */
++			if (cpacr & 0x00F00000) {
++				/* Found target with enabled FPU */
++				cm4_fpu_enabled = 1;
++			}
++		}
++	}
++
++	if (cm4_fpu_enabled == 1) {
++		/* Read the LR to decide between stacking with or without FPU */
++		uint32_t LR_svc = 0;
++		retval = target_read_buffer(rtos->target,
++				stack_ptr + 0x20,
++				param->pointer_width,
++				(uint8_t *)&LR_svc);
++		if (retval != ERROR_OK) {
++			LOG_OUTPUT("Error reading stack frame from FreeRTOS thread\r\n");
++			return retval;
++		}
++		if ((LR_svc & 0x10) == 0)
++		{
++			stack = (struct rtos_register_stacking*)param->stacking_info_cm4f_fpu;
++		}
++		else
++		{
++			stack = (struct rtos_register_stacking*)param->stacking_info_cm4f;
++		}
++	} 
++	else
++	{
++		stack = (struct rtos_register_stacking*)param->stacking_info_cm3;
++	}
++	
++	/* Read the stack */
++	uint8_t *stack_data = malloc(stack->stack_registers_size);
++	uint32_t address = stack_ptr;
++
++	if (stack->stack_growth_direction == 1)
++		address -= stack->stack_registers_size;
++	retval = target_read_buffer(rtos->target, address, stack->stack_registers_size, stack_data);
++	if (retval != ERROR_OK) {
++		free(stack_data);
++		LOG_ERROR("Error reading stack frame from thread");
++		return retval;
++	}
++
++	/* Remap */
++	if(index >= stack->num_output_registers)
++	{
++		if(index == 0x20)
++		{
++			index = 0x1;
++		}
++	}
++
++	if(NULL==(*hex_reg_list = malloc(stack->register_offsets[index].width_bits/4 + 1)))
++		return ERROR_FAIL;
++	
++	memset(*hex_reg_list, 0x0, stack->register_offsets[index].width_bits/4 + 1);
++	char *tmp_str_ptr = *hex_reg_list;
++
++	for (i= 0; i < stack->register_offsets[index].width_bits/8; i++)
++	{
++		tmp_str_ptr += sprintf(tmp_str_ptr, "%02x",
++						stack_data[stack->register_offsets[index].offset + i]);
++	}
++
++	free(stack_data);
++	return ERROR_OK;
++}
+\ No newline at end of file
+diff --git a/src/rtos/ThreadX.c b/src/rtos/ThreadX.c
+--- a/src/rtos/ThreadX.c
++++ b/src/rtos/ThreadX.c
+@@ -141,6 +141,20 @@ struct ThreadX_params {
+ };
+ 
+ static const struct ThreadX_params ThreadX_params_list[] = {
++#if 0
++	{
++	"riscv",				/* target_name */
++	4,							/* pointer_width; */
++	8,							/* thread_stack_offset; */
++	40,							/* thread_name_offset; */
++	48,							/* thread_state_offset; */
++	136,						/* thread_next_offset */
++	&rtos_standard_RiscV32I_stacking,	/* stacking_info */
++	1,							/* stacking_info_nb */
++	NULL,						/* fn_get_stacking_info */
++	NULL,						/* fn_is_thread_id_valid */
++	},
++#endif
+ 	{
+ 	"cortex_m",				/* target_name */
+ 	4,							/* pointer_width; */
+new mode 100755
+diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
+--- a/src/rtos/rtos.c
++++ b/src/rtos/rtos.c
+@@ -436,6 +436,8 @@ int rtos_get_gdb_reg_list(struct connection *connection)
+ 	return ERROR_FAIL;
+ }
+ 
++
++
+ int rtos_generic_stack_read(struct target *target,
+ 	const struct rtos_register_stacking *stacking,
+ 	int64_t stack_ptr,
+@@ -500,6 +502,35 @@ int rtos_generic_stack_read(struct target *target,
+ 	return ERROR_OK;
+ }
+ 
++int rtos_get_gdb_reg(struct connection *connection, int index)
++{
++	struct target *target = get_target_from_connection(connection);
++	int64_t current_threadid = target->rtos->current_threadid;
++	if ((target->rtos != NULL) && (current_threadid != -1) &&
++			(current_threadid != 0) &&
++			((current_threadid != target->rtos->current_thread) ||
++			(target->smp))) {	/* in smp several current thread are possible */
++		char *hex_reg_list = NULL;
++		
++
++		if(0 == strcmp(target->rtos->type->name, FreeRTOS_rtos.name) )
++		{
++			int FreeRTOS_get_thread_reg(struct rtos *rtos, int64_t thread_id, char **hex_reg_list, int index);
++			if(ERROR_OK!=FreeRTOS_get_thread_reg(target->rtos, current_threadid, &hex_reg_list, index))
++			{
++				return ERROR_FAIL;
++			}
++		}
++
++		if (hex_reg_list != NULL) {
++			gdb_put_packet(connection, hex_reg_list, strlen(hex_reg_list));
++			free(hex_reg_list);
++			return ERROR_OK;
++		}
++	}
++	return ERROR_FAIL;
++}
++
+ int rtos_try_next(struct target *target)
+ {
+ 	struct rtos *os = target->rtos;
+diff --git a/src/rtos/rtos.h b/src/rtos/rtos.h
+--- a/src/rtos/rtos.h
++++ b/src/rtos/rtos.h
+@@ -107,5 +107,5 @@ void rtos_free_threadlist(struct rtos *rtos);
+ int rtos_smp_init(struct target *target);
+ /*  function for handling symbol access */
+ int rtos_qsymbol(struct connection *connection, char const *packet, int packet_size);
+-
++int rtos_get_gdb_reg(struct connection *connection, int index);
+ #endif /* OPENOCD_RTOS_RTOS_H */
+diff --git a/src/rtos/rtos_standard_stackings.c b/src/rtos/rtos_standard_stackings.c
+--- a/src/rtos/rtos_standard_stackings.c
++++ b/src/rtos/rtos_standard_stackings.c
+@@ -23,6 +23,43 @@
+ #include "rtos.h"
+ #include "target/armv7m.h"
+ 
++#include "log.h"
++
++static const struct stack_register_offset rtos_standard_RiscV32I_stack_offsets[] = {
++	{ -1 , 32 },		/* X0 */
++	{ 0x00, 32 },		/* x1 ra  */
++	{ 0x04, 32 },		/* x2 sp  */
++	{ 0x08, 32 },		/* x3 gp  */
++	{ 0x0c, 32 },		/* x4 tp  */
++	{ 0x10, 32 },		/* x5 t0  */
++	{ 0x14, 32 },		/* x6 t1  */
++	{ 0x18, 32 },		/* x7 t2  */
++	{ 0x1c, 32 },		/* x8 s0/fp  */
++	{ 0x20, 32 },		/* x9 s1  */
++	{ 0x24, 32 },		/* x10 a0 */
++	{ 0x28, 32 },		/* x11 a1 */
++	{ 0x2c, 32 },		/* x12 a2 */
++	{ 0x30, 32 },		/* x13 a3  */
++	{ 0x34, 32 },		/* x14 a4  */
++	{ 0x38, 32 },		/* x15 a5  */
++	{ 0x3c, 32 },		/* x16 a6 */
++	{ 0x40, 32 },		/* x17 a7  */
++	{ 0x44, 32 },		/* x18 s2  */
++	{ 0x48, 32 },		/* x19 s3  */
++	{ 0x4c, 32 },		/* x20 s4  */
++	{ 0x50, 32 },		/* x21 s5  */
++	{ 0x54, 32 },		/* x22 s6  */
++	{ 0x58, 32 },		/* x23 s7  */
++	{ 0x5c, 32 },		/* x24 s8  */
++	{ 0x60, 32 },		/* x25 s9  */
++	{ 0x64, 32 },		/* x26 s10  */
++	{ 0x68, 32 },		/* x27 s11 */
++	{ 0x6c, 32 },		/* x28 t3 */
++	{ 0x70, 32 },		/* x29 t4 */
++	{ 0x74, 32 },		/* x30 t5  */
++	{ 0x78, 32 },		/* x31 t6  */
++	{ 0x80, 32 }		/* PC */
++};
+ static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
+ 	{ 0x20, 32 },		/* r0   */
+ 	{ 0x24, 32 },		/* r1   */
+@@ -225,10 +262,54 @@ static int64_t rtos_standard_Cortex_M3_stack_align(struct target *target,
+ 	int64_t stack_ptr)
+ {
+ 	const int XPSR_OFFSET = 0x3c;
++#if 0
++	int i, *ptr=(int*)stack_data;
++	for(i=0; i<17; i++)
++	{
++		LOG_INFO("X%02d = 0x%08x.", i, *ptr++);
++	}
++#endif
+ 	return rtos_Cortex_M_stack_align(target, stack_data, stacking,
+ 		stack_ptr, XPSR_OFFSET);
+ }
+ 
++int64_t rtos_standard_RiscV32I_stack_align(struct target *target,
++	const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
++	int64_t stack_ptr)
++{
++	int64_t new_stack_ptr;
++	int64_t aligned_stack_ptr;
++#if 0
++	int i, *ptr=(int*)stack_data;
++	for(i=1; i<32; i++)
++	{
++		LOG_INFO("X%02d = 0x%08x.", i, *ptr++);
++	}
++#endif
++	new_stack_ptr = stack_ptr - stacking->stack_growth_direction *
++		stacking->stack_registers_size;
++	
++	aligned_stack_ptr = new_stack_ptr & ~((int64_t)4 - 1);
++	if (aligned_stack_ptr != new_stack_ptr &&
++		stacking->stack_growth_direction == -1) {
++		/* If we have a downward growing stack, the simple alignment code
++		 * above results in a wrong result (since it rounds down to nearest
++		 * alignment).  We want to round up so add an extra align.
++		 */
++		aligned_stack_ptr += (int64_t)4;
++	}
++	//LOG_INFO("raw 0x%lx,before 0x%lx, now 0x%lx.", stack_ptr, new_stack_ptr, aligned_stack_ptr);
++	return aligned_stack_ptr;
++}
++
++const struct rtos_register_stacking rtos_standard_RiscV32I_stacking = {
++	0x84,					/* stack_registers_size */
++	-1,						/* stack_growth_direction */
++	32,						/* num_output_registers */
++	rtos_standard_RiscV32I_stack_align,	/* stack_alignment */
++	rtos_standard_RiscV32I_stack_offsets	/* register_offsets */
++};
++
+ const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
+ 	0x40,					/* stack_registers_size */
+ 	-1,						/* stack_growth_direction */
+diff --git a/src/rtos/rtos_standard_stackings.h b/src/rtos/rtos_standard_stackings.h
+--- a/src/rtos/rtos_standard_stackings.h
++++ b/src/rtos/rtos_standard_stackings.h
+@@ -24,7 +24,7 @@
+ #endif
+ 
+ #include "rtos.h"
+-
++extern const struct rtos_register_stacking rtos_standard_RiscV32I_stacking;
+ extern const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking;
+ extern const struct rtos_register_stacking rtos_standard_Cortex_M4F_stacking;
+ extern const struct rtos_register_stacking rtos_standard_Cortex_M4F_FPU_stacking;
+diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
+--- a/src/server/gdb_server.c
++++ b/src/server/gdb_server.c
+@@ -255,7 +255,7 @@ static int gdb_get_char_inner(struct connection *connection, int *next_char)
+ 
+ #ifdef _DEBUG_GDB_IO_
+ 	debug_buffer = strndup(gdb_con->buffer, gdb_con->buf_cnt);
+-	LOG_DEBUG("received '%s'", debug_buffer);
++	LOG_INFO("received '%s'", debug_buffer);
+ 	free(debug_buffer);
+ #endif
+ 
+@@ -267,7 +267,7 @@ static int gdb_get_char_inner(struct connection *connection, int *next_char)
+ 	else
+ 		connection->input_pending = 0;
+ #ifdef _DEBUG_GDB_IO_
+-	LOG_DEBUG("returned char '%c' (0x%2.2x)", *next_char, *next_char);
++	LOG_INFO("returned char '%c' (0x%2.2x)", *next_char, *next_char);
+ #endif
+ 
+ 	return retval;
+@@ -293,7 +293,7 @@ static inline int gdb_get_char_fast(struct connection *connection,
+ 			connection->input_pending = 0;
+ 
+ #ifdef _DEBUG_GDB_IO_
+-		LOG_DEBUG("returned char '%c' (0x%2.2x)", *next_char, *next_char);
++		LOG_INFO("returned char '%c' (0x%2.2x)", *next_char, *next_char);
+ #endif
+ 
+ 		return ERROR_OK;
+@@ -377,7 +377,7 @@ static int gdb_put_packet_inner(struct connection *connection,
+ 		if (reply == '$') {
+ 			/* fix a problem with some IAR tools */
+ 			gdb_putback_char(connection, reply);
+-			LOG_DEBUG("Unexpected start of new packet");
++			LOG_INFO("Unexpected start of new packet");
+ 			break;
+ 		}
+ 
+@@ -388,7 +388,7 @@ static int gdb_put_packet_inner(struct connection *connection,
+ 	while (1) {
+ #ifdef _DEBUG_GDB_IO_
+ 		debug_buffer = strndup(buffer, len);
+-		LOG_DEBUG("sending packet '$%s#%2.2x'", debug_buffer, my_checksum);
++		LOG_INFO("sending packet '$%s#%2.2x'", debug_buffer, my_checksum);
+ 		free(debug_buffer);
+ #endif
+ 
+@@ -608,7 +608,7 @@ static int gdb_get_packet_inner(struct connection *connection,
+ 				return retval;
+ 
+ #ifdef _DEBUG_GDB_IO_
+-			LOG_DEBUG("character: '%c'", character);
++			LOG_INFO("character: '%c'", character);
+ #endif
+ 
+ 			switch (character) {
+@@ -1140,7 +1140,7 @@ static int gdb_get_registers_packet(struct connection *connection,
+ 	int i;
+ 
+ #ifdef _DEBUG_GDB_IO_
+-	LOG_DEBUG("-");
++	LOG_INFO("-");
+ #endif
+ 
+ 	if ((target->rtos != NULL) && (ERROR_OK == rtos_get_gdb_reg_list(connection)))
+@@ -1180,7 +1180,7 @@ static int gdb_get_registers_packet(struct connection *connection,
+ 	{
+ 		char *reg_packet_p_debug;
+ 		reg_packet_p_debug = strndup(reg_packet, reg_packet_size);
+-		LOG_DEBUG("reg_packet: %s", reg_packet_p_debug);
++		LOG_INFO("reg_packet: %s", reg_packet_p_debug);
+ 		free(reg_packet_p_debug);
+ 	}
+ #endif
+@@ -1204,7 +1204,7 @@ static int gdb_set_registers_packet(struct connection *connection,
+ 	char const *packet_p;
+ 
+ #ifdef _DEBUG_GDB_IO_
+-	LOG_DEBUG("-");
++	LOG_INFO("-");
+ #endif
+ 
+ 	/* skip command character */
+@@ -1265,9 +1265,11 @@ static int gdb_get_register_packet(struct connection *connection,
+ 	int retval;
+ 
+ #ifdef _DEBUG_GDB_IO_
+-	LOG_DEBUG("-");
++	LOG_INFO("-");
+ #endif
+-
++	if ((target->rtos != NULL) && (ERROR_OK == rtos_get_gdb_reg(connection, reg_num)))
++		return ERROR_OK;
++	
+ 	retval = target_get_gdb_reg_list(target, &reg_list, &reg_list_size,
+ 			REG_CLASS_ALL);
+ 	if (retval != ERROR_OK)
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diff --git a/tools/pib/KL2AI01_PIB.bin b/tools/pib/KL2AI01_PIB.bin
new file mode 100644
index 0000000..fdbf59b
Binary files /dev/null and b/tools/pib/KL2AI01_PIB.bin differ
diff --git a/tools/pib/KL2CCO01_OEM.bin b/tools/pib/KL2CCO01_OEM.bin
new file mode 100644
index 0000000..f70523f
Binary files /dev/null and b/tools/pib/KL2CCO01_OEM.bin differ
diff --git a/tools/pib/KL2CCO01_PIB.bin b/tools/pib/KL2CCO01_PIB.bin
new file mode 100644
index 0000000..89accf6
Binary files /dev/null and b/tools/pib/KL2CCO01_PIB.bin differ
diff --git a/tools/pib/KL2STA01_OEM.bin b/tools/pib/KL2STA01_OEM.bin
new file mode 100644
index 0000000..6797958
Binary files /dev/null and b/tools/pib/KL2STA01_OEM.bin differ
diff --git a/tools/pib/KL2STA01_PIB.bin b/tools/pib/KL2STA01_PIB.bin
new file mode 100644
index 0000000..fdbf59b
Binary files /dev/null and b/tools/pib/KL2STA01_PIB.bin differ
diff --git a/tools/pib/LEDCCCO01_LP_PIB.bin b/tools/pib/LEDCCCO01_LP_PIB.bin
new file mode 100644
index 0000000..5242dc0
Binary files /dev/null and b/tools/pib/LEDCCCO01_LP_PIB.bin differ
diff --git a/tools/pib/LEDCCCO01_PIB.bin b/tools/pib/LEDCCCO01_PIB.bin
new file mode 100644
index 0000000..4cd3e4e
Binary files /dev/null and b/tools/pib/LEDCCCO01_PIB.bin differ
diff --git a/tools/pib/LEDCSTA01_LP_PIB.bin b/tools/pib/LEDCSTA01_LP_PIB.bin
new file mode 100644
index 0000000..db9114c
Binary files /dev/null and b/tools/pib/LEDCSTA01_LP_PIB.bin differ
diff --git a/tools/pib/LEDCSTA01_PIB.bin b/tools/pib/LEDCSTA01_PIB.bin
new file mode 100644
index 0000000..76def78
Binary files /dev/null and b/tools/pib/LEDCSTA01_PIB.bin differ
diff --git a/tools/pib/SMARTCCO01_PIB.bin b/tools/pib/SMARTCCO01_PIB.bin
new file mode 100644
index 0000000..6b873db
Binary files /dev/null and b/tools/pib/SMARTCCO01_PIB.bin differ
diff --git a/tools/pib/SMARTCCO_STA01_OEM.bin b/tools/pib/SMARTCCO_STA01_OEM.bin
new file mode 100644
index 0000000..04877bc
Binary files /dev/null and b/tools/pib/SMARTCCO_STA01_OEM.bin differ
diff --git a/tools/pib/SMARTSTA01_PIB.bin b/tools/pib/SMARTSTA01_PIB.bin
new file mode 100644
index 0000000..c300bd6
Binary files /dev/null and b/tools/pib/SMARTSTA01_PIB.bin differ
diff --git a/tools/pib/SOLRCCO01_PIB.bin b/tools/pib/SOLRCCO01_PIB.bin
new file mode 100755
index 0000000..aea25a4
Binary files /dev/null and b/tools/pib/SOLRCCO01_PIB.bin differ
diff --git a/tools/pib/SOLRSTA01_PIB.bin b/tools/pib/SOLRSTA01_PIB.bin
new file mode 100755
index 0000000..fdbf59b
Binary files /dev/null and b/tools/pib/SOLRSTA01_PIB.bin differ
diff --git a/tools/pib/TFMTI3C01_LP_PIB.bin b/tools/pib/TFMTI3C01_LP_PIB.bin
new file mode 100644
index 0000000..0852524
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diff --git a/tools/pib/TFMTI3C01_PIB.bin b/tools/pib/TFMTI3C01_PIB.bin
new file mode 100644
index 0000000..2b77170
Binary files /dev/null and b/tools/pib/TFMTI3C01_PIB.bin differ
diff --git a/tools/pib/WQRDCCO01_09_PIB.bin b/tools/pib/WQRDCCO01_09_PIB.bin
new file mode 100644
index 0000000..50c5621
Binary files /dev/null and b/tools/pib/WQRDCCO01_09_PIB.bin differ
diff --git a/tools/pib/WQRDCCO01_LP_PIB.bin b/tools/pib/WQRDCCO01_LP_PIB.bin
new file mode 100644
index 0000000..07f0eea
Binary files /dev/null and b/tools/pib/WQRDCCO01_LP_PIB.bin differ
diff --git a/tools/pib/WQRDCCO01_OEM.bin b/tools/pib/WQRDCCO01_OEM.bin
new file mode 100644
index 0000000..0d8d3a7
Binary files /dev/null and b/tools/pib/WQRDCCO01_OEM.bin differ
diff --git a/tools/pib/WQRDCCO01_PIB.bin b/tools/pib/WQRDCCO01_PIB.bin
new file mode 100644
index 0000000..3a577f3
Binary files /dev/null and b/tools/pib/WQRDCCO01_PIB.bin differ
diff --git a/tools/pib/WQRDIIC01_OEM.bin b/tools/pib/WQRDIIC01_OEM.bin
new file mode 100644
index 0000000..ff44ba7
Binary files /dev/null and b/tools/pib/WQRDIIC01_OEM.bin differ
diff --git a/tools/pib/WQRDIIC01_PIB.bin b/tools/pib/WQRDIIC01_PIB.bin
new file mode 100644
index 0000000..d7609a7
Binary files /dev/null and b/tools/pib/WQRDIIC01_PIB.bin differ
diff --git a/tools/pib/WQRDSTA01_LP_PIB.bin b/tools/pib/WQRDSTA01_LP_PIB.bin
new file mode 100644
index 0000000..11460d2
Binary files /dev/null and b/tools/pib/WQRDSTA01_LP_PIB.bin differ
diff --git a/tools/pib/WQRDSTA01_OEM.bin b/tools/pib/WQRDSTA01_OEM.bin
new file mode 100644
index 0000000..12a81dc
Binary files /dev/null and b/tools/pib/WQRDSTA01_OEM.bin differ
diff --git a/tools/pib/WQRDSTA01_PIB.bin b/tools/pib/WQRDSTA01_PIB.bin
new file mode 100644
index 0000000..d7609a7
Binary files /dev/null and b/tools/pib/WQRDSTA01_PIB.bin differ
diff --git a/tools/pibxml/GLDQCCO01_PIB.xml b/tools/pibxml/GLDQCCO01_PIB.xml
new file mode 100644
index 0000000..59e349e
--- /dev/null
+++ b/tools/pibxml/GLDQCCO01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_cco_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>208</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92210</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/GLDQIIC01_PIB.xml b/tools/pibxml/GLDQIIC01_PIB.xml
new file mode 100644
index 0000000..2dee148
--- /dev/null
+++ b/tools/pibxml/GLDQIIC01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>196</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92210</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/GLDQSTA01_PIB.xml b/tools/pibxml/GLDQSTA01_PIB.xml
new file mode 100644
index 0000000..eb6d415
--- /dev/null
+++ b/tools/pibxml/GLDQSTA01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>191</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>96</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92210</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/HTZDCCO01_09_LP_PIB.xml b/tools/pibxml/HTZDCCO01_09_LP_PIB.xml
new file mode 100644
index 0000000..ed98ca0
--- /dev/null
+++ b/tools/pibxml/HTZDCCO01_09_LP_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_cco_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>103</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>50</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92262</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/HTZDCCO01_09_PIB.xml b/tools/pibxml/HTZDCCO01_09_PIB.xml
new file mode 100644
index 0000000..fc4f930
--- /dev/null
+++ b/tools/pibxml/HTZDCCO01_09_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_cco_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>101</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92262</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/HTZDCCO01_LP_PIB.xml b/tools/pibxml/HTZDCCO01_LP_PIB.xml
new file mode 100644
index 0000000..acc7ab7
--- /dev/null
+++ b/tools/pibxml/HTZDCCO01_LP_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_cco_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>22</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>50</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92258</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/HTZDCCO01_PIB.xml b/tools/pibxml/HTZDCCO01_PIB.xml
new file mode 100644
index 0000000..038f160
--- /dev/null
+++ b/tools/pibxml/HTZDCCO01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_cco_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>20</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92258</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/HTZDIIC01_LP_PIB.xml b/tools/pibxml/HTZDIIC01_LP_PIB.xml
new file mode 100644
index 0000000..5cbffa5
--- /dev/null
+++ b/tools/pibxml/HTZDIIC01_LP_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>36</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>50</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92258</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/HTZDIIC01_PIB.xml b/tools/pibxml/HTZDIIC01_PIB.xml
new file mode 100644
index 0000000..a514640
--- /dev/null
+++ b/tools/pibxml/HTZDIIC01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>38</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92258</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/HTZDSTA01_LP_PIB.xml b/tools/pibxml/HTZDSTA01_LP_PIB.xml
new file mode 100644
index 0000000..5cbffa5
--- /dev/null
+++ b/tools/pibxml/HTZDSTA01_LP_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>36</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>50</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92258</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/HTZDSTA01_PIB.xml b/tools/pibxml/HTZDSTA01_PIB.xml
new file mode 100644
index 0000000..a514640
--- /dev/null
+++ b/tools/pibxml/HTZDSTA01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>38</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92258</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/HZBJCCO01_09_PIB.xml b/tools/pibxml/HZBJCCO01_09_PIB.xml
new file mode 100644
index 0000000..fefbac5
--- /dev/null
+++ b/tools/pibxml/HZBJCCO01_09_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_cco_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>53</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92262</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/HZBJCCO01_PIB.xml b/tools/pibxml/HZBJCCO01_PIB.xml
new file mode 100644
index 0000000..9f636fa
--- /dev/null
+++ b/tools/pibxml/HZBJCCO01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_cco_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>68</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92258</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/HZBJIIC01_PIB.xml b/tools/pibxml/HZBJIIC01_PIB.xml
new file mode 100644
index 0000000..bf46a8f
--- /dev/null
+++ b/tools/pibxml/HZBJIIC01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>118</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92258</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/HZBJSTA01_PIB.xml b/tools/pibxml/HZBJSTA01_PIB.xml
new file mode 100644
index 0000000..bf46a8f
--- /dev/null
+++ b/tools/pibxml/HZBJSTA01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>118</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92258</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/JSMTCCO01_09_LP_PIB.xml b/tools/pibxml/JSMTCCO01_09_LP_PIB.xml
new file mode 100644
index 0000000..f1d0e13
--- /dev/null
+++ b/tools/pibxml/JSMTCCO01_09_LP_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_cco_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>48</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>50</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>67201126</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/JSMTCCO01_09_PIB.xml b/tools/pibxml/JSMTCCO01_09_PIB.xml
new file mode 100644
index 0000000..d22cd00
--- /dev/null
+++ b/tools/pibxml/JSMTCCO01_09_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_cco_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>50</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>67201126</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/JSMTCCO01_LP_PIB.xml b/tools/pibxml/JSMTCCO01_LP_PIB.xml
new file mode 100644
index 0000000..eb72c1e
--- /dev/null
+++ b/tools/pibxml/JSMTCCO01_LP_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_cco_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>11</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>50</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92274</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/JSMTCCO01_PIB.xml b/tools/pibxml/JSMTCCO01_PIB.xml
new file mode 100644
index 0000000..ecd8401
--- /dev/null
+++ b/tools/pibxml/JSMTCCO01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_cco_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>9</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92274</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/JSMTIIC01_LP_PIB.xml b/tools/pibxml/JSMTIIC01_LP_PIB.xml
new file mode 100644
index 0000000..5cbffa5
--- /dev/null
+++ b/tools/pibxml/JSMTIIC01_LP_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>36</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>50</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92258</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/JSMTIIC01_PIB.xml b/tools/pibxml/JSMTIIC01_PIB.xml
new file mode 100644
index 0000000..a514640
--- /dev/null
+++ b/tools/pibxml/JSMTIIC01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>38</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92258</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/JSMTSTA01_LP_PIB.xml b/tools/pibxml/JSMTSTA01_LP_PIB.xml
new file mode 100644
index 0000000..5cbffa5
--- /dev/null
+++ b/tools/pibxml/JSMTSTA01_LP_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>36</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>50</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92258</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/JSMTSTA01_PIB.xml b/tools/pibxml/JSMTSTA01_PIB.xml
new file mode 100644
index 0000000..a514640
--- /dev/null
+++ b/tools/pibxml/JSMTSTA01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>38</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92258</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/PIBBuilder.exe b/tools/pibxml/PIBBuilder.exe
new file mode 100644
index 0000000..4bfd194
Binary files /dev/null and b/tools/pibxml/PIBBuilder.exe differ
diff --git a/tools/pibxml/PIBBuilder.pdb b/tools/pibxml/PIBBuilder.pdb
new file mode 100644
index 0000000..9fa7d19
Binary files /dev/null and b/tools/pibxml/PIBBuilder.pdb differ
diff --git a/tools/pibxml/SMARTCCO01_PIB.xml b/tools/pibxml/SMARTCCO01_PIB.xml
new file mode 100644
index 0000000..59e349e
--- /dev/null
+++ b/tools/pibxml/SMARTCCO01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_cco_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>208</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92210</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/SMARTSTA01_PIB.xml b/tools/pibxml/SMARTSTA01_PIB.xml
new file mode 100644
index 0000000..156e972
--- /dev/null
+++ b/tools/pibxml/SMARTSTA01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>226</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92210</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/WQRDCCO01_09_PIB.xml b/tools/pibxml/WQRDCCO01_09_PIB.xml
new file mode 100644
index 0000000..5afdc33
--- /dev/null
+++ b/tools/pibxml/WQRDCCO01_09_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_cco_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>16</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92198</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/WQRDCCO01_PIB.xml b/tools/pibxml/WQRDCCO01_PIB.xml
new file mode 100644
index 0000000..131e552
--- /dev/null
+++ b/tools/pibxml/WQRDCCO01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_cco_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>97</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92194</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/WQRDIIC01_PIB.xml b/tools/pibxml/WQRDIIC01_PIB.xml
new file mode 100644
index 0000000..8ac3026
--- /dev/null
+++ b/tools/pibxml/WQRDIIC01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>83</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92194</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/WQRDSTA01_PIB.xml b/tools/pibxml/WQRDSTA01_PIB.xml
new file mode 100644
index 0000000..8ac3026
--- /dev/null
+++ b/tools/pibxml/WQRDSTA01_PIB.xml
@@ -0,0 +1,168 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<Root name="PIBTool.iot_pib_r_sta_t" size="296">
+  <item name="iot_pib_hdr_t.piblen">
+    <type>System.UInt16</type>
+    <value>296</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibcrc8">
+    <type>System.Byte</type>
+    <value>83</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pibtype">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_minor_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_hdr_t.pib_major_ver">
+    <type>System.UInt16</type>
+    <value>1</value>
+    <size>2</size>
+  </item>
+  <item name="iot_pib_r_board_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>128</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cli_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_mac_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>32</size>
+    <value>0000000000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_reduce_db">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_psd_fix_db">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.iot_pib_r_halphy_cfg_info.tx_pwr_ctl_ena">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_halphy_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>29</size>
+    <value>0000000000000000000000000000000000000000000000000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.cvg_sta_feature">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_sta_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>6</size>
+    <value>000000000000</value>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.dev_type">
+    <type>System.Byte</type>
+    <value>2</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.freq_band_id">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allow_chan_eval">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.allowed_cco_tf_sr">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.proxy_select_dur">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.assoc_retry_int">
+    <type>System.UInt32</type>
+    <value>10000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.fb_chg_delay">
+    <type>System.UInt32</type>
+    <value>60000</value>
+    <size>4</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.iot_pib_r_cvg_real_cfg_t.iot_pib_r_cvg_cco_cfg_t.min_bc_period">
+    <type>System.Byte</type>
+    <value>1</value>
+    <size>1</size>
+  </item>
+  <item name="iot_pib_r_cvg_cfg_t.reserved">
+    <type>System.Byte[]</type>
+    <size>10</size>
+    <value>00000000000000000000</value>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>92194</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_cco_app_pib_ro_t.iot_sg_cco_cmn_cfg_t.oem_mft_code">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>0</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>131</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>3</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.fr">
+    <type>System.Int32</type>
+    <value>3</value>
+    <size>4</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.iot_sg_sta_app_pib_ro_t.iot_sg_sta_cmn_cfg_t.drv_id">
+    <type>System.Byte</type>
+    <value>4</value>
+    <size>1</size>
+  </item>
+  <item name="iot_sg_app_pib_ro_t.reserved">
+    <type>System.Byte[]</type>
+    <size>12</size>
+    <value>000000000000000000000000</value>
+  </item>
+</Root>
\ No newline at end of file
diff --git a/tools/pibxml/xml_generate_pib.py b/tools/pibxml/xml_generate_pib.py
new file mode 100644
index 0000000..ef53e5e
--- /dev/null
+++ b/tools/pibxml/xml_generate_pib.py
@@ -0,0 +1,130 @@
+#!/usr/bin/env python
+# -*- coding: UTF-8 -*-
+__metaclass__ = type
+
+import binascii
+import os
+import re
+import sys
+import struct
+import xml.etree.ElementTree as xml_et
+
+
+DictCtypesFmt = {
+    "byte": "B", "int8": "b", "uint8": "b",
+    "uint16": "H", "int16": "h",
+    "uint32": "I", "int32": "i",
+    "uint64": "L", "int64": "l"
+}
+
+
+######################################################################################################################
+#                                                                                                                    #
+#                                               Functions Initialization                                             #
+#                                                                                                                    #
+######################################################################################################################
+def xml_info_parse(f_xml, lname, child_lab_1, child_lab_2, child_lab_3):
+    xml_data_info_list = []
+    xml_value_list, xml_size_list, xml_type_list = [], [], []
+    s_fmt = None
+    tree = xml_et.parse(f_xml)
+    root = tree.getroot()
+
+    root_attrib_dict = root.attrib
+    xml_info_total_size = int(root_attrib_dict[child_lab_2])
+
+    for item in root.findall(lname):
+        i_value = item.find(child_lab_1).text
+        i_size = item.find(child_lab_2).text
+        i_type = item.find(child_lab_3).text
+        xml_value_list.append(i_value)
+        xml_size_list.append(int(i_size))
+        xml_type_list.append(i_type)
+
+    if len(xml_size_list) == len(xml_value_list) == len(xml_type_list):
+        if sum(xml_size_list) == xml_info_total_size:
+            for i in range(len(xml_type_list)):
+                hex_value_str = ""
+                xml_type_str = xml_type_list[i].lower()
+                m_type = re.search(r"system\.(\w+)", xml_type_str)
+                if m_type:
+                    ctype_str = m_type.group(1)
+                    if ctype_str in DictCtypesFmt.keys():
+                        s_fmt = DictCtypesFmt[ctype_str]
+                    else:
+                        print ("Ctype String Not Match Any Format in Dict, Please check...")
+                        return 0
+                if xml_type_list[i].find("[]") >= 0:  # hex
+                    hex_value_str += xml_value_list[i]
+                else:  # decimal
+                    hex_value_str = struct.pack('<' + s_fmt, int(xml_value_list[i])).encode("hex")
+                xml_data_info_list.append(hex_value_str)
+            return xml_data_info_list
+        else:
+            print ("Error: XML Data Size mismatched...\r\n")
+            return 0
+    else:
+        print ("Erro: XML Lable size, value count mismatched...\r\n")
+        return 0
+
+
+def crc32_calculate(xml_crc32_info):
+    crc32_byte_dec_value = binascii.crc32(xml_crc32_info.decode("hex"))
+    crc32_byte_hex_str = struct.pack('<i', crc32_byte_dec_value).encode("hex")  # little endian
+    crc32_byte_str = crc32_byte_hex_str[-2:]  # crc 32 >> 24
+
+    return crc32_byte_str
+
+
+######################################################################################################################
+#                                                                                                                    #
+#                                                     Main Entrance                                                  #
+#                                                                                                                    #
+######################################################################################################################
+if __name__ == '__main__':
+    xml_file, file_name_str, xml_file_list = '', '', []
+    cmd_parameters = sys.argv
+    if 2 <= len(cmd_parameters):
+        xml_file = sys.argv[1]
+
+    if xml_file:
+        xml_file_list.append(xml_file)
+    else:
+        all_dir_list = os.listdir(os.getcwd())
+        for each_file in all_dir_list:
+            if each_file.find(r".xml") > 0:
+                xml_file_list.append(each_file)
+
+    for each_xml_file in xml_file_list:
+        if each_xml_file.find("\\") > 0:
+            xml_file_name = os.path.basename(each_xml_file)
+        else:
+            xml_file_name = each_xml_file
+        m_name = re.search(r"(\w+)\.xml", xml_file_name)
+        if m_name:
+            file_name_str = m_name.group(1)
+        else:
+            print ("Error: Please input .xml file...Reload...")
+            sys.exit()
+
+        bin_file = file_name_str + r".bin"
+        label_name = "item"
+        child_label_1, child_label_2, child_label_3 = "value", "size", "type"
+        xml_parse_info_list = []
+
+        xml_parse_info_list = xml_info_parse(each_xml_file, label_name, child_label_1, child_label_2, child_label_3)
+        xml_parse_info_str = "".join(xml_parse_info_list)
+        xml_crc32_str = xml_parse_info_str[3 * 2:]  # ignore first 3 bytes
+
+        crc32_info = crc32_calculate(xml_crc32_str)
+        print ("Crc byte : %s" % crc32_info)
+        xml_parse_info_list[1] = crc32_info
+
+        xml_restruct_info_str = "".join(xml_parse_info_list)
+        wf = open(bin_file, 'wb')
+        wf.write(binascii.a2b_hex(xml_restruct_info_str))
+        wf.close()
+
+        print ("Pib file %s generated complete, please check...\r\n" % each_xml_file)
+
+    raw_input("Press <Enter> to Exit...")
diff --git a/tools/ram/smoke/kl_ram.bin b/tools/ram/smoke/kl_ram.bin
new file mode 100755
index 0000000..7b05179
Binary files /dev/null and b/tools/ram/smoke/kl_ram.bin differ
diff --git a/tools/ram/smoke/kl_ram.md5 b/tools/ram/smoke/kl_ram.md5
new file mode 100644
index 0000000..63e196b
--- /dev/null
+++ b/tools/ram/smoke/kl_ram.md5
@@ -0,0 +1 @@
+42301bef20ea7305723447373ca48273
diff --git a/tools/rom_img/make_ld.sh b/tools/rom_img/make_ld.sh
new file mode 100755
index 0000000..7efcff2
--- /dev/null
+++ b/tools/rom_img/make_ld.sh
@@ -0,0 +1,67 @@
+#!/bin/bash
+
+# This script is intended for use with separately linked ROM and RAM.
+# It creates EITHER a linker script that satisfies references made by RAM
+# applications to ROM symbols OR a linker script that forces symbols to
+# be included in a ROM image.
+#
+# The option "--addrs" causes the RAM linkage script to be generated
+# and the option "--externs" causes the ROM linkage script to be generated.
+#
+# Example usage:
+#     make_ld.sh --addrs sw.rom.out rom.symbols > rom.addrs.ld
+#     make_ld.sh --externs rom.symbols > rom.externs.ld
+
+KUNLUN_NM=riscv64-unknown-elf-nm
+
+eval NM=$KUNLUN_NM
+
+Usage() {
+    echo Usage:
+    echo $progname '{--addrs ROM_ELF_Image | --externs} symbol_file'
+    exit 1
+}
+
+Provide() {
+    addr=0x`$NM $image_file | grep " $1$" | cut -d ' ' -f 1`
+    if [ "$addr" != "0x" ]
+    then
+    	echo PROVIDE \( $1 = $addr \)\;
+    fi
+}
+
+Extern() {
+    echo EXTERN \( $1 \)\;
+}
+
+progname=$0
+script_choice=$1
+
+if [ "$script_choice" == "--addrs" ]
+then
+    action=Provide
+    image_file=$2
+    if [ ! -r "$image_file" ]
+    then
+        echo "Cannot read ELF image: $image_file"
+        Usage
+    fi
+    symbol_file=$3
+elif [ "$script_choice" == "--externs" ]
+then
+    action=Extern
+    symbol_file=$2
+else
+    Usage
+fi
+
+if [ ! -r "$symbol_file" ]
+then
+    echo "Cannot read symbol list from: $symbol_file"
+    Usage
+fi
+
+for i in `cat $symbol_file`
+do
+    $action $i
+done
diff --git a/tools/rom_img/riscv/kl_rom.out b/tools/rom_img/riscv/kl_rom.out
new file mode 100644
index 0000000..7894792
Binary files /dev/null and b/tools/rom_img/riscv/kl_rom.out differ
diff --git a/tools/rom_img/riscv/rom_symbol b/tools/rom_img/riscv/rom_symbol
new file mode 100644
index 0000000..889087f
--- /dev/null
+++ b/tools/rom_img/riscv/rom_symbol
@@ -0,0 +1,64 @@
+_gp
+_end
+iot_indir_tbl
+crypto_stream_chacha20_ref_implementation
+log_ctxt
+memset
+memcpy
+memcmp
+iot_sprintf
+iot_printf
+format_str_v
+mbedtls_sha512
+mbedtls_sha256
+mbedtls_sha512
+mbedtls_md_info_from_type
+mbedtls_md_hmac
+mbedtls_entropy_init
+mbedtls_ctr_drbg_init
+mbedtls_pk_init
+mbedtls_pk_free
+mbedtls_entropy_func
+mbedtls_ctr_drbg_random
+mbedtls_pk_sign
+mbedtls_pk_verify
+mbedtls_pk_info_from_type
+mbedtls_pk_setup
+mbedtls_fast_ec_info_from_type
+mbedtls_fast_ec_setup
+mbedtls_rsa_gen_key
+mbedtls_rsa_free
+mbedtls_ecdh_free
+mbedtls_entropy_free
+mbedtls_ctr_drbg_free
+mbedtls_ctr_drbg_seed
+mbedtls_ecp_group_copy
+mbedtls_ecp_copy
+mbedtls_mpi_copy
+mbedtls_ecdh_calc_secret
+mbedtls_fast_ec_get_shared_len
+mbedtls_fast_ec_compute_shared
+mbedtls_pk_parse_key
+mbedtls_pk_parse_public_key
+mbedtls_kdf_info_from_type
+mbedtls_kdf
+mbedtls_ecp_gen_key
+mbedtls_pk_write_pubkey_der
+mbedtls_pk_write_key_der
+mbedtls_fast_ec_gen_key
+mbedtls_asn1_get_tag
+mbedtls_asn1_get_bitstring
+mbedtls_ecp_group_load
+mbedtls_mpi_read_binary
+mbedtls_ecp_keypair_free
+mbedtls_mpi_init
+mbedtls_mpi_grow
+mbedtls_mpi_free
+mbedtls_mpi_lset
+mbedtls_mpi_cmp_int
+mbedtls_mpi_div_mpi
+mbedtls_mpi_add_mpi
+mbedtls_mpi_cmp_int
+mbedtls_mpi_sub_mpi
+mbedtls_mpi_cmp_mpi
+mbedtls_memory_buffer_alloc_init
diff --git a/tools/rom_img/riscv/sp_symbol b/tools/rom_img/riscv/sp_symbol
new file mode 100644
index 0000000..b07b1c0
--- /dev/null
+++ b/tools/rom_img/riscv/sp_symbol
@@ -0,0 +1,3 @@
+_gp
+g_phy_cpu_share_ctxt
+g_cpu1_state
diff --git a/tools/rom_img/riscv2/kl_pmu_rom.out b/tools/rom_img/riscv2/kl_pmu_rom.out
new file mode 100755
index 0000000..2c71273
Binary files /dev/null and b/tools/rom_img/riscv2/kl_pmu_rom.out differ
diff --git a/tools/rom_img/riscv2/kl_rom.out b/tools/rom_img/riscv2/kl_rom.out
new file mode 100755
index 0000000..288bcb0
Binary files /dev/null and b/tools/rom_img/riscv2/kl_rom.out differ
diff --git a/tools/rom_img/riscv2/pmu_rom_gen.sh b/tools/rom_img/riscv2/pmu_rom_gen.sh
new file mode 100755
index 0000000..c331038
--- /dev/null
+++ b/tools/rom_img/riscv2/pmu_rom_gen.sh
@@ -0,0 +1,14 @@
+#!/bin/bash
+
+CUR_DIR=$(cd `dirname $0`; pwd)
+TOP_DIR=$CUR_DIR"/../../../"
+rm $CUR_DIR"/kl_pmu_rom.out"
+rm $CUR_DIR"/pmu_rom.addrs.ld"
+cp $TOP_DIR"rom/riscv2/pmu_rom/.output/lib/kl_pmu_rom.out" $CUR_DIR
+../make_ld.sh --addrs $CUR_DIR"/kl_pmu_rom.out" pmu_rom_symbol > $CUR_DIR"/pmu_rom.addrs.ld"
+
+#cp $CUR_DIR/"/rom.addrs.ld" $TOP_DIR"/startup/ldscripts/riscv2"
+
+elf2hex 2415927296 4 1024 kl_pmu_rom.out > pmu_rom_code_0.hex
+
+./hex2bin pmu_rom_code_0.hex pmu_rom_code_0
diff --git a/tools/rom_img/riscv2/pmu_rom_symbol b/tools/rom_img/riscv2/pmu_rom_symbol
new file mode 100644
index 0000000..bd38ea0
--- /dev/null
+++ b/tools/rom_img/riscv2/pmu_rom_symbol
@@ -0,0 +1 @@
+_gp
diff --git a/tools/rom_img/riscv2/rom_gen.sh b/tools/rom_img/riscv2/rom_gen.sh
new file mode 100755
index 0000000..4259666
--- /dev/null
+++ b/tools/rom_img/riscv2/rom_gen.sh
@@ -0,0 +1,24 @@
+#!/bin/bash
+
+CUR_DIR=$(cd `dirname $0`; pwd)
+TOP_DIR=$CUR_DIR"/../../../"
+rm $CUR_DIR"/kl_rom.out"
+rm $CUR_DIR"/rom.addrs.ld"
+cp $TOP_DIR"rom/riscv2/rom/.output/lib/kl_rom.out" $CUR_DIR
+../make_ld.sh --addrs $CUR_DIR"/kl_rom.out" rom_symbol > $CUR_DIR"/rom.addrs.ld"
+
+cp $CUR_DIR/"/rom.addrs.ld" $TOP_DIR"/startup/ldscripts/riscv2"
+
+elf2hex 196608 4 8192 kl_rom.out > rom_code_0.hex
+elf2hex 229376 4 8192 kl_rom.out > rom_code_1.hex
+elf2hex 262144 4 8192 kl_rom.out > rom_code_2.hex
+elf2hex 294912 4 8192 kl_rom.out > rom_code_3.hex
+elf2hex 327680 4 8192 kl_rom.out > rom_code_4.hex
+elf2hex 360448 4 8192 kl_rom.out > rom_code_5.hex
+
+./hex2bin rom_code_0.hex rom_code_0
+./hex2bin rom_code_1.hex rom_code_1
+./hex2bin rom_code_2.hex rom_code_2
+./hex2bin rom_code_3.hex rom_code_3
+./hex2bin rom_code_4.hex rom_code_4
+./hex2bin rom_code_5.hex rom_code_5
diff --git a/tools/rom_img/riscv2/rom_symbol b/tools/rom_img/riscv2/rom_symbol
new file mode 100644
index 0000000..277c819
--- /dev/null
+++ b/tools/rom_img/riscv2/rom_symbol
@@ -0,0 +1,503 @@
+_gp
+_end
+iot_indir_tbl
+log_ctxt
+memset
+memcpy
+memcmp
+iot_sprintf
+iot_printf
+mbedtls_rsa_rsaes_oaep_encrypt                                         
+mbedtls_cipher_reset                                                   
+mbedtls_fast_ec_get_name                                               
+crypto_sign_ed25519_ref10_fe_sq                                        
+mbedtls_ctr_drbg_init                                                  
+crypto_sign_ed25519_ref10_ge_tobytes                                   
+strcpy                                                                 
+mbedtls_pkcs12_derivation                                              
+crypto_aead_chacha20poly1305_decrypt                                   
+mbedtls_ctr_drbg_set_prediction_resistance                             
+SFC_OPR_SET                                                            
+mbedtls_mpi_grow                                                       
+mbedtls_md_starts                                                      
+mbedtls_asn1_get_bitstring_null                                        
+crypto_aead_xchacha20poly1305_ietf_encrypt_detached                    
+mbedtls_ecp_point_init                                                 
+mbedtls_oid_get_oid_by_kdf_alg                                         
+mbedtls_fast_ec_get_shared_len                                         
+crypto_sign_ed25519_ref10_ge_p2_dbl                                    
+mbedtls_rsa_free                                                       
+crypto_sign_ed25519_ref10_fe_invert                                    
+mbedtls_hardware_poll                                                  
+crypto_onetimeauth_poly1305_update                                     
+mbedtls_asn1_write_tag                                                 
+mbedtls_ctr_drbg_update                                                
+mbedtls_ecdh_init                                                      
+mbedtls_gcm_init                                                       
+mbedtls_asn1_get_len                                                   
+mbedtls_ecp_point_cmp                                                  
+CRC32_Update                                                           
+mbedtls_dhm_read_params                                                
+sFlashPageRead                                                         
+mbedtls_strerror                                                       
+crypto_aead_xchacha20poly1305_ietf_encrypt                             
+crypto_aead_chacha20poly1305_ietf_abytes                               
+mbedtls_mpi_write_binary                                               
+mbedtls_ecp_keypair_free                                               
+mbedtls_ecp_muladd                                                     
+crypto_sign_ed25519_ref10_fe_1                                         
+mbedtls_ed25519_pubkey_to_curve25519                                   
+mbedtls_ed25519_verify                                                 
+mbedtls_asn1_get_alg                                                   
+mbedtls_ecdsa_sign                                                     
+mbedtls_mpi_sub_int                                                    
+mbedtls_kdf2                                                           
+mbedtls_asn1_write_ia5_string                                          
+memmove                                                                
+mbedtls_asn1_get_bool                                                  
+crypto_aead_xchacha20poly1305_ietf_decrypt                             
+mbedtls_ecies_write_hmac                                               
+mbedtls_version_check_feature                                          
+mbedtls_aes_free                                                       
+mbedtls_sha256_init                                                    
+crypto_aead_chacha20poly1305_ietf_decrypt_detached                     
+mbedtls_dhm_make_public                                                
+mbedtls_kdf_info_from_type                                             
+mbedtls_ecp_copy                                                       
+crypto_stream_chacha20_keygen                                          
+mbedtls_hmac_drbg_seed_buf                                             
+mbedtls_mpi_shrink                                                     
+crypto_verify_64                                                       
+crypto_sign_ed25519_ref10_ge_p3_to_cached                              
+mbedtls_fast_ec_info_from_type                                         
+mbedtls_cipher_auth_encrypt                                            
+crypto_sign_ed25519_ref10_ge_p3_tobytes                                
+mbedtls_kdf_info_from_string                                           
+mbedtls_sha1_finish                                                    
+crypto_aead_xchacha20poly1305_ietf_abytes                              
+mbedtls_rsa_rsaes_oaep_decrypt                                         
+mbedtls_rsa_pkcs1_decrypt                                              
+mbedtls_pk_can_do                                                      
+mbedtls_sha256                                                         
+mbedtls_rsa_rsassa_pss_verify                                          
+FLASH_WRITE_ENABLE                                                     
+mbedtls_rsa_check_privkey                                              
+mbedtls_pk_get_type                                                    
+romUartBoot                                                            
+crypto_stream_chacha20_xor                                             
+mbedtls_mpi_read_string                                                
+mbedtls_ctr_drbg_free                                                  
+mbedtls_ctr_drbg_random_with_add                                       
+mbedtls_asn1_write_octet_string                                        
+sha256_init                                                            
+mbedtls_curve25519_sign                                                
+mbedtls_md                                                             
+mbedtls_ecp_group_copy                                                 
+iot_printf                                                             
+mbedtls_ecdh_gen_public                                                
+mbedtls_asn1_get_tag                                                   
+mbedtls_ecdsa_verify                                                   
+mbedtls_ctr_drbg_set_entropy_len                                       
+_crypto_onetimeauth_poly1305_pick_best_implementation                  
+romAHBInit                                                             
+mbedtls_fast_ec_compute_pub                                            
+crypto_sign_ed25519_ref10_fe_pow22523                                  
+mbedtls_sha256_finish                                                  
+mbedtls_mpi_shift_r                                                    
+mbedtls_sha512_clone                                                   
+crypto_sign_ed25519_ref10_ge_p2_0                                      
+mbedtls_ctr_drbg_random                                                
+mbedtls_ed25519_sign                                                   
+mbedtls_pk_write_pubkey                                                
+mbedtls_mpi_gen_prime                                                  
+mbedtls_ecp_curve_info_from_grp_id                                     
+mbedtls_asn1_write_algorithm_identifier_no_params                      
+mbedtls_mpi_get_bit                                                    
+mbedtls_ecies_decrypt                                                  
+mbedtls_mpi_read_binary                                                
+crypto_core_hchacha20_outputbytes                                                                                               
+mbedtls_asn1_write_int                                                 
+mbedtls_sha1_init                                                      
+crypto_stream_chacha20_ietf_keygen                                     
+mbedtls_cipher_info_from_values                                        
+mbedtls_asn1_get_int                                                   
+mbedtls_ctr_drbg_seed_entropy_len                                      
+mbedtls_fast_ec_copy                                                   
+crypto_onetimeauth_poly1305_verify                                     
+mbedtls_ecies_write_kdf                                                
+memcpy                                                                 
+sUartPutString                                                         
+mbedtls_sha1_starts                                                    
+mbedtls_sha1_process                                                   
+mbedtls_cipher_info_from_string                                        
+crypto_sign_ed25519_ref10_ge_scalarmult_base                           
+crypto_sign_ed25519_ref10_fe_frombytes                                 
+mbedtls_hmac_drbg_random_with_add                                      
+mbedtls_fast_ec_get_type                                               
+crypto_aead_chacha20poly1305_keybytes                                  
+crypto_sign_ed25519_ref10_fe_isnonzero                                 
+crypto_sign_ed25519_ref10_fe_mul                                       
+mbedtls_platform_set_printf                                            
+mbedtls_ecp_curve_info_from_name                                       
+mbedtls_aes_setkey_dec                                                 
+mbedtls_ecp_group_free                                                 
+crypto_onetimeauth_poly1305_statebytes                                 
+mbedtls_kdf_list                                                       
+mbedtls_rsa_copy                                                       
+mbedtls_version_get_string_full                                        
+mbedtls_rsa_rsaes_pkcs1_v15_encrypt                                    
+mbedtls_ecies_read_hmac                                                
+mbedtls_asn1_get_alg_null                                              
+crypto_sign_ed25519_ref10_ge_add                                       
+mbedtls_sha256_starts                                                  
+crypto_aead_chacha20poly1305_nsecbytes                                 
+mbedtls_sha256_update                                                  
+mbedtls_mpi_bitlen                                                     
+mbedtls_ecdsa_free                                                     
+mbedtls_rsa_check_pubkey                                               
+mbedtls_sha512_free                                                    
+mbedtls_md5_update                                                     
+mbedtls_oid_get_md_alg                                                 
+mbedtls_ecp_check_pub_priv                                             
+mbedtls_mpi_mul_mpi                                                    
+FLASH_SECTOR_ERASE                                                     
+mbedtls_kdf                                                            
+mbedtls_ecp_set_zero                                                   
+mbedtls_dhm_free                                                       
+mbedtls_cipher_auth_decrypt                                            
+crypto_sign_ed25519_ref10_fe_0                                         
+crypto_core_hchacha20_keybytes                                         
+crypto_sign_ed25519_ref10_ge_p3_to_p2                                  
+mbedtls_mpi_init                                                       
+mbedtls_mpi_lsb                                                        
+mbedtls_pkcs12_pbe                                                     
+randombytes_buf                                                        
+mbedtls_oid_get_oid_by_sig_alg                                         
+mbedtls_cipher_free                                                    
+mbedtls_memory_buffer_alloc_free                                       
+mbedtls_curve25519_verify                                              
+iot_sprintf                                                            
+mbedtls_pk_parse_key                                                   
+mbedtls_oid_get_numeric_string                                         
+crypto_core_hchacha20_constbytes                                       
+mbedtls_hmac_drbg_reseed                                               
+mbedtls_rsa_rsaes_pkcs1_v15_decrypt                                    
+mbedtls_pk_free                                                                                                                    
+mbedtls_pk_get_name                                                    
+mbedtls_mpi_add_mpi                                                    
+crypto_sign_ed25519_ref10_ge_p3_0                                      
+crypto_sign_ed25519_ref10_ge_frombytes_negate_vartime                  
+mbedtls_sha512                                                         
+crypto_sign_ed25519_ref10_ge_sub                                       
+crypto_aead_chacha20poly1305_ietf_nsecbytes                            
+mbedtls_md5_process                                                    
+mbedtls_asn1_write_bool                                                
+mbedtls_hmac_drbg_set_entropy_len                                      
+mbedtls_hmac_drbg_set_prediction_resistance                            
+mbedtls_oid_get_oid_by_pk_alg                                          
+mbedtls_pk_decrypt                                                     
+mbedtls_gcm_setkey                                                     
+mbedtls_ecp_gen_keypair                                                
+mbedtls_asn1_write_mpi                                                 
+mbedtls_mpi_sub_mpi                                                                                                              
+crypto_core_hchacha20                                                  
+mbedtls_md_get_name                                                    
+mbedtls_rsa_rsassa_pss_verify_ext                                      
+mbedtls_dhm_calc_secret                                                
+mbedtls_ctr_drbg_seed                                                  
+mbedtls_ecdh_get_params                                                
+crypto_aead_xchacha20poly1305_ietf_nsecbytes                           
+mbedtls_asn1_get_bitstring                                             
+crypto_sign_ed25519_ref10_fe_add                                       
+mbedtls_asn1_store_named_data                                          
+mbedtls_ecies_write_version                                            
+mbedtls_oid_get_oid_by_md                                              
+mbedtls_gcm_starts                                                                                                                
+mbedtls_rsa_pkcs1_encrypt                                              
+mbedtls_rsa_rsassa_pkcs1_v15_sign                                      
+mbedtls_ecp_point_read_binary                                          
+crypto_aead_chacha20poly1305_encrypt_detached                          
+crypto_aead_chacha20poly1305_decrypt_detached                          
+crypto_aead_chacha20poly1305_ietf_encrypt                              
+mbedtls_asn1_write_printable_string                                    
+crypto_aead_xchacha20poly1305_ietf_keygen                              
+mbedtls_ctr_drbg_reseed                                                                                                   
+crypto_aead_chacha20poly1305_ietf_keygen                               
+mbedtls_ecies_read_content_info                                        
+mbedtls_mpi_lset                                                       
+mbedtls_md5_free                                                       
+mbedtls_fast_ec_sign                                                   
+mbedtls_cipher_write_tag                                               
+mbedtls_platform_set_fprintf                                           
+mbedtls_ecp_point_read_string                                          
+mbedtls_ecies_read_envelope                                            
+mbedtls_rsa_public                                                     
+mbedtls_ecdsa_from_keypair                                                                                                        
+mbedtls_ecp_gen_key                                                    
+mbedtls_pk_verify_ext                                                  
+crypto_sign_ed25519_ref10_ge_p1p1_to_p3                                
+mbedtls_mpi_div_int                                                    
+mbedtls_fast_ec_init                                                   
+romConfigPin                                                           
+mbedtls_cipher_setkey                                                  
+crypto_stream_chacha20_keybytes                                        
+sha256_process                                                         
+mbedtls_sha512_process                                                 
+mbedtls_pk_get_bitlen                                                  
+mbedtls_mpi_mul_int                                                    
+mbedtls_mpi_exp_mod                                                    
+mbedtls_mpi_safe_cond_assign                                           
+mbedtls_aes_setkey_enc                                                 
+mbedtls_ecies_read_version                                             
+mbedtls_cipher_update                                                  
+mbedtls_hardclock_poll                                                 
+mbedtls_ecp_curve_list                                                 
+mbedtls_kdf_get_type                                                   
+mbedtls_md_init                                                        
+mbedtls_dhm_make_params                                                
+mbedtls_oid_get_pkcs12_pbe_alg                                         
+crypto_sign_ed25519_ref10_sc_muladd                                    
+crypto_sign_ed25519_ref10_ge_p3_dbl                                    
+mbedtls_ecp_gen_keypair_base                                           
+mbedtls_mpi_cmp_abs                                                    
+mbedtls_pk_verify                                                      
+crypto_sign_ed25519_ref10_fe_copy                                      
+mbedtls_rsa_check_pub_priv                                             
+format_str                                                             
+mbedtls_entropy_free                                                   
+mbedtls_asn1_write_bitstring                                           
+mbedtls_fast_ec_free                                                   
+crypto_stream_chacha20_ietf_keybytes                                   
+mbedtls_ecp_point_free                                                 
+mbedtls_sha512_update                                                  
+mbedtls_platform_set_exit                                              
+mbedtls_cipher_setup                                                   
+mbedtls_mpi_cmp_int                                                                                                                    
+mbedtls_ecp_check_pubkey                                               
+crypto_sign_ed25519_ref10_ge_madd                                      
+mbedtls_entropy_init                                                   
+mbedtls_memory_buffer_alloc_init                                       
+mbedtls_pk_write_key_pkcs8_der                                         
+mbedtls_mpi_mod_int                                                    
+mbedtls_oid_get_oid_by_cipher_alg                                      
+mbedtls_fast_ec_get_key_bitlen                                         
+crypto_aead_chacha20poly1305_abytes                                    
+mbedtls_ecies_encrypt                                                  
+mbedtls_ecdh_read_params                                               
+mbedtls_oid_get_cipher_alg                                             
+mbedtls_rsa_rsassa_pss_sign                                            
+mbedtls_mpi_copy                                                                                                                
+crypto_sign_ed25519_ref10_fe_sq2                                       
+_crypto_stream_chacha20_pick_best_implementation                       
+mbedtls_ed25519_get_pubkey                                             
+mbedtls_ecdsa_init                                                                                                            
+mbedtls_curve25519_key_exchange                                        
+mbedtls_sha1_update                                                    
+mbedtls_mpi_swap                                                                                                               
+mbedtls_ecdh_read_public                                               
+mbedtls_ed25519_key_to_curve25519                                      
+mbedtls_dhm_read_public                                                
+crypto_verify_16                                                       
+crypto_stream_chacha20_ietf                                            
+mbedtls_asn1_write_len                                                 
+mbedtls_md_hmac_update                                                 
+mbedtls_ecp_tls_read_group                                             
+mbedtls_mpi_shift_l                                                                                                            
+mbedtls_mpi_cmp_mpi                                                                                                               
+mbedtls_gcm_finish                                                     
+mbedtls_ecp_group_load                                                 
+crypto_stream_chacha20_noncebytes                                      
+mbedtls_asn1_write_oid                                                 
+mbedtls_ecp_point_write_binary                                         
+mbedtls_ctr_drbg_set_reseed_interval                                   
+mbedtls_dhm_parse_dhm                                                  
+mbedtls_oid_get_sig_alg                                                
+mbedtls_rsa_pkcs1_verify                                               
+mbedtls_mpi_add_abs                                                    
+mbedtls_ecdh_make_params                                               
+mbedtls_entropy_gather                                                 
+mbedtls_ecdh_compute_shared                                                                                                      
+mbedtls_ecdsa_genkey                                                   
+mbedtls_fast_ec_verify                                                 
+mbedtls_mpi_mod_mpi                                                    
+mbedtls_md_process                                                     
+crypto_stream_chacha20_xor_ic                                                                                                 
+mbedtls_md_setup                                                       
+crypto_aead_chacha20poly1305_npubbytes                                 
+mbedtls_fast_ec_compute_shared                                         
+mbedtls_ecdsa_write_signature                                          
+crypto_aead_chacha20poly1305_keygen                                    
+crypto_onetimeauth_poly1305_keybytes                                   
+mbedtls_platform_set_calloc_free                                       
+mbedtls_pk_parse_subpubkey                                             
+mbedtls_cipher_check_tag                                               
+mbedtls_hmac_drbg_free                                                 
+crypto_stream_chacha20_ietf_xor_ic                                     
+mbedtls_cipher_crypt                                                   
+mbedtls_pk_encrypt                                                     
+mbedtls_mpi_gcd                                                        
+crypto_sign_ed25519_ref10_ge_precomp_0                                 
+mbedtls_md_finish                                                      
+iot_snprintf                                                           
+mbedtls_sha256_clone                                                   
+mbedtls_ecp_mul                                                        
+mbedtls_hmac_drbg_update                                               
+mbedtls_md_list                                                        
+mbedtls_pk_sign                                                        
+crypto_sign_ed25519_ref10_fe_cswap                                     
+crypto_verify_16_bytes                                                 
+crypto_sign_ed25519_ref10_sc_reduce                                    
+mbedtls_rsa_private                                                    
+mbedtls_md5_starts                                                     
+mbedtls_ecdh_make_public                                               
+crypto_core_hchacha20_inputbytes                                       
+mbedtls_md_get_type                                                    
+mbedtls_kdf_get_name                                                   
+sha256_free                                                            
+mbedtls_oid_get_sig_alg_desc                                           
+mbedtls_gcm_crypt_and_tag                                              
+mbedtls_sha256_free                                                    
+mbedtls_version_get_number                                             
+mbedtls_ecies_write_content_info                                       
+mbedtls_gcm_auth_decrypt                                               
+crypto_onetimeauth_poly1305_init                                       
+mbedtls_ecp_keypair_init                                               
+crypto_sign_ed25519_ref10_fe_neg                                       
+mbedtls_md_hmac_finish                                                 
+crypto_sign_ed25519_ref10_fe_tobytes                                   
+mbedtls_aes_init                                                       
+crypto_stream_chacha20_ietf_noncebytes                                 
+mbedtls_cipher_init                                                    
+crypto_verify_32                                                       
+mbedtls_pk_info_from_type                                              
+mbedtls_sha256_process                                                 
+mbedtls_rsa_set_padding                                                
+mbedtls_md5_init                                                       
+mbedtls_cipher_info_from_type                                          
+mbedtls_fast_ec_get_sig_len                                            
+mbedtls_cipher_list                                                    
+mbedtls_md5_clone                                                      
+mbedtls_md_init_ctx                                                    
+mbedtls_md_info_from_string                                            
+mbedtls_sha512_finish                                                  
+mbedtls_asn1_find_named_data                                           
+crypto_aead_xchacha20poly1305_ietf_npubbytes                           
+mbedtls_platform_set_snprintf                                                                                                       
+mbedtls_mpi_add_int                                                    
+crypto_stream_chacha20_ietf_xor                                        
+mbedtls_asn1_free_named_data_list                                                                                               
+crypto_aead_chacha20poly1305_ietf_encrypt_detached                     
+mbedtls_pk_debug                                                       
+mbedtls_fast_ec_gen_key                                                
+mbedtls_entropy_update_manual                                          
+sha256_update                                                          
+mbedtls_ecp_is_zero                                                                                                            
+mbedtls_ecdh_free                                                                                                               
+crypto_onetimeauth_poly1305                                            
+mbedtls_oid_get_pk_alg                                                 
+crypto_aead_xchacha20poly1305_ietf_decrypt_detached                    
+mbedtls_ecp_tls_write_group                                            
+crypto_sign_ed25519_ref10_fe_isnegative                                
+mbedtls_pk_write_key_der                                                                                                         
+mbedtls_mpi_inv_mod                                                    
+crypto_verify_64_bytes                                                 
+mbedtls_hmac_drbg_seed                                                 
+mbedtls_sha1_clone                                                     
+mbedtls_ecp_tls_write_point                                            
+mbedtls_mpi_div_mpi                                                    
+mbedtls_mpi_size                                                       
+mbedtls_cipher_update_ad                                               
+mbedtls_aes_crypt_ecb                                                  
+mbedtls_sha1_free                                                      
+mbedtls_aes_crypt_ctr                                                                                                                  
+mbedtls_asn1_get_mpi                                                   
+mbedtls_mpi_set_bit                                                    
+crypto_aead_chacha20poly1305_ietf_keybytes                             
+crypto_sign_ed25519_ref10_fe_cmov                                      
+iot_vsnprintf                                                          
+crypto_onetimeauth_poly1305_bytes                                      
+mbedtls_asn1_write_raw_buffer                                                                                                   
+mbedtls_mpi_is_prime                                                   
+mbedtls_ecp_curve_info_from_tls_id                                     
+mbedtls_rsa_rsassa_pkcs1_v15_verify                                    
+mbedtls_sha1                                                           
+mbedtls_curve25519_get_pubkey                                          
+mbedtls_ecdsa_read_signature                                           
+mbedtls_asn1_get_sequence_of                                           
+mbedtls_pkcs12_pbe_sha1_rc4_128                                        
+crypto_stream_chacha20                                                 
+mbedtls_pkcs12_pbe_ext                                                 
+mbedtls_gcm_update                                                     
+mpi_montmul                                                            
+mbedtls_ecp_tls_read_point                                             
+mbedtls_oid_get_ec_grp                                                 
+mbedtls_fast_ec_check_pub_priv                                         
+mbedtls_md_clone                                                       
+mbedtls_gcm_free                                                                                                           
+mbedtls_ecp_group_init                                                                                                         
+mbedtls_ecp_grp_id_list                                                
+mbedtls_md_hmac_reset                                                  
+mbedtls_sha512_init                                                    
+mbedtls_ecies_write_envelope                                           
+mbedtls_sha512_starts                                                  
+mbedtls_md_update                                                      
+crypto_aead_chacha20poly1305_ietf_npubbytes                            
+crypto_aead_chacha20poly1305_ietf_decrypt                              
+mbedtls_md_get_size                                                                                                             
+crypto_onetimeauth_poly1305_final                                      
+format_str_v                                                           
+sodium_memzero                                                         
+mbedtls_md5_finish                                                     
+mbedtls_mpi_free                                                       
+crypto_verify_32_bytes                                                 
+mbedtls_md_hmac                                                        
+mbedtls_asn1_write_null                                                                                                     
+crypto_aead_xchacha20poly1305_ietf_keybytes                            
+mbedtls_fast_ec_setup                                                  
+mbedtls_pk_parse_public_key                                            
+mbedtls_hmac_drbg_random                                               
+mbedtls_ecdh_calc_secret                                               
+crypto_sign_ed25519_ref10_ge_double_scalarmult_vartime                 
+mbedtls_pk_setup_rsa_alt                                               
+mbedtls_dhm_init                                                       
+crypto_sign_ed25519_ref10_fe_mul121666                                                                                              
+mbedtls_aes_crypt_cbc                                                  
+mbedtls_hmac_drbg_init                                                 
+mbedtls_hmac_drbg_set_reseed_interval                                  
+mbedtls_pk_write_pubkey_der                                            
+mbedtls_mpi_safe_cond_swap                                             
+crypto_sign_ed25519_ref10_fe_sub                                       
+mbedtls_oid_get_oid_by_ec_grp                                                                                                        
+mbedtls_cipher_finish                                                  
+mbedtls_md_hmac_starts                                                 
+crypto_sign_ed25519_ref10_ge_p1p1_to_p2                                
+mbedtls_fast_ec_get_key_len                                            
+crypto_onetimeauth_poly1305_keygen                                     
+mbedtls_cipher_set_padding_mode                                        
+mbedtls_rsa_init                                                       
+mbedtls_rsa_pkcs1_sign                                                 
+mbedtls_pk_setup                                                                                                               
+mbedtls_pk_init                                                        
+mbedtls_mpi_sub_abs                                                    
+mbedtls_mpi_fill_random                                                                                                       
+mbedtls_entropy_func                                                   
+mbedtls_md_info_from_type                                              
+mbedtls_entropy_add_source                                             
+mbedtls_md_free                                                        
+mbedtls_mpi_write_string                                               
+mbedtls_rsa_gen_key                                                    
+mbedtls_version_get_string                                             
+mbedtls_asn1_free_named_data                                           
+mbedtls_oid_get_kdf_alg                                                
+mbedtls_ecp_check_privkey                                              
+mbedtls_memory_buffer_set_verify                                       
+mbedtls_cipher_set_iv                                                  
+mbedtls_pk_check_pair                                                  
+crypto_sign_ed25519_ref10_ge_msub                                      
+mbedtls_ecies_read_kdf                                                 
+mbedtls_asn1_write_algorithm_identifier                                
+mbedtls_ecies_info_from_type                                           
+crypto_aead_chacha20poly1305_encrypt                                   
+mbedtls_memory_buffer_alloc_verify                                     
+mbedtls_md5
+crypto_stream_chacha20_ref_implementation
diff --git a/tools/rom_img/riscv2/sp_symbol b/tools/rom_img/riscv2/sp_symbol
new file mode 100644
index 0000000..4c7868a
--- /dev/null
+++ b/tools/rom_img/riscv2/sp_symbol
@@ -0,0 +1,7 @@
+_gp
+_start_2
+g_cpu1_state
+g_wq_vtb_topo_op
+g_decm_filter
+g_cos_tab
+g_sin_tab
\ No newline at end of file
diff --git a/tools/rom_img/riscv3/Kl3_rom_自测记录表_V1.0.xlsx b/tools/rom_img/riscv3/Kl3_rom_自测记录表_V1.0.xlsx
new file mode 100644
index 0000000..daa5856
Binary files /dev/null and b/tools/rom_img/riscv3/Kl3_rom_自测记录表_V1.0.xlsx differ
diff --git a/tools/rom_img/riscv3/ROM_IMG_V3.1.0.0_20210811.zip b/tools/rom_img/riscv3/ROM_IMG_V3.1.0.0_20210811.zip
new file mode 100644
index 0000000..5b9da52
Binary files /dev/null and b/tools/rom_img/riscv3/ROM_IMG_V3.1.0.0_20210811.zip differ
diff --git a/tools/rom_img/riscv3/ROM_IMG_V3.1.0.1_20210907.zip b/tools/rom_img/riscv3/ROM_IMG_V3.1.0.1_20210907.zip
new file mode 100644
index 0000000..a6f052a
Binary files /dev/null and b/tools/rom_img/riscv3/ROM_IMG_V3.1.0.1_20210907.zip differ
diff --git a/tools/rom_img/riscv3/ROM_IMG_V3.1.0.2_20210914.zip b/tools/rom_img/riscv3/ROM_IMG_V3.1.0.2_20210914.zip
new file mode 100644
index 0000000..21f468e
Binary files /dev/null and b/tools/rom_img/riscv3/ROM_IMG_V3.1.0.2_20210914.zip differ
diff --git a/tools/rom_img/riscv3/ROM_IMG_V3.1.0.3_20210917.zip b/tools/rom_img/riscv3/ROM_IMG_V3.1.0.3_20210917.zip
new file mode 100644
index 0000000..fdc59c8
Binary files /dev/null and b/tools/rom_img/riscv3/ROM_IMG_V3.1.0.3_20210917.zip differ
diff --git a/tools/rom_img/riscv3/ROM_IMG_V3.1.0.4_20211014.zip b/tools/rom_img/riscv3/ROM_IMG_V3.1.0.4_20211014.zip
new file mode 100644
index 0000000..c517a86
Binary files /dev/null and b/tools/rom_img/riscv3/ROM_IMG_V3.1.0.4_20211014.zip differ
diff --git a/tools/rom_img/riscv3/ROM_IMG_V3.2.0.0_20211126.zip b/tools/rom_img/riscv3/ROM_IMG_V3.2.0.0_20211126.zip
new file mode 100644
index 0000000..fc8762f
Binary files /dev/null and b/tools/rom_img/riscv3/ROM_IMG_V3.2.0.0_20211126.zip differ
diff --git a/tools/rom_img/riscv3/ROM_IMG_V3.2.0.2_20211202.zip b/tools/rom_img/riscv3/ROM_IMG_V3.2.0.2_20211202.zip
new file mode 100644
index 0000000..512eb8f
Binary files /dev/null and b/tools/rom_img/riscv3/ROM_IMG_V3.2.0.2_20211202.zip differ
diff --git a/tools/rom_img/riscv3/ROM_IMG_V3.2.1.0_20211203.zip b/tools/rom_img/riscv3/ROM_IMG_V3.2.1.0_20211203.zip
new file mode 100644
index 0000000..48cca6a
Binary files /dev/null and b/tools/rom_img/riscv3/ROM_IMG_V3.2.1.0_20211203.zip differ
diff --git a/tools/rom_img/riscv3/ROM_IMG_V3.2.1.1_20211206.zip b/tools/rom_img/riscv3/ROM_IMG_V3.2.1.1_20211206.zip
new file mode 100644
index 0000000..21fff46
Binary files /dev/null and b/tools/rom_img/riscv3/ROM_IMG_V3.2.1.1_20211206.zip differ
diff --git a/tools/rom_img/riscv3/rom_gen.sh b/tools/rom_img/riscv3/rom_gen.sh
new file mode 100755
index 0000000..235e37e
--- /dev/null
+++ b/tools/rom_img/riscv3/rom_gen.sh
@@ -0,0 +1,14 @@
+#!/bin/bash
+
+CUR_DIR=$(cd `dirname $0`; pwd)
+TOP_DIR=$CUR_DIR"/../../../"
+
+#cp $TOP_DIR"rom/riscv3/crypto/.output/lib/kl_romlib.out" $CUR_DIR
+../make_ld.sh --addrs $CUR_DIR"/libs/kl_romlib.out" rom_symbol > $CUR_DIR"/romlib.addrs.ld"
+
+cp $CUR_DIR"/romlib.addrs.ld" $TOP_DIR"/startup/ldscripts/riscv3"
+
+cd ./libs
+riscv64-unknown-elf-objdump -D kl_rom.out > kl_rom.asm
+python ../romhex.py kl_rom.bin kl_romlib.bin
+cd -
\ No newline at end of file
diff --git a/tools/rom_img/riscv3/rom_symbol b/tools/rom_img/riscv3/rom_symbol
new file mode 100644
index 0000000..760ceb5
--- /dev/null
+++ b/tools/rom_img/riscv3/rom_symbol
@@ -0,0 +1,517 @@
+_gp
+_end
+iot_indir_tbl
+log_ctxt
+memset
+memcpy
+memcmp
+iot_sprintf
+iot_printf
+mbedtls_rsa_rsaes_oaep_encrypt                                         
+mbedtls_cipher_reset                                                   
+mbedtls_fast_ec_get_name                                               
+crypto_sign_ed25519_ref10_fe_sq                                        
+mbedtls_ctr_drbg_init                                                  
+crypto_sign_ed25519_ref10_ge_tobytes                                   
+strcpy                                                                 
+mbedtls_pkcs12_derivation                                              
+crypto_aead_chacha20poly1305_decrypt                                   
+mbedtls_ctr_drbg_set_prediction_resistance                             
+SFC_OPR_SET                                                            
+mbedtls_mpi_grow                                                       
+mbedtls_md_starts                                                      
+mbedtls_asn1_get_bitstring_null                                        
+crypto_aead_xchacha20poly1305_ietf_encrypt_detached                    
+mbedtls_ecp_point_init                                                 
+mbedtls_oid_get_oid_by_kdf_alg                                         
+mbedtls_fast_ec_get_shared_len                                         
+crypto_sign_ed25519_ref10_ge_p2_dbl                                    
+mbedtls_rsa_free                                                       
+crypto_sign_ed25519_ref10_fe_invert                                    
+mbedtls_hardware_poll                                                  
+crypto_onetimeauth_poly1305_update                                     
+mbedtls_asn1_write_tag                                                 
+mbedtls_ctr_drbg_update                                                
+mbedtls_ecdh_init                                                      
+mbedtls_gcm_init                                                       
+mbedtls_asn1_get_len                                                   
+mbedtls_ecp_point_cmp                                                  
+CRC32_Update                                                           
+mbedtls_dhm_read_params                                                
+sFlashPageRead                                                         
+mbedtls_strerror                                                       
+crypto_aead_xchacha20poly1305_ietf_encrypt                             
+crypto_aead_chacha20poly1305_ietf_abytes                               
+mbedtls_mpi_write_binary                                               
+mbedtls_ecp_keypair_free                                               
+mbedtls_ecp_muladd                                                     
+crypto_sign_ed25519_ref10_fe_1                                         
+mbedtls_ed25519_pubkey_to_curve25519                                   
+mbedtls_ed25519_verify                                                 
+mbedtls_asn1_get_alg                                                   
+mbedtls_ecdsa_sign                                                     
+mbedtls_mpi_sub_int                                                    
+mbedtls_kdf2                                                           
+mbedtls_asn1_write_ia5_string                                          
+memmove                                                                
+mbedtls_asn1_get_bool                                                  
+crypto_aead_xchacha20poly1305_ietf_decrypt                             
+mbedtls_ecies_write_hmac                                               
+mbedtls_version_check_feature                                          
+mbedtls_aes_free                                                       
+mbedtls_sha256_init                                                    
+crypto_aead_chacha20poly1305_ietf_decrypt_detached                     
+mbedtls_dhm_make_public                                                
+mbedtls_kdf_info_from_type                                             
+mbedtls_ecp_copy                                                       
+crypto_stream_chacha20_keygen                                          
+mbedtls_hmac_drbg_seed_buf                                             
+mbedtls_mpi_shrink                                                     
+crypto_verify_64                                                       
+crypto_sign_ed25519_ref10_ge_p3_to_cached                              
+mbedtls_fast_ec_info_from_type                                         
+mbedtls_cipher_auth_encrypt                                            
+crypto_sign_ed25519_ref10_ge_p3_tobytes                                
+mbedtls_kdf_info_from_string                                           
+mbedtls_sha1_finish                                                    
+crypto_aead_xchacha20poly1305_ietf_abytes                              
+mbedtls_rsa_rsaes_oaep_decrypt                                         
+mbedtls_rsa_pkcs1_decrypt                                              
+mbedtls_pk_can_do                                                      
+mbedtls_sha256                                                         
+mbedtls_rsa_rsassa_pss_verify                                          
+FLASH_WRITE_ENABLE                                                     
+mbedtls_rsa_check_privkey                                              
+mbedtls_pk_get_type                                                    
+romUartBoot                                                            
+crypto_stream_chacha20_xor                                             
+mbedtls_mpi_read_string                                                
+mbedtls_ctr_drbg_free                                                  
+mbedtls_ctr_drbg_random_with_add                                       
+mbedtls_asn1_write_octet_string                                        
+sha256_init                                                            
+mbedtls_curve25519_sign                                                
+mbedtls_md                                                             
+mbedtls_ecp_group_copy                                                 
+iot_printf                                                             
+mbedtls_ecdh_gen_public                                                
+mbedtls_asn1_get_tag                                                   
+mbedtls_ecdsa_verify                                                   
+mbedtls_ctr_drbg_set_entropy_len                                       
+_crypto_onetimeauth_poly1305_pick_best_implementation                  
+romAHBInit                                                             
+mbedtls_fast_ec_compute_pub                                            
+crypto_sign_ed25519_ref10_fe_pow22523                                  
+mbedtls_sha256_finish                                                  
+mbedtls_mpi_shift_r                                                    
+mbedtls_sha512_clone                                                   
+crypto_sign_ed25519_ref10_ge_p2_0                                      
+mbedtls_ctr_drbg_random                                                
+mbedtls_ed25519_sign                                                   
+mbedtls_pk_write_pubkey                                                
+mbedtls_mpi_gen_prime                                                  
+mbedtls_ecp_curve_info_from_grp_id                                     
+mbedtls_asn1_write_algorithm_identifier_no_params                      
+mbedtls_mpi_get_bit                                                    
+mbedtls_ecies_decrypt                                                  
+mbedtls_mpi_read_binary                                                
+crypto_core_hchacha20_outputbytes                                                                                               
+mbedtls_asn1_write_int                                                 
+mbedtls_sha1_init                                                      
+crypto_stream_chacha20_ietf_keygen                                     
+mbedtls_cipher_info_from_values                                        
+mbedtls_asn1_get_int                                                   
+mbedtls_ctr_drbg_seed_entropy_len                                      
+mbedtls_fast_ec_copy                                                   
+crypto_onetimeauth_poly1305_verify                                     
+mbedtls_ecies_write_kdf                                                
+memcpy                                                                 
+sUartPutString                                                         
+mbedtls_sha1_starts                                                    
+mbedtls_sha1_process                                                   
+mbedtls_cipher_info_from_string                                        
+crypto_sign_ed25519_ref10_ge_scalarmult_base                           
+crypto_sign_ed25519_ref10_fe_frombytes                                 
+mbedtls_hmac_drbg_random_with_add                                      
+mbedtls_fast_ec_get_type                                               
+crypto_aead_chacha20poly1305_keybytes                                  
+crypto_sign_ed25519_ref10_fe_isnonzero                                 
+crypto_sign_ed25519_ref10_fe_mul                                       
+mbedtls_platform_set_printf                                            
+mbedtls_ecp_curve_info_from_name                                       
+mbedtls_aes_setkey_dec                                                 
+mbedtls_ecp_group_free                                                 
+crypto_onetimeauth_poly1305_statebytes                                 
+mbedtls_kdf_list                                                       
+mbedtls_rsa_copy                                                       
+mbedtls_version_get_string_full                                        
+mbedtls_rsa_rsaes_pkcs1_v15_encrypt                                    
+mbedtls_ecies_read_hmac                                                
+mbedtls_asn1_get_alg_null                                              
+crypto_sign_ed25519_ref10_ge_add                                       
+mbedtls_sha256_starts                                                  
+crypto_aead_chacha20poly1305_nsecbytes                                 
+mbedtls_sha256_update                                                  
+mbedtls_mpi_bitlen                                                     
+mbedtls_ecdsa_free                                                     
+mbedtls_rsa_check_pubkey                                               
+mbedtls_sha512_free                                                    
+mbedtls_md5_update                                                     
+mbedtls_oid_get_md_alg                                                 
+mbedtls_ecp_check_pub_priv                                             
+mbedtls_mpi_mul_mpi                                                    
+FLASH_SECTOR_ERASE                                                     
+mbedtls_kdf                                                            
+mbedtls_ecp_set_zero                                                   
+mbedtls_dhm_free                                                       
+mbedtls_cipher_auth_decrypt                                            
+crypto_sign_ed25519_ref10_fe_0                                         
+crypto_core_hchacha20_keybytes                                         
+crypto_sign_ed25519_ref10_ge_p3_to_p2                                  
+mbedtls_mpi_init                                                       
+mbedtls_mpi_lsb                                                        
+mbedtls_pkcs12_pbe                                                     
+randombytes_buf                                                        
+mbedtls_oid_get_oid_by_sig_alg                                         
+mbedtls_cipher_free                                                    
+mbedtls_memory_buffer_alloc_free                                       
+mbedtls_curve25519_verify                                              
+iot_sprintf                                                            
+mbedtls_pk_parse_key                                                   
+mbedtls_oid_get_numeric_string                                         
+crypto_core_hchacha20_constbytes                                       
+mbedtls_hmac_drbg_reseed                                               
+mbedtls_rsa_rsaes_pkcs1_v15_decrypt                                    
+mbedtls_pk_free                                                                                                                    
+mbedtls_pk_get_name                                                    
+mbedtls_mpi_add_mpi                                                    
+crypto_sign_ed25519_ref10_ge_p3_0                                      
+crypto_sign_ed25519_ref10_ge_frombytes_negate_vartime                  
+mbedtls_sha512                                                         
+crypto_sign_ed25519_ref10_ge_sub                                       
+crypto_aead_chacha20poly1305_ietf_nsecbytes                            
+mbedtls_md5_process                                                    
+mbedtls_asn1_write_bool                                                
+mbedtls_hmac_drbg_set_entropy_len                                      
+mbedtls_hmac_drbg_set_prediction_resistance                            
+mbedtls_oid_get_oid_by_pk_alg                                          
+mbedtls_pk_decrypt                                                     
+mbedtls_gcm_setkey                                                     
+mbedtls_ecp_gen_keypair                                                
+mbedtls_asn1_write_mpi                                                 
+mbedtls_mpi_sub_mpi                                                                                                              
+crypto_core_hchacha20                                                  
+mbedtls_md_get_name                                                    
+mbedtls_rsa_rsassa_pss_verify_ext                                      
+mbedtls_dhm_calc_secret                                                
+mbedtls_ctr_drbg_seed                                                  
+mbedtls_ecdh_get_params                                                
+crypto_aead_xchacha20poly1305_ietf_nsecbytes                           
+mbedtls_asn1_get_bitstring                                             
+crypto_sign_ed25519_ref10_fe_add                                       
+mbedtls_asn1_store_named_data                                          
+mbedtls_ecies_write_version                                            
+mbedtls_oid_get_oid_by_md                                              
+mbedtls_gcm_starts                                                                                                                
+mbedtls_rsa_pkcs1_encrypt                                              
+mbedtls_rsa_rsassa_pkcs1_v15_sign                                      
+mbedtls_ecp_point_read_binary                                          
+crypto_aead_chacha20poly1305_encrypt_detached                          
+crypto_aead_chacha20poly1305_decrypt_detached                          
+crypto_aead_chacha20poly1305_ietf_encrypt                              
+mbedtls_asn1_write_printable_string                                    
+crypto_aead_xchacha20poly1305_ietf_keygen                              
+mbedtls_ctr_drbg_reseed                                                                                                   
+crypto_aead_chacha20poly1305_ietf_keygen                               
+mbedtls_ecies_read_content_info                                        
+mbedtls_mpi_lset                                                       
+mbedtls_md5_free                                                       
+mbedtls_fast_ec_sign                                                   
+mbedtls_cipher_write_tag                                               
+mbedtls_platform_set_fprintf                                           
+mbedtls_ecp_point_read_string                                          
+mbedtls_ecies_read_envelope                                            
+mbedtls_rsa_public                                                     
+mbedtls_ecdsa_from_keypair                                                                                                        
+mbedtls_ecp_gen_key                                                    
+mbedtls_pk_verify_ext                                                  
+crypto_sign_ed25519_ref10_ge_p1p1_to_p3                                
+mbedtls_mpi_div_int                                                    
+mbedtls_fast_ec_init                                                   
+romConfigPin                                                           
+mbedtls_cipher_setkey                                                  
+crypto_stream_chacha20_keybytes                                        
+sha256_process                                                         
+mbedtls_sha512_process                                                 
+mbedtls_pk_get_bitlen                                                  
+mbedtls_mpi_mul_int                                                    
+mbedtls_mpi_exp_mod                                                    
+mbedtls_mpi_safe_cond_assign                                           
+mbedtls_aes_setkey_enc                                                 
+mbedtls_ecies_read_version                                             
+mbedtls_cipher_update                                                  
+mbedtls_hardclock_poll                                                 
+mbedtls_ecp_curve_list                                                 
+mbedtls_kdf_get_type                                                   
+mbedtls_md_init                                                        
+mbedtls_dhm_make_params                                                
+mbedtls_oid_get_pkcs12_pbe_alg                                         
+crypto_sign_ed25519_ref10_sc_muladd                                    
+crypto_sign_ed25519_ref10_ge_p3_dbl                                    
+mbedtls_ecp_gen_keypair_base                                           
+mbedtls_mpi_cmp_abs                                                    
+mbedtls_pk_verify                                                      
+crypto_sign_ed25519_ref10_fe_copy                                      
+mbedtls_rsa_check_pub_priv                                             
+format_str                                                             
+mbedtls_entropy_free                                                   
+mbedtls_asn1_write_bitstring                                           
+mbedtls_fast_ec_free                                                   
+crypto_stream_chacha20_ietf_keybytes                                   
+mbedtls_ecp_point_free                                                 
+mbedtls_sha512_update                                                  
+mbedtls_platform_set_exit                                              
+mbedtls_cipher_setup                                                   
+mbedtls_mpi_cmp_int                                                                                                                    
+mbedtls_ecp_check_pubkey                                               
+crypto_sign_ed25519_ref10_ge_madd                                      
+mbedtls_entropy_init                                                   
+mbedtls_memory_buffer_alloc_init                                       
+mbedtls_pk_write_key_pkcs8_der                                         
+mbedtls_mpi_mod_int                                                    
+mbedtls_oid_get_oid_by_cipher_alg                                      
+mbedtls_fast_ec_get_key_bitlen                                         
+crypto_aead_chacha20poly1305_abytes                                    
+mbedtls_ecies_encrypt                                                  
+mbedtls_ecdh_read_params                                               
+mbedtls_oid_get_cipher_alg                                             
+mbedtls_rsa_rsassa_pss_sign                                            
+mbedtls_mpi_copy                                                                                                                
+crypto_sign_ed25519_ref10_fe_sq2                                       
+_crypto_stream_chacha20_pick_best_implementation                       
+mbedtls_ed25519_get_pubkey                                             
+mbedtls_ecdsa_init                                                                                                            
+mbedtls_curve25519_key_exchange                                        
+mbedtls_sha1_update                                                    
+mbedtls_mpi_swap                                                                                                               
+mbedtls_ecdh_read_public                                               
+mbedtls_ed25519_key_to_curve25519                                      
+mbedtls_dhm_read_public                                                
+crypto_verify_16                                                       
+crypto_stream_chacha20_ietf                                            
+mbedtls_asn1_write_len                                                 
+mbedtls_md_hmac_update                                                 
+mbedtls_ecp_tls_read_group                                             
+mbedtls_mpi_shift_l                                                                                                            
+mbedtls_mpi_cmp_mpi                                                                                                               
+mbedtls_gcm_finish                                                     
+mbedtls_ecp_group_load                                                 
+crypto_stream_chacha20_noncebytes                                      
+mbedtls_asn1_write_oid                                                 
+mbedtls_ecp_point_write_binary                                         
+mbedtls_ctr_drbg_set_reseed_interval                                   
+mbedtls_dhm_parse_dhm                                                  
+mbedtls_oid_get_sig_alg                                                
+mbedtls_rsa_pkcs1_verify                                               
+mbedtls_mpi_add_abs                                                    
+mbedtls_ecdh_make_params                                               
+mbedtls_entropy_gather                                                 
+mbedtls_ecdh_compute_shared                                                                                                      
+mbedtls_ecdsa_genkey                                                   
+mbedtls_fast_ec_verify                                                 
+mbedtls_mpi_mod_mpi                                                    
+mbedtls_md_process                                                     
+crypto_stream_chacha20_xor_ic                                                                                                 
+mbedtls_md_setup                                                       
+crypto_aead_chacha20poly1305_npubbytes                                 
+mbedtls_fast_ec_compute_shared                                         
+mbedtls_ecdsa_write_signature                                          
+crypto_aead_chacha20poly1305_keygen                                    
+crypto_onetimeauth_poly1305_keybytes                                   
+mbedtls_platform_set_calloc_free                                       
+mbedtls_pk_parse_subpubkey                                             
+mbedtls_cipher_check_tag                                               
+mbedtls_hmac_drbg_free                                                 
+crypto_stream_chacha20_ietf_xor_ic                                     
+mbedtls_cipher_crypt                                                   
+mbedtls_pk_encrypt                                                     
+mbedtls_mpi_gcd                                                        
+crypto_sign_ed25519_ref10_ge_precomp_0                                 
+mbedtls_md_finish                                                      
+iot_snprintf                                                           
+mbedtls_sha256_clone                                                   
+mbedtls_ecp_mul                                                        
+mbedtls_hmac_drbg_update                                               
+mbedtls_md_list                                                        
+mbedtls_pk_sign                                                        
+crypto_sign_ed25519_ref10_fe_cswap                                     
+crypto_verify_16_bytes                                                 
+crypto_sign_ed25519_ref10_sc_reduce                                    
+mbedtls_rsa_private                                                    
+mbedtls_md5_starts                                                     
+mbedtls_ecdh_make_public                                               
+crypto_core_hchacha20_inputbytes                                       
+mbedtls_md_get_type                                                    
+mbedtls_kdf_get_name                                                   
+sha256_free                                                            
+mbedtls_oid_get_sig_alg_desc                                           
+mbedtls_gcm_crypt_and_tag                                              
+mbedtls_sha256_free                                                    
+mbedtls_version_get_number                                             
+mbedtls_ecies_write_content_info                                       
+mbedtls_gcm_auth_decrypt                                               
+crypto_onetimeauth_poly1305_init                                       
+mbedtls_ecp_keypair_init                                               
+crypto_sign_ed25519_ref10_fe_neg                                       
+mbedtls_md_hmac_finish                                                 
+crypto_sign_ed25519_ref10_fe_tobytes                                   
+mbedtls_aes_init                                                       
+crypto_stream_chacha20_ietf_noncebytes                                 
+mbedtls_cipher_init                                                    
+crypto_verify_32                                                       
+mbedtls_pk_info_from_type                                              
+mbedtls_sha256_process                                                 
+mbedtls_rsa_set_padding                                                
+mbedtls_md5_init                                                       
+mbedtls_cipher_info_from_type                                          
+mbedtls_fast_ec_get_sig_len                                            
+mbedtls_cipher_list                                                    
+mbedtls_md5_clone                                                      
+mbedtls_md_init_ctx                                                    
+mbedtls_md_info_from_string                                            
+mbedtls_sha512_finish                                                  
+mbedtls_asn1_find_named_data                                           
+crypto_aead_xchacha20poly1305_ietf_npubbytes                           
+mbedtls_platform_set_snprintf                                                                                                       
+mbedtls_mpi_add_int                                                    
+crypto_stream_chacha20_ietf_xor                                        
+mbedtls_asn1_free_named_data_list                                                                                               
+crypto_aead_chacha20poly1305_ietf_encrypt_detached                     
+mbedtls_pk_debug                                                       
+mbedtls_fast_ec_gen_key                                                
+mbedtls_entropy_update_manual                                          
+sha256_update                                                          
+mbedtls_ecp_is_zero                                                                                                            
+mbedtls_ecdh_free                                                                                                               
+crypto_onetimeauth_poly1305                                            
+mbedtls_oid_get_pk_alg                                                 
+crypto_aead_xchacha20poly1305_ietf_decrypt_detached                    
+mbedtls_ecp_tls_write_group                                            
+crypto_sign_ed25519_ref10_fe_isnegative                                
+mbedtls_pk_write_key_der                                                                                                         
+mbedtls_mpi_inv_mod                                                    
+crypto_verify_64_bytes                                                 
+mbedtls_hmac_drbg_seed                                                 
+mbedtls_sha1_clone                                                     
+mbedtls_ecp_tls_write_point                                            
+mbedtls_mpi_div_mpi                                                    
+mbedtls_mpi_size                                                       
+mbedtls_cipher_update_ad                                               
+mbedtls_aes_crypt_ecb                                                  
+mbedtls_sha1_free                                                      
+mbedtls_aes_crypt_ctr                                                                                                                  
+mbedtls_asn1_get_mpi                                                   
+mbedtls_mpi_set_bit                                                    
+crypto_aead_chacha20poly1305_ietf_keybytes                             
+crypto_sign_ed25519_ref10_fe_cmov                                      
+iot_vsnprintf                                                          
+crypto_onetimeauth_poly1305_bytes                                      
+mbedtls_asn1_write_raw_buffer                                                                                                   
+mbedtls_mpi_is_prime                                                   
+mbedtls_ecp_curve_info_from_tls_id                                     
+mbedtls_rsa_rsassa_pkcs1_v15_verify                                    
+mbedtls_sha1                                                           
+mbedtls_curve25519_get_pubkey                                          
+mbedtls_ecdsa_read_signature                                           
+mbedtls_asn1_get_sequence_of                                           
+mbedtls_pkcs12_pbe_sha1_rc4_128                                        
+crypto_stream_chacha20                                                 
+mbedtls_pkcs12_pbe_ext                                                 
+mbedtls_gcm_update                                                     
+mpi_montmul                                                            
+mbedtls_ecp_tls_read_point                                             
+mbedtls_oid_get_ec_grp                                                 
+mbedtls_fast_ec_check_pub_priv                                         
+mbedtls_md_clone                                                       
+mbedtls_gcm_free                                                                                                           
+mbedtls_ecp_group_init                                                                                                         
+mbedtls_ecp_grp_id_list                                                
+mbedtls_md_hmac_reset                                                  
+mbedtls_sha512_init                                                    
+mbedtls_ecies_write_envelope                                           
+mbedtls_sha512_starts                                                  
+mbedtls_md_update                                                      
+crypto_aead_chacha20poly1305_ietf_npubbytes                            
+crypto_aead_chacha20poly1305_ietf_decrypt                              
+mbedtls_md_get_size                                                                                                             
+crypto_onetimeauth_poly1305_final                                      
+format_str_v                                                           
+sodium_memzero                                                         
+mbedtls_md5_finish                                                     
+mbedtls_mpi_free                                                       
+crypto_verify_32_bytes                                                 
+mbedtls_md_hmac                                                        
+mbedtls_asn1_write_null                                                                                                     
+crypto_aead_xchacha20poly1305_ietf_keybytes                            
+mbedtls_fast_ec_setup                                                  
+mbedtls_pk_parse_public_key                                            
+mbedtls_hmac_drbg_random                                               
+mbedtls_ecdh_calc_secret                                               
+crypto_sign_ed25519_ref10_ge_double_scalarmult_vartime                 
+mbedtls_pk_setup_rsa_alt                                               
+mbedtls_dhm_init                                                       
+crypto_sign_ed25519_ref10_fe_mul121666                                                                                              
+mbedtls_aes_crypt_cbc                                                  
+mbedtls_hmac_drbg_init                                                 
+mbedtls_hmac_drbg_set_reseed_interval                                  
+mbedtls_pk_write_pubkey_der                                            
+mbedtls_mpi_safe_cond_swap                                             
+crypto_sign_ed25519_ref10_fe_sub                                       
+mbedtls_oid_get_oid_by_ec_grp                                                                                                        
+mbedtls_cipher_finish                                                  
+mbedtls_md_hmac_starts                                                 
+crypto_sign_ed25519_ref10_ge_p1p1_to_p2                                
+mbedtls_fast_ec_get_key_len                                            
+crypto_onetimeauth_poly1305_keygen                                     
+mbedtls_cipher_set_padding_mode                                        
+mbedtls_rsa_init                                                       
+mbedtls_rsa_pkcs1_sign                                                 
+mbedtls_pk_setup                                                                                                               
+mbedtls_pk_init                                                        
+mbedtls_mpi_sub_abs                                                    
+mbedtls_mpi_fill_random                                                                                                       
+mbedtls_entropy_func                                                   
+mbedtls_md_info_from_type                                              
+mbedtls_entropy_add_source                                             
+mbedtls_md_free                                                        
+mbedtls_mpi_write_string                                               
+mbedtls_rsa_gen_key                                                    
+mbedtls_version_get_string                                             
+mbedtls_asn1_free_named_data                                           
+mbedtls_oid_get_kdf_alg                                                
+mbedtls_ecp_check_privkey                                              
+mbedtls_memory_buffer_set_verify                                       
+mbedtls_cipher_set_iv                                                  
+mbedtls_pk_check_pair                                                  
+crypto_sign_ed25519_ref10_ge_msub                                      
+mbedtls_ecies_read_kdf                                                 
+mbedtls_asn1_write_algorithm_identifier                                
+mbedtls_ecies_info_from_type                                           
+crypto_aead_chacha20poly1305_encrypt                                   
+mbedtls_memory_buffer_alloc_verify                                     
+mbedtls_md5
+crypto_stream_chacha20_ref_implementation
+romlib_section_init
+mbedtls_x509_crt_free
+mbedtls_x509_crt_info
+mbedtls_x509_crt_init
+mbedtls_x509_crt_parse
+mbedtls_x509_crt_parse_der
+mbedtls_x509_crt_profile_default
+mbedtls_x509_crt_profile_next
+mbedtls_x509_crt_profile_suiteb
+mbedtls_x509_crt_verify
+mbedtls_x509_crt_verify_info
+mbedtls_x509_crt_verify_with_profile
+mbedtls_base64_decode
+mbedtls_base64_encode
\ No newline at end of file
diff --git a/tools/rom_img/riscv3/romhex.py b/tools/rom_img/riscv3/romhex.py
new file mode 100644
index 0000000..36d4d92
--- /dev/null
+++ b/tools/rom_img/riscv3/romhex.py
@@ -0,0 +1,73 @@
+#
+# Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
+#
+# This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
+# be copied by any method or incorporated into another program without
+# the express written consent of Aerospace C.Power. This Information or any portion
+# thereof remains the property of Aerospace C.Power. The Information contained herein
+# is believed to be accurate and Aerospace C.Power assumes no responsibility or
+# liability for its use in any way and conveys no license or title under
+# any patent or copyright and makes no representation or warranty that this
+# Information is free from patent or copyright infringement.
+
+import os
+import sys
+import time
+
+len1 = 16384
+len2 = 245760
+split_len = 65536
+
+def bin_to_hex(target1, target2):
+    with open("romcode_total.bin", 'wb') as tmpf:
+        # write romcode_total.bin use target1
+        with open(target1, 'rb') as sf1:
+            in_size = 0
+            b = sf1.read(4)
+            while b:
+                tmpf.write(b)
+                in_size = in_size + len(b)
+                b = sf1.read(4)
+        while in_size < len1:
+            tmpf.write(b'\0')
+            in_size = in_size + 1
+
+        # continue write romcode_total.bin use target2
+        with open(target2, 'rb') as sf2:
+            in_size = 0
+            b = sf2.read(4)
+            while b:
+                tmpf.write(b)
+                in_size = in_size + len(b)
+                b = sf2.read(4)
+        while in_size < len2:
+            tmpf.write(b'\0')
+            in_size = in_size + 1
+        tmpf.flush()
+        tmpf.close()
+
+        time.sleep(1)
+        # split romcode_total use split_len
+        with open("romcode_total.bin", 'rb') as out_total:
+            file_index = 1
+            b = out_total.read(4)
+            while b:
+                out_name = 'romcode' + str(file_index) + '.hex'
+                print("" + out_name)
+                with open(out_name, 'w') as outf:
+                    in_size = 4
+                    while in_size <= split_len and b:
+                        outf.write('%02x%02x%02x%02x\n' % (b[3], b[2], b[1], b[0]))
+                        in_size = in_size + 4
+                        b = out_total.read(4)
+                    while in_size <= split_len:
+                        outf.write('%02x%02x%02x%02x\n' % (0, 0, 0, 0))
+                        in_size = in_size + 4
+                    outf.flush()
+                    outf.close()
+                file_index = file_index + 1
+
+
+if __name__ == "__main__":
+    bin_to_hex(sys.argv[1], sys.argv[2])
+
diff --git a/tools/rom_img/riscv3/sec_cpu_symbol b/tools/rom_img/riscv3/sec_cpu_symbol
new file mode 100644
index 0000000..793be28
--- /dev/null
+++ b/tools/rom_img/riscv3/sec_cpu_symbol
@@ -0,0 +1,3 @@
+g_sec_cpu_run_state
+g_crypto_share
+g_phy_cpu_share_ctxt
\ No newline at end of file