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app/chaokongbao/app_dev_drv/mcp_io_drv.h
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app/chaokongbao/app_dev_drv/mcp_io_drv.h
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#ifndef _INCLUDE_MCP_IO_DRV_H_
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#define _INCLUDE_MCP_IO_DRV_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MCP_SLAVER_ADDR (0x20)
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#define MCP_GPA 0x0
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#define MCP_GPB 0x1
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#define MCP_GPMAX 0x2
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/* 32 & 33 conflicted with LED_RX & LED_TX */
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#define MCP_SDA_GPIO 32
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#define MCP_SCL_GPIO 33
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#define MCP_MAX_GPIO_NUM_PER_PORT 8
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#define MCP_MAX_GPIO_NUM (MCP_MAX_GPIO_NUM_PER_PORT * MCP_GPMAX)
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#define MCP_GPIO_VALID(io) (((io) < MCP_MAX_GPIO_NUM && (io) >= 0) ? 1 : 0)
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/*
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GPIO <---> PORT
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0 GPA0
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1 GPA1
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2 GPA2
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3 GPA3
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4 GPA4
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5 GPA5
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6 GPA6
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7 GPA7
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8 GPB0
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9 GPB1
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10 GPB2
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11 GPB3
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12 GPB4
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13 GPB5
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14 GPB6
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15 GPB7
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*/
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/* mcp23017 register addr use bank = 0 ,here wo don't use bank = 1*/
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#define IODIRA (0x00)
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#define IPOLA (0x02)
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#define GPINTENA (0x04)
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#define DEFVALA (0x06)
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#define INTCONA (0x08)
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#define IOCONA (0x0A)
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#define GPPUA (0x0C)
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#define INTFA (0x0E)
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#define INTCAPA (0x10)
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#define GPIOA (0x12)
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#define OLATA (0x14)
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#define IODIRB (0x01)
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#define IPOLB (0x03)
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#define GPINTENB (0x05)
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#define DEFVALB (0x07)
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#define INTCONB (0x09)
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#define IOCONB (0x0B)
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#define GPPUB (0x0D)
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#define INTFB (0x0F)
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#define INTCAPB (0x11)
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#define GPIOB (0x13)
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#define OLATB (0x15)
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#define IO_2_GP(io) ((io) < MCP_MAX_GPIO_NUM_PER_PORT ? MCP_GPA : MCP_GPB)
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#define IO_SHIFT(io) ((io) < MCP_MAX_GPIO_NUM_PER_PORT ? (io) : (io) - MCP_MAX_GPIO_NUM_PER_PORT)
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/*
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Controls the direction of the data I/O.
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1 = Pin is configured as an input.
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0 = Pin is configured as an output.
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*/
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#define IODIR(io) (IO_2_GP(io) == MCP_GPA ? IODIRA : IODIRB)
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/*
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This register allows the user to configure the polarity on
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the corresponding GPIO port bits.
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1 = GPIO register bit will reflect the opposite logic state of the input pin.
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0 = GPIO register bit will reflect the same logic state of the input pin.
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*/
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#define IPOL(io) (IO_2_GP(io) == MCP_GPA ? IPOLA : IPOLB)
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/*
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The GPINTEN register controls the interrupt-onchange feature for each pin.
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1 = Enable GPIO input pin for interrupt-on-change event.
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0 = Disable GPIO input pin for interrupt-on-change event.
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*/
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#define GPINTEN(io) (IO_2_GP(io) == MCP_GPA ? GPINTENA : GPINTENB)
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/*
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The default comparison value is configured in the
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DEFVAL register. If enabled (via GPINTEN and
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INTCON) to compare against the DEFVAL register, an
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opposite value on the associated pin will cause an
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interrupt to occur.
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*/
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#define DEFVAL(io) (IO_2_GP(io) == MCP_GPA ? DEFVALA : DEFVALB)
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/*
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The INTCON register controls how the associated pin
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value is compared for the interrupt-on-change feature.
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If a bit is set, the corresponding I/O pin is compared
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against the associated bit in the DEFVAL register. If a
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bit value is clear, the corresponding I/O pin is compared
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against the previous value
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1 = The corresponding I/O pin is compared against the associated bit in
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the DEFVAL register.
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0 = Pin value is compared against the previous pin value.
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*/
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#define INTCON(io) (IO_2_GP(io) == MCP_GPA ? INTCONA : INTCONB)
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/*
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Keep default value.
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*/
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#define IOCON(io) (IO_2_GP(io) == MCP_GPA ? IOCONA : IOCONB)
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/*
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The GPPU register controls the pull-up resistors for the
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port pins. If a bit is set and the corresponding pin is
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configured as an input, the corresponding port pin is
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internally pulled up with a 100 kΩ resistor.
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1 = Pull-up enabled.
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0 = Pull-up disabled.
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*/
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#define GPPU(io) (IO_2_GP(io) == MCP_GPA ? GPPUA : GPPUB)
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/*
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The INTF register reflects the interrupt condition on the
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port pins of any pin that is enabled for interrupts via the
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GPINTEN register. A ‘set’ bit indicates that the
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associated pin caused the interrupt.
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1 = Pin caused interrupt.
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0 = Interrupt not pending.
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*/
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#define INTF(io) (IO_2_GP(io) == MCP_GPA ? INTFA : INTFB)
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/*
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The INTCAP register captures the GPIO port value at
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the time the interrupt occurred. The register is ‘read
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only’ and is updated only when an interrupt occurs. The
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register will remain unchanged until the interrupt is
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cleared via a read of INTCAP or GPIO.
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1 = Logic-high.
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0 = Logic-low
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*/
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#define INTCAP(io) (IO_2_GP(io) == MCP_GPA ? INTCAPA : INTCAPB)
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/*
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The GPIO register reflects the value on the port.
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Reading from this register reads the port. Writing to this
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register modifies the Output Latch (OLAT) register.
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1 = Logic-high.
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0 = Logic-low.
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*/
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#define GPIO(io) (IO_2_GP(io) == MCP_GPA ? GPIOA : GPIOB)
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/*
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The OLAT register provides access to the output
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latches. A read from this register results in a read of the
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OLAT and not the port itself. A write to this register
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modifies the output latches that modifies the pins
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configured as outputs.
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1 = Logic-high.
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0 = Logic-low.
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*/
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#define OLAT(io) (IO_2_GP(io) == MCP_GPA ? OLATA : OLATB)
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#define MCP_IO_BIT(io) (1 << IO_SHIFT(io))
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#define MCP_IO_SET(data, io) ((data) |= MCP_IO_BIT(io))
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#define MCP_IO_GET(data, io) (((data) & MCP_IO_BIT(io)) ? 1 : 0)
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#define MCP_IO_CLEAR(data, io) ((data) &= (~ MCP_IO_BIT(io)))
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enum mcp_gpio_mode
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{
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MCP_GPIO_INPUT,
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MCP_GPIO_OUTPUT
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};
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/**
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* @brief Modes of interrupt. Only when gpio_mode set as GPIO_INTERRUPT,
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* int_mode is available.
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*/
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enum mcp_gpio_int_trigger_mode
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{
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MCP_GPIO_RAISING, /**< Interrupt triggered when the voltage of this
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GPIO switchs from LOW to HIGH. */
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MCP_GPIO_FALLING, /**< Interrupt triggered when the voltage of this
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GPIO switchs from HIGH to LOW. */
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MCP_GPIO_BOTH_EDGE, /**< Interrupt triggered when the voltage of this GPIO
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switchs to HIGH or LOW . */
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MCP_GPIO_INVALID /**< Invalid value */
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};
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uint32_t mcp_gpio_get_value(uint32_t gpio);
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uint32_t mcp_gpio_set_value(uint32_t gpio, uint32_t val);
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uint32_t mcp_gpio_set_dir(uint32_t gpio, uint32_t dir);
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uint32_t mcp_gpio_set_interrupt(uint32_t gpio, uint32_t enable, uint32_t mode);
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uint32_t mcp_gpio_get_int_gpio(void);
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uint32_t mcp_gpio_set_pullup(uint32_t gpio, uint32_t enable);
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uint32_t mcp_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif/*__GPIO_EX_H*/
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