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andy
2024-09-28 14:24:04 +08:00
commit c756587541
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73
bb_cpu/common/bb_cpu_timer.c Normal file
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/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
****************************************************************************/
#include "bb_cpu_timer.h"
#include "hw_reg_api.h"
#include "rfplc_reg_base.h"
#include "rf_mac_reg.h"
#include "mac_sys_reg.h"
#include "mac_rf_isr.h"
extern rf_mac_isr_ctx_t g_rf_mac_isr_1;
uint32_t bb_cpu_timer_get_timeout_id()
{
return RF_MAC_READ_REG(CFG_RF_MAC_COMMON_TIMER_REG_7_ADDR);
}
void bb_cpu_timer_clr_timeout_id(uint32_t timer_sts)
{
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_TIMER_REG_5_ADDR, timer_sts);
}
void bb_cpu_timer_enable()
{
g_rf_mac_isr_1.isr_timer_mask = RF_MAC_COMMON_TIMER_CLR_CPU1_MASK;
/* enable all timer */
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_TIMER_REG_1_ADDR,
g_rf_mac_isr_1.isr_timer_mask);
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_TIMER_REG_9_ADDR,
g_rf_mac_isr_1.isr_timer_mask);
}
void bb_cpu_timer_disable()
{
g_rf_mac_isr_1.isr_timer_mask = 0;
/* disable all common timer */
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_TIMER_REG_1_ADDR, 0);
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_TIMER_REG_9_ADDR, 0);
/* clear all status */
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_TIMER_REG_5_ADDR,
RF_MAC_COMMON_TIMER_CLR_CPU1_MASK);
}
void bb_cpu_timer_start(uint32_t timer_id)
{
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_TIMER_REG_3_ADDR, (1 << timer_id));
}
void bb_cpu_timer_stop(uint32_t timer_id)
{
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_TIMER_REG_5_ADDR, (1 << timer_id));
}
void bb_cpu_timer_set(uint32_t timer_id, uint32_t time_us)
{
IOT_ASSERT(timer_id < BB_CPU_TIMER_MAX_ID &&
time_us < BB_CPU_TIMER_MAX_TIME_US);
uint32_t addr_base = CFG_RF_MAC_COMMON_TIMER_REG_42_ADDR;
RF_MAC_WRITE_REG(addr_base + (timer_id * 4), (time_us * 25));
}

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bb_cpu/common/bb_cpu_utils.c Normal file
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/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
****************************************************************************/
#include "bb_cpu_utils.h"

148
bb_cpu/common/rf_spi_api.c Normal file
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/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
***************************************************************************/
#include "iot_utils.h"
#include "spi.h"
#include "iot_errno_api.h"
#include "iot_io_api.h"
#include "iot_spi_api.h"
#include "spi.h"
#include "rf_spi_api.h"
#include "iot_board.h"
#include "iot_config.h"
#include "mac_rf_common_hw.h"
#define PHY_RF_SPI_PORT 1
#define SPI_SCPOL 0
#define SPI_SCPH 0
// max 50Mhz
#define RF_SPI_FREQUENCY 6*1000*1000
//8bit register address, 16bit register data
#define RF_SPI_WRITE_BUF_SIZE 3
//16bit register data
#define RF_SPI_READ_BUF_SIZE 2
/**
* rf default spi basic configuration.
*/
spi_cfg rf_spi_def_cfg = {
/* master mode. */
.dev_type = SPI_MASTER,
/* transmit and receive. */
.trs_mode = TMOD_TRANCIEVER,
/* standard spi mode. */
.frm_fmt = FRM_STD,
/* 8 data frame size for transmiting. */
.dfrm_sz = SPI_DFRAME_SIZE_8,
/* slave select enable. */
.cs_en = 0,
/* spi clk frequency. */
.frq = DEVICE_SPI_DEFAULT_FREQUENCY,
.rx_thd = DEVICE_SPI_DEFAULT_RX_THRESHOULD,
.tx_thd = DEVICE_SPI_DEFAULT_TX_THRESHOULD
};
/**
* rf Default spi timing configuration.
*/
tm_cfg rf_spi_time_cfg = {
/* clk polar high when spi is idle. */
.scpol = SPI_SCPOL,
/* the data transfer clock starts toggling in middle of first data. */
.scph = SPI_SCPH
};
static uint8_t rf_spi_init_flag = 0;
void rf_spi_init(void)
{
if (rf_spi_init_flag == 0) {
rf_spi_init_flag = 1;
} else {
return;
}
iot_spi_cfg_t cfg = {0};
uint8_t clk, cs, miso, mosi;
mac_rf_get_spi_gpio(&clk, &cs, &mosi, &miso);
cfg.gpio.clk = clk;
cfg.gpio.cs = cs;
cfg.gpio.miso = miso;
cfg.gpio.mosi = mosi;
cfg.port = PHY_RF_SPI_PORT;
if (ERR_OK != iot_spi_dev_open(&cfg)) {
rf_spi_init_flag = 0;
iot_printf("init port %d gpio fail.\r\n", cfg.port);
}
spi_cfg basic_cfg;
basic_cfg.dev_type = SPI_MASTER;
basic_cfg.dfrm_sz = SPI_DEFAULT_FRAM_SIZE;
basic_cfg.frm_fmt = FRM_STD;
basic_cfg.frq = RF_SPI_FREQUENCY;
basic_cfg.trs_mode = TMOD_TRANCIEVER;
basic_cfg.rx_thd = SPI_DEFAULT_RX_THR;
basic_cfg.tx_thd = SPI_DEFAULT_TX_THR;
basic_cfg.cs_en = 0;
/* Set spi basic cfg and time cfg. */
if (ERR_OK != iot_spi_dev_register_detail(
PHY_RF_SPI_PORT, &basic_cfg,&rf_spi_time_cfg, NULL, NULL, 0x0)) {
rf_spi_init_flag = 0;
iot_printf("[spi_DRV@%04d]:spi register failed!\n", __LINE__);
}
}
uint32_t rf_spi_write(uint8_t addr, uint16_t value)
{
xfer_buf spi_tx;
char tx_buf[RF_SPI_WRITE_BUF_SIZE] = {0};
os_mem_set(&spi_tx, 0, sizeof(xfer_buf));
tx_buf[0] = addr & 0x7F;
tx_buf[2] = value & 0xFF;
tx_buf[1] = (value >> 8) & 0xFF;
spi_tx.p_nt = NULL;
spi_tx.txbuf = tx_buf;
spi_tx.size = RF_SPI_WRITE_BUF_SIZE;
return iot_spi_poll_transfer(PHY_RF_SPI_PORT, &spi_tx);
}
uint16_t rf_spi_read(uint8_t addr)
{
char cmd_buf[4];
char p_buf[RF_SPI_READ_BUF_SIZE];
xfer_buf x_buf[2];
os_mem_set(x_buf, 0, sizeof(x_buf));
x_buf[0].p_nt = &x_buf[1];
x_buf[0].size = 1;
x_buf[0].txbuf = cmd_buf;
x_buf[1].p_nt = NULL;
x_buf[1].size = RF_SPI_READ_BUF_SIZE;
x_buf[1].rxbuf = (char *)p_buf;
cmd_buf[0] = addr|0x80;
iot_spi_poll_transfer(PHY_RF_SPI_PORT, x_buf);
return (p_buf[0] << 8) | p_buf[1];
}