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andy
2024-09-28 14:24:04 +08:00
commit c756587541
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bb_cpu/mac/bb_cpu_hw_ring.c Normal file
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/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
****************************************************************************/
/* os shim includes */
#include "iot_config.h"
#include "os_types.h"
#include "iot_mem.h"
/* plc public api includes */
#include "plc_fr.h"
#include "plc_const.h"
#include "iot_bitops.h"
/* driver includes */
#include "iot_irq.h"
#include "iot_gpio_api.h"
#include "iot_board_api.h"
#include "pin_rf.h"
#include "iot_io.h"
#include "bb_cpu_hw_ring.h"
#include "mac.h"
#include "mac_rf_hwq_mgr.h"
#include "rfplc_reg_base.h"
#include "hw_reg_api.h"
#include "bb_cpu_mac_isr.h"
#include "bb_cpu_timer.h"
#include "rf_mac_reg.h"
#include "mac_sys_reg.h"
#include "mac_cmn_hw.h"
#include "bb_cpu_config.h"
#include "bb_rf_cfg.h"
#include "rf_mac_int.h"
#include "rf_hw_tonemap.h"
#include "rf_mac_rx_reg.h"
#include "mac_rf_rx_buf_ring.h"
#include "bb_cpu_hw_ring.h"
#include "mac_rf_common_hw.h"
#include "bb_cpu_mac_init.h"
#include "bb_cpu_fsm.h"
#define BB_CPU_HW_RING_ID_INVALID MAX_RF_RX_RING_NUM
#define RF_BUF_RINGX_OFFSET \
(RF_BUFFER_RING1_0_ADDR - RF_BUFFER_RING0_0_ADDR)
/* get hw ring rx buffer list address */
#define bb_cpu_hw_ring_list_get(r_id) \
((uint8_t **)REG_FIELD_GET(CFG_RF_RING0_PTR, \
RGF_RF_RX_READ_REG(RF_BUFFER_RING0_0_ADDR + (r_id * RF_BUF_RINGX_OFFSET))))
/* get hw ring is enable or disable */
#define bb_cpu_hw_ring_is_enable(r_id) \
(REG_FIELD_GET(CFG_RF_RING0_EN, RGF_RF_RX_READ_REG(RF_BUFFER_RING0_2_ADDR \
+ ((r_id) * RF_BUF_RINGX_OFFSET))))
/* get hw ring buffer size, unit: 1byte */
#define bb_cpu_hw_ring_sz_get(r_id) \
(REG_FIELD_GET(CFG_RF_RING0_BUF_SIZE, \
RGF_RF_RX_READ_REG(RF_BUFFER_RING0_1_ADDR \
+ ((r_id) * RF_BUF_RINGX_OFFSET))) << 2)
/* get hw rfmac hw ring read index */
#define bb_cpu_hw_ring_ridx_get(r_id) \
(REG_FIELD_GET(CFG_RF_RING0_RD_IDX, \
RGF_RF_RX_READ_REG(RF_BUFFER_RING0_2_ADDR + (r_id * RF_BUF_RINGX_OFFSET))))
/* get rf ring buffer write index */
#define bb_cpu_hw_ring_reg_wr_idx_get(r_id, reg_idx) \
REG_FIELD_GET(RO_RF_RING##r_id##_MPDU_BUF_WR_IDX, \
RGF_RF_RX_READ_REG(RX_BUF_RING_WR_IDX_##reg_idx##_ADDR))
typedef struct _mac_hw_ring_ctxt {
/* current select ring id */
uint8_t ring_id;
/* ring is enable or disable */
uint8_t enable;
/* reserved */
uint16_t rsvd1;
/* current ring rx desc address */
uint8_t *rx_desc;
} bb_cpu_hw_ring_ctxt_t;
/* tmp buf */
uint8_t bb_cpu_buf[520] = { 0 };
#if BB_CPU_HW_RING_ENABLE
static bb_cpu_hw_ring_ctxt_t hw_ring_ctxt = {0};
static uint8_t bb_cpu_hw_ring_id_get(uint32_t payload_len, uint8_t *ring_id)
{
uint8_t id;
uint8_t target_id;
uint32_t target_ring_sz;
uint32_t ring_sz;
target_id = BB_CPU_HW_RING_ID_INVALID;
target_ring_sz = 0;
for (id = 0; id < MAX_RF_RX_RING_NUM; id++) {
/* check ring is enable */
if (!bb_cpu_hw_ring_is_enable(id)) {
continue;
}
/* check rx buffer valid */
if (!bb_cpu_hw_ring_list_get(id)) {
continue;
}
/* get ring buffer byte size */
ring_sz = bb_cpu_hw_ring_sz_get(id);
if (payload_len <= ring_sz) {
if (target_id == BB_CPU_HW_RING_ID_INVALID) {
target_id = id;
target_ring_sz = ring_sz;
} else {
if (ring_sz < target_ring_sz) {
target_id = id;
target_ring_sz = ring_sz;
}
}
}
/* TODO: add more select ring buffer method */
}
if (target_id == BB_CPU_HW_RING_ID_INVALID) {
return ERR_FAIL;
}
*ring_id = target_id;
return ERR_OK;
}
static uint32_t bb_cpu_hw_ring_widx_get(uint8_t ring_id)
{
uint32_t widx;
switch (ring_id) {
case 0:
widx = bb_cpu_hw_ring_reg_wr_idx_get(0, 0);
break;
case 1:
widx = bb_cpu_hw_ring_reg_wr_idx_get(1, 0);
break;
case 2:
widx = bb_cpu_hw_ring_reg_wr_idx_get(2, 0);
break;
case 3:
widx = bb_cpu_hw_ring_reg_wr_idx_get(3, 1);
break;
case 4:
widx = bb_cpu_hw_ring_reg_wr_idx_get(4, 1);
break;
case 5:
widx = bb_cpu_hw_ring_reg_wr_idx_get(5, 1);
break;
default:
IOT_ASSERT(0);
widx = 0;
break;
}
return widx;
}
static void bb_cpu_hw_ring_widx_set(uint8_t ring_id, int32_t offset)
{
uint32_t tmp, buf_num;
int32_t widx;
switch (ring_id) {
case 0:
tmp = RGF_RF_RX_READ_REG(RX_BUF_RING_WR_IDX_0_ADDR);
widx = REG_FIELD_GET(RO_RF_RING0_MPDU_BUF_WR_IDX, tmp) + offset;
buf_num = REG_FIELD_GET(CFG_RF_RING0_BUF_NUM,
RGF_RF_RX_READ_REG(RF_BUFFER_RING0_1_ADDR));
if (widx >= buf_num) {
widx = 0;
}
REG_FIELD_SET(RO_RF_RING0_MPDU_BUF_WR_IDX, tmp, widx);
RGF_RF_RX_WRITE_REG(RX_BUF_RING_WR_IDX_0_ADDR, tmp);
break;
case 1:
tmp = RGF_RF_RX_READ_REG(RX_BUF_RING_WR_IDX_0_ADDR);
widx = REG_FIELD_GET(RO_RF_RING1_MPDU_BUF_WR_IDX, tmp) + offset;
buf_num = REG_FIELD_GET(CFG_RF_RING1_BUF_NUM,
RGF_RF_RX_READ_REG(RF_BUFFER_RING1_1_ADDR));
if (widx >= buf_num) {
widx = 0;
}
REG_FIELD_SET(RO_RF_RING1_MPDU_BUF_WR_IDX, tmp, widx);
RGF_RF_RX_WRITE_REG(RX_BUF_RING_WR_IDX_0_ADDR, tmp);
break;
case 2:
tmp = RGF_RF_RX_READ_REG(RX_BUF_RING_WR_IDX_0_ADDR);
widx = REG_FIELD_GET(RO_RF_RING2_MPDU_BUF_WR_IDX, tmp) + offset;
buf_num = REG_FIELD_GET(CFG_RF_RING2_BUF_NUM,
RGF_RF_RX_READ_REG(RF_BUFFER_RING2_1_ADDR));
if (widx >= buf_num) {
widx = 0;
}
REG_FIELD_SET(RO_RF_RING2_MPDU_BUF_WR_IDX, tmp, widx);
RGF_RF_RX_WRITE_REG(RX_BUF_RING_WR_IDX_0_ADDR, tmp);
break;
case 3:
tmp = RGF_RF_RX_READ_REG(RX_BUF_RING_WR_IDX_1_ADDR);
widx = REG_FIELD_GET(RO_RF_RING3_MPDU_BUF_WR_IDX, tmp) + offset;
buf_num = REG_FIELD_GET(CFG_RF_RING3_BUF_NUM,
RGF_RF_RX_READ_REG(RF_BUFFER_RING3_1_ADDR));
if (widx >= buf_num) {
widx = 0;
}
REG_FIELD_SET(RO_RF_RING3_MPDU_BUF_WR_IDX, tmp, widx);
RGF_RF_RX_WRITE_REG(RX_BUF_RING_WR_IDX_1_ADDR, tmp);
break;
case 4:
tmp = RGF_RF_RX_READ_REG(RX_BUF_RING_WR_IDX_1_ADDR);
widx = REG_FIELD_GET(RO_RF_RING4_MPDU_BUF_WR_IDX, tmp) + offset;
buf_num = REG_FIELD_GET(CFG_RF_RING4_BUF_NUM,
RGF_RF_RX_READ_REG(RF_BUFFER_RING4_1_ADDR));
if (widx >= buf_num) {
widx = 0;
}
REG_FIELD_SET(RO_RF_RING4_MPDU_BUF_WR_IDX, tmp, widx);
RGF_RF_RX_WRITE_REG(RX_BUF_RING_WR_IDX_1_ADDR, tmp);
break;
case 5:
tmp = RGF_RF_RX_READ_REG(RX_BUF_RING_WR_IDX_1_ADDR);
widx = REG_FIELD_GET(RO_RF_RING5_MPDU_BUF_WR_IDX, tmp) + offset;
buf_num = REG_FIELD_GET(CFG_RF_RING5_BUF_NUM,
RGF_RF_RX_READ_REG(RF_BUFFER_RING5_1_ADDR));
if (widx >= buf_num) {
widx = 0;
}
REG_FIELD_SET(RO_RF_RING5_MPDU_BUF_WR_IDX, tmp, widx);
RGF_RF_RX_WRITE_REG(RX_BUF_RING_WR_IDX_1_ADDR, tmp);
break;
default:
IOT_ASSERT(0);
break;
}
}
static uint8_t *bb_cpu_hw_ring_rx_desc_get(uint8_t ring_id)
{
uint32_t r_idx, w_idx;
uint8_t **list;
w_idx = bb_cpu_hw_ring_widx_get(ring_id);
r_idx = bb_cpu_hw_ring_ridx_get(ring_id);
/* check watermake */
(void)r_idx;
list = bb_cpu_hw_ring_list_get(ring_id);
return list[w_idx];
}
static uint32_t bb_cpu_hw_ring_ctxt_reset(void)
{
hw_ring_ctxt.ring_id = BB_CPU_HW_RING_ID_INVALID;
hw_ring_ctxt.enable = 0;
hw_ring_ctxt.rx_desc = NULL;
return ERR_OK;
}
uint8_t *bb_cpu_hw_ring_select(void *phr_info)
{
uint8_t ring_id;
uint32_t pb_sz, pb_num, ret, is_sack = 0;
uint8_t *rx_desc, *payload_addr = NULL;
rf_rx_attention *att;
rf_rx_mpdu_start *mpdu_st;
rf_rx_mpdu_end *mpdu_ed;
rf_rx_pb_end *pb_ed;
/* reset hw ring context */
bb_cpu_hw_ring_ctxt_reset();
if (phr_info) {
bb_cpu_rf_fc_t fc_msg = {0};
bb_cpu_mac_get_msg_from_phr(bb_cpu_get_proto(), phr_info, &fc_msg);
if (fc_msg.delimiter == FC_DELIM_BEACON ||
fc_msg.delimiter == FC_DELIM_SOF) {
pb_num = 1;
pb_sz = phy_rf_get_pbsz(fc_msg.rf_pb_sz_idx);
} else if (fc_msg.delimiter == FC_DELIM_SACK) {
is_sack = 1;
pb_num = 0;
pb_sz = 0;
} else {
pb_num = 0;
pb_sz = 0;
}
} else {
pb_num = 0;
pb_sz = 0;
}
/* sta sack need ring */
if (mac_get_hw_role() && is_sack && !mac_rf_get_cert_mode()) {
return bb_cpu_buf;
}
/* base on phr get ring id */
ret = bb_cpu_hw_ring_id_get(pb_num * pb_sz, &ring_id);
if (ret) {
/* ring is not enable, not care data.
* use bb_cpu_buf.
*/
return bb_cpu_buf;
}
/* get desc address base on ring id */
rx_desc = bb_cpu_hw_ring_rx_desc_get(ring_id);
IOT_ASSERT(rx_desc);
att = (rf_rx_attention *)(rx_desc + RF_RX_ATTENTION_OFFSET);
mpdu_st = (rf_rx_mpdu_start *)(rx_desc + RF_RX_MPDU_START_OFFSET);
mpdu_ed = (rf_rx_mpdu_end *)(rx_desc + RF_RX_MPDU_END_OFFSET);
pb_ed = (rf_rx_pb_end *)(rx_desc + RF_RX_PB_END_OFFSET);
IOT_ASSERT(att->rx_mpdu_done == 0);
IOT_ASSERT(mpdu_ed->rx_mpdu_done == 0);
IOT_ASSERT(pb_ed->rx_pb_done == 0);
if (phr_info) {
/* update info to mpdu start desc */
mac_rf_rx_mpdu_st_set_phr(mpdu_st, (uint8_t *)phr_info);
}
hw_ring_ctxt.ring_id = ring_id;
hw_ring_ctxt.rx_desc = rx_desc;
if (pb_num) {
payload_addr = rx_desc + RF_RX_PB_PAYLOAD_OFFSET;
} else {
payload_addr = NULL;
}
hw_ring_ctxt.enable = 1;
return payload_addr;
}
uint32_t bb_cpu_hw_ring_set_rx_status(uint32_t rx_status)
{
uint8_t *rx_desc;
rf_rx_attention *att;
if (!hw_ring_ctxt.enable) {
return ERR_FAIL;
}
IOT_ASSERT(hw_ring_ctxt.ring_id != BB_CPU_HW_RING_ID_INVALID);
rx_desc = hw_ring_ctxt.rx_desc;
IOT_ASSERT(rx_desc);
att = (rf_rx_attention *)(rx_desc + RF_RX_ATTENTION_OFFSET);
/* update att status */
mac_rf_rx_att_set_rx_status(att, rx_status);
return ERR_OK;
}
uint32_t bb_cpu_hw_ring_set_tx_sack_status(uint32_t tx_sack_status)
{
uint8_t *rx_desc;
rf_rx_attention *att;
if (!hw_ring_ctxt.enable) {
return ERR_FAIL;
}
IOT_ASSERT(hw_ring_ctxt.ring_id != BB_CPU_HW_RING_ID_INVALID);
rx_desc = hw_ring_ctxt.rx_desc;
IOT_ASSERT(rx_desc);
att = (rf_rx_attention *)(rx_desc + RF_RX_ATTENTION_OFFSET);
/* update att status */
mac_rf_rx_att_set_tx_sack_status(att, tx_sack_status);
return ERR_OK;
}
static uint32_t bb_cpu_hw_judge_pld_ok(void *phr, int16_t *dlt)
{
int16_t dlt_tmp;
uint32_t pld_crc = 1, pld_fl_from_rd, pld_fl_from_phr = 0;
/* pld fl from record, interrupt pld - interrupt phr */
pld_fl_from_rd = bb_cpu_mac_get_rx_pld_start_local_ntb() -
bb_cpu_mac_get_rx_phr_local_ntb();
bb_cpu_rf_fc_t fc_msg = {0};
bb_cpu_mac_get_msg_from_phr(bb_cpu_get_proto(), phr, &fc_msg);
if (FC_DELIM_BEACON == fc_msg.delimiter ||
FC_DELIM_SOF == fc_msg.delimiter) {
pld_fl_from_phr = phy_rf_get_g_psdu_fl_ntb(fc_msg.rf_mcs,
fc_msg.rf_pb_sz_idx);
} else {
IOT_ASSERT(0);
}
/* judge */
dlt_tmp = pld_fl_from_rd - pld_fl_from_phr;
if (IOT_ABS(dlt_tmp) <= 5) {
pld_crc = 0;
}
*dlt = dlt_tmp;
return pld_crc;
}
uint32_t bb_cpu_hw_ring_rx_complete_cfg_desc(void)
{
uint32_t pb_size = 0, pb_crc_invaild = 0;
uint8_t *rx_desc;
rf_rx_attention *att;
rf_rx_mpdu_start *mpdu_st;
rf_rx_mpdu_end *mpdu_ed;
rf_rx_pb_start *pb_st;
rf_rx_pb_end *pb_ed;
uint8_t *payload, *crc_addr;
int16_t dlt;
if (!hw_ring_ctxt.enable) {
return ERR_FAIL;
}
IOT_ASSERT(hw_ring_ctxt.ring_id != BB_CPU_HW_RING_ID_INVALID);
rx_desc = hw_ring_ctxt.rx_desc;
IOT_ASSERT(rx_desc);
att = (rf_rx_attention *)(rx_desc + RF_RX_ATTENTION_OFFSET);
mpdu_st = (rf_rx_mpdu_start *)(rx_desc + RF_RX_MPDU_START_OFFSET);
mpdu_ed = (rf_rx_mpdu_end *)(rx_desc + RF_RX_MPDU_END_OFFSET);
pb_st = (rf_rx_pb_start *)(rx_desc + RF_RX_PB_START_OFFSET);
pb_ed = (rf_rx_pb_end *)(rx_desc + RF_RX_PB_END_OFFSET);
payload = (uint8_t *)(rx_desc + RF_RX_PB_PAYLOAD_OFFSET);
/* update att desc */
switch (mac_rf_rx_att_get_rx_status(att)) {
case BB_CPU_RX_RING_SIG_ERR:
att->sig_crc_err = 1;
break;
case BB_CPU_RX_RING_PHR_ERR:
case BB_CPU_RX_RING_PHR_TIMEOUT:
case BB_CPU_RX_RING_WAIT_PHR_RX_ABORT:
case BB_CPU_RX_RING_WAIT_PHR_RESET:
att->phr_crc_err = 1;
break;
case BB_CPU_RX_RING_WAIT_PLD_TIMEOUT:
case BB_CPU_RX_RING_WAIT_PLD_RX_ABORT:
case BB_CPU_RX_RING_WAIT_PLD_RESET:
case BB_CPU_RX_RING_WAIT_PLD_RESET_TIMEOUT:
pb_crc_invaild = 1;
break;
default:
att->sig_crc_err = 0;
att->phr_crc_err = 0;
break;
}
if (!att->sig_crc_err) {
/* SIG info */
mac_rf_rx_att_set_phr_mcs(att, bb_rf_get_rx_sig_info());
}
if (!att->phr_crc_err) {
/* update mpdu start desc */
void *phr = mac_rf_rx_mpdu_st_get_phr_addr(mpdu_st);
bb_cpu_rf_fc_t fc_msg = {0};
bb_cpu_mac_get_msg_from_phr(bb_cpu_get_proto(), phr, &fc_msg);
/* update pb end desc */
switch (fc_msg.delimiter) {
case FC_DELIM_BEACON:
mac_rf_rx_att_set_pb_num(att, 1);
mac_rf_rx_att_set_pld_mcs(att, fc_msg.rf_mcs);
mac_rf_rx_pb_st_set_rx_pb_cnt(pb_st, 1);
mac_rf_rx_pb_st_set_pb_sz_idx(pb_st, fc_msg.rf_pb_sz_idx);
if (pb_crc_invaild) {
pb_ed->rx_beacon_pld_crc_err = 1;
pb_ed->rx_pb_crc_err = 1;
mac_rf_rx_pb_end_set_mismatch_dlt(pb_ed, 0);
} else {
pb_size = phy_rf_get_pbsz(fc_msg.rf_pb_sz_idx);
crc_addr = (uint8_t *)(payload + pb_size - SG_BCN_PB_CRC_LEN);
pb_ed->pb_crc = (uint32_t)crc_addr[0] +
((uint32_t)crc_addr[1] << 8) + ((uint32_t)crc_addr[2] << 16);
pb_ed->rx_beacon_pld_crc_err = !!bb_rf_get_pld_crc32_err();
pb_ed->rx_pb_crc_err = !!bb_rf_get_pld_crc24_err();
if (pb_ed->rx_pb_crc_err == 0) {
//pb_ed->rx_pb_crc_err = bb_cpu_hw_judge_pld_ok(phr, &dlt);
bb_cpu_hw_judge_pld_ok(phr, &dlt);
mac_rf_rx_pb_end_set_mismatch_dlt(pb_ed, dlt);
}
}
break;
case FC_DELIM_SOF:
mac_rf_rx_att_set_pb_num(att, 1);
mac_rf_rx_att_set_pld_mcs(att, fc_msg.rf_mcs);
mac_rf_rx_pb_st_set_rx_pb_cnt(pb_st, 1);
mac_rf_rx_pb_st_set_pb_sz_idx(pb_st, fc_msg.rf_pb_sz_idx);
mac_rf_rx_pb_st_set_first_pb(pb_st, 1);
mac_rf_rx_pb_st_set_last_pb(pb_st, 1);
if (pb_crc_invaild) {
pb_ed->rx_pb_crc_err = 1;
mac_rf_rx_pb_end_set_mismatch_dlt(pb_ed, 0);
} else {
/* update pb start desc */
pb_size = phy_rf_get_pbsz(fc_msg.rf_pb_sz_idx);
#if SUPPORT_SMART_GRID
if (PLC_PROTO_TYPE_SG == bb_cpu_get_proto()) {
sg_sof_pb_hdr_t *pb_hdr = (sg_sof_pb_hdr_t *)payload;
mac_rf_rx_pb_st_set_pb_ssn(pb_st, pb_hdr->seq);
mac_rf_rx_pb_st_set_msdu_start(pb_st,
pb_hdr->mac_frame_start);
mac_rf_rx_pb_st_set_msdu_end(pb_st, pb_hdr->mac_frame_end);
crc_addr =
(uint8_t *)(payload + pb_size - SG_SOF_PB_CRC_LEN);
pb_ed->pb_crc = (uint32_t)crc_addr[0] +
((uint32_t)crc_addr[1] << 8) +
((uint32_t)crc_addr[2] << 16);
if (!mac_rf_get_pb_hdr_to_buf()) {
os_mem_cpy(payload, payload + SG_SOF_PB_HDR_LEN,
pb_size - SG_SOF_PB_HDR_LEN);
}
} else
#endif
#if SUPPORT_SOUTHERN_POWER_GRID
if (PLC_PROTO_TYPE_SPG == bb_cpu_get_proto()) {
/* update pb start desc */
spg_sof_pb_hdr_t *pb_hdr = (spg_sof_pb_hdr_t *)payload;
mac_rf_rx_pb_st_set_pb_ssn(pb_st, pb_hdr->seq);
mac_rf_rx_pb_st_set_msdu_start(pb_st, 1);
mac_rf_rx_pb_st_set_msdu_end(pb_st, 1);
crc_addr =
(uint8_t *)(payload + pb_size - SPG_SOF_PB_CRC_LEN);
pb_ed->pb_crc = (uint32_t)crc_addr[0] +
((uint32_t)crc_addr[1] << 8) +
((uint32_t)crc_addr[2] << 16);
if (!mac_rf_get_pb_hdr_to_buf()) {
os_mem_cpy(payload, payload + SPG_SOF_PB_HDR_LEN,
pb_size - SPG_SOF_PB_HDR_LEN);
}
} else
#endif
{
//do not delete this case
}
pb_ed->rx_pb_crc_err = !!bb_rf_get_pld_crc24_err();
if (pb_ed->rx_pb_crc_err == 0) {
//pb_ed->rx_pb_crc_err = bb_cpu_hw_judge_pld_ok(phr, &dlt);
bb_cpu_hw_judge_pld_ok(phr, &dlt);
mac_rf_rx_pb_end_set_mismatch_dlt(pb_ed, dlt);
}
}
break;
case FC_DELIM_SACK:
pb_ed->rx_beacon_pld_crc_err = 0;
pb_ed->rx_pb_crc_err = 0;
pb_ed->pb_crc = 0;
break;
default:
break;
}
}
mac_rf_rx_att_set_channel_id(att, mac_rf_get_cur_channel_id());
mac_rf_rx_att_set_option(att, mac_rf_get_option());
/* update mpdu end desc */
mpdu_ed->ntb_timestamp = bb_cpu_mac_get_rx_stf_ntb() -
BB_CPU_RX_GOLDEN_GAP(mac_rf_get_option());
mpdu_ed->local_timestamp = bb_cpu_mac_get_rx_stf_local_ntb() -
BB_CPU_RX_GOLDEN_GAP(mac_rf_get_option());
return ERR_OK;
}
uint32_t bb_cpu_hw_ring_rx_done_set(void)
{
rf_rx_attention *att;
rf_rx_mpdu_end *mpdu_ed;
rf_rx_pb_end *pb_ed;
if (!hw_ring_ctxt.enable) {
bb_cpu_hw_ring_ctxt_reset();
return ERR_FAIL;
}
IOT_ASSERT(hw_ring_ctxt.ring_id != BB_CPU_HW_RING_ID_INVALID);
/* update rx done */
att = (rf_rx_attention *)(hw_ring_ctxt.rx_desc + RF_RX_ATTENTION_OFFSET);
mpdu_ed = (rf_rx_mpdu_end *)(hw_ring_ctxt.rx_desc + RF_RX_MPDU_END_OFFSET);
pb_ed = (rf_rx_pb_end *)(hw_ring_ctxt.rx_desc + RF_RX_PB_END_OFFSET);
att->rx_mpdu_done = 1;
mpdu_ed->rx_mpdu_done = 1;
pb_ed->rx_pb_done = 1;
/* update write idx */
bb_cpu_hw_ring_widx_set(hw_ring_ctxt.ring_id, 1);
/* notify plc cpu rx done */
bb_cpu_mac_set_share_irq_to_maincpu(hw_ring_ctxt.ring_id +
RF_MAC_INT_RX_RING_BIT_OFFSET);
bb_cpu_mac_set_sw_irq_to_maincpu(RF_MAC_SW_ISR_RX_MPDU_COMPLETE);
bb_cpu_hw_ring_ctxt_reset();
return ERR_OK;
}
#if HPLC_BBCPU_CALC_SNR_RSSI
void bb_cpu_hw_ring_snr_set(int8_t snr)
{
rf_rx_mpdu_start *mpdu_st;
if (!hw_ring_ctxt.enable) {
return;
}
mpdu_st = (rf_rx_mpdu_start *)(hw_ring_ctxt.rx_desc
+ RF_RX_MPDU_START_OFFSET);
mac_rf_rx_mpdu_st_set_avg_snr(mpdu_st, snr);
}
void bb_cpu_hw_ring_raw_snr_set(uint16_t snr)
{
rf_rx_mpdu_start *mpdu_st;
if (!hw_ring_ctxt.enable) {
return;
}
mpdu_st = (rf_rx_mpdu_start *)(hw_ring_ctxt.rx_desc
+ RF_RX_MPDU_START_OFFSET);
mac_rf_rx_mpdu_st_set_raw_snr(mpdu_st, snr);
}
void bb_cpu_hw_ring_rssi_set(int8_t rssi)
{
rf_rx_mpdu_start *mpdu_st;
if (!hw_ring_ctxt.enable) {
return;
}
mpdu_st = (rf_rx_mpdu_start *)(hw_ring_ctxt.rx_desc
+ RF_RX_MPDU_START_OFFSET);
mac_rf_rx_mpdu_st_set_rssi(mpdu_st, rssi);
}
void bb_cpu_hw_ring_rx_gain_set(uint8_t rx_gain)
{
rf_rx_mpdu_start *mpdu_st;
if (!hw_ring_ctxt.enable) {
return;
}
mpdu_st = (rf_rx_mpdu_start *)(hw_ring_ctxt.rx_desc
+ RF_RX_MPDU_START_OFFSET);
mac_rf_rx_mpdu_st_set_rx_gain(mpdu_st, rx_gain);
}
#else /* HPLC_BBCPU_CALC_SNR_RSSI */
void bb_cpu_hw_ring_raw_snr_rssi_set(uint32_t raw_snr_rssi_reg1,
uint32_t raw_snr_rssi_reg2, uint32_t raw_snr_rssi_reg3)
{
rf_rx_mpdu_start *mpdu_st;
if (!hw_ring_ctxt.enable) {
return;
}
mpdu_st = (rf_rx_mpdu_start *)(hw_ring_ctxt.rx_desc
+ RF_RX_MPDU_START_OFFSET);
mac_rf_rx_mpdu_st_set_raw_snr_rssi_reg1(mpdu_st, raw_snr_rssi_reg1);
mac_rf_rx_mpdu_st_set_raw_snr_rssi_reg2(mpdu_st, raw_snr_rssi_reg2);
mac_rf_rx_mpdu_st_set_raw_snr_rssi_reg3(mpdu_st, raw_snr_rssi_reg3);
}
#endif /* HPLC_BBCPU_CALC_SNR_RSSI */
void bb_cpu_hw_ring_rx_ppmhz_set(int32_t rx_ppm_hz)
{
rf_rx_mpdu_start *mpdu_st;
if (!hw_ring_ctxt.enable) {
return;
}
mpdu_st = (rf_rx_mpdu_start *)(hw_ring_ctxt.rx_desc
+ RF_RX_MPDU_START_OFFSET);
mac_rf_rx_mpdu_st_set_rx_ppmhz(mpdu_st, rx_ppm_hz);
}
void bb_cpu_hw_ring_init(void)
{
//TODO: add init ring buffer reg code
bb_cpu_hw_ring_ctxt_reset();
}
#else /* !BB_CPU_HW_RING_ENABLE */
uint8_t *bb_cpu_hw_ring_select(void *phr_info)
{
(void)phr_info;
return bb_cpu_buf;
}
uint32_t bb_cpu_hw_ring_set_rx_status(uint32_t rx_status)
{
(void)rx_status;
return ERR_OK;
}
uint32_t bb_cpu_hw_ring_set_tx_sack_status(uint32_t tx_sack_status)
{
(void)rx_status;
return ERR_OK;
}
uint32_t bb_cpu_hw_ring_rx_complete_cfg_desc(void)
{
return ERR_OK;
}
uint32_t bb_cpu_hw_ring_rx_done_set(void)
{
uint32_t ring_id = 0;
bb_cpu_mac_set_share_irq_to_maincpu(ring_id + RF_MAC_INT_RX_RING_BIT_OFFSET);
bb_cpu_mac_set_sw_irq_to_maincpu(RF_MAC_SW_ISR_RX_MPDU_COMPLETE);
return ERR_OK;
}
void bb_cpu_hw_ring_snr_set(int8_t snr)
{
(void)snr;
}
void bb_cpu_hw_ring_raw_snr_set(uint16_t snr)
{
(void)snr;
}
void bb_cpu_hw_ring_rssi_set(int8_t rssi)
{
(void)rssi;
}
void bb_cpu_hw_ring_rx_gain_set(uint8_t rx_gain)
{
(void)rx_gain;
}
void bb_cpu_hw_ring_rx_ppmhz_set(int32_t rx_ppm_hz)
{
(void)rx_ppm_hz;
}
void bb_cpu_hw_ring_init(void)
{
}
#endif /* BB_CPU_HW_RING_ENABLE */

686
bb_cpu/mac/bb_cpu_mac_init.c Normal file
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@@ -0,0 +1,686 @@
/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
****************************************************************************/
/* os shim includes */
#include "iot_config.h"
#include "os_types.h"
#include "iot_mem.h"
/* plc public api includes */
#include "plc_fr.h"
#include "plc_const.h"
#include "iot_bitops.h"
/* driver includes */
#include "iot_irq.h"
#include "iot_gpio_api.h"
#include "iot_board_api.h"
#include "pin_rf.h"
#include "iot_io.h"
#include "bb_cpu_utils.h"
#include "mac.h"
#include "mac_rf_hwq_mgr.h"
#include "mac_rf_txq_hw.h"
#include "rfplc_reg_base.h"
#include "hw_reg_api.h"
#include "bb_cpu_mac_init.h"
#include "bb_cpu_mac_isr.h"
#include "bb_cpu_timer.h"
#include "bb_cpu_fsm.h"
#include "rf_mac_reg.h"
#include "mac_sys_reg.h"
#include "bb_rf_cfg.h"
#include "bb_cpu_hw_ring.h"
#include "mac_rf_common_hw.h"
#include "wmac_reg.h"
#include "bb_cpu_config.h"
#include "mpdu_header.h"
#define BB_CPU_CHECK_WMAC_FSM_DUE_TO_CMDLIST_DONE 1
#define BB_CPU_CHECK_WMAC_FSM_DUE_TO_EARLY_STOP 2
uint32_t bb_cpu_mac_get_txq_ptr()
{
return RF_MAC_READ_REG(CFG_RF_MAC_CUR_TX_PTR_ADDR);
}
uint32_t bb_cpu_mac_get_rx_crc32_check()
{
// TODO: get rx crc32 need check or not
return 0;
}
uint32_t bb_cpu_mac_get_cur_hwqid()
{
uint32_t tmp, sel_bitmap, hwq_id = MAX_MAC_RF_TXQ_NUM;
tmp = RF_MAC_READ_REG(CFG_RF_MAC_DEBUG_BUS0_ADDR);
sel_bitmap = REG_FIELD_GET(RF_MAC_TXQ_SEL_BIT_MAP, tmp);
if (sel_bitmap) {
hwq_id = iot_bitops_fls(sel_bitmap) - 1;
if (sel_bitmap & (~(1 << hwq_id))) {
iot_printf("selbit err:0x%x, cmdbitmap:0x%x\n", sel_bitmap,
REG_FIELD_GET(RF_MAC_TXQ_BITMAP_2CPU2, tmp));
IOT_ASSERT(0);
}
} else {
iot_printf("selbit is 0\n");
IOT_ASSERT(0);
}
return hwq_id;
}
uint32_t bb_cpu_mac_judge_cur_cmd_need_tx_csma()
{
uint32_t tmp, txq_bit_map, ret = 0;
if (mac_rf_txq_is_dbg_mode()) {
tmp = RF_MAC_READ_REG(CFG_RF_MAC_DEBUG_CFG_ADDR);
txq_bit_map = REG_FIELD_GET(RF_MAC_DEBUG_TXQ_BITMAP, tmp);
} else {
tmp = RF_MAC_READ_REG(CFG_RF_MAC_DEBUG_BUS0_ADDR);
txq_bit_map = REG_FIELD_GET(RF_MAC_TXQ_BITMAP_2CPU2, tmp);
}
if (txq_bit_map & (1 << MAC_RF_QUE_CSMA_0) ||
txq_bit_map & (1 << MAC_RF_QUE_CSMA_1) ||
txq_bit_map & (1 << MAC_RF_QUE_CSMA_2) ||
txq_bit_map & (1 << MAC_RF_QUE_CSMA_3) ||
txq_bit_map & (1 << MAC_RF_QUE_CSMA_DBG) ||
txq_bit_map & (1 << MAC_RF_QUE_BCSMA)) {
ret = 1;
}
return ret;
}
uint32_t bb_cpu_mac_judge_cur_cmd_need_tx_tdma()
{
uint32_t tmp, txq_bit_map, ret = 0;
if (mac_rf_txq_is_dbg_mode()) {
tmp = RF_MAC_READ_REG(CFG_RF_MAC_DEBUG_CFG_ADDR);
txq_bit_map = REG_FIELD_GET(RF_MAC_DEBUG_TXQ_BITMAP, tmp);
} else {
tmp = RF_MAC_READ_REG(CFG_RF_MAC_DEBUG_BUS0_ADDR);
txq_bit_map = REG_FIELD_GET(RF_MAC_TXQ_BITMAP_2CPU2, tmp);
}
if (txq_bit_map & (1 << MAC_RF_QUE_BCN) ||
txq_bit_map & (1 << MAC_RF_QUE_TDMA)) {
ret = 1;
}
return ret;
}
uint32_t bb_cpu_mac_judge_next_cmd_is_vld()
{
uint32_t tmp, is_vld;
tmp = RF_MAC_READ_REG(CFG_RF_MAC_DEBUG_BUS1_ADDR);
is_vld = REG_FIELD_GET(RF_MAC_NEXT_CMD_VLD_2CPU2, tmp);
(void)is_vld;
/* NOTE: this function is bad */
return 0;
}
uint32_t bb_cpu_mac_judge_next_cmd_need_tx_tdma()
{
uint32_t tmp, is_vld, txq_bit_map, ret = 0;
tmp = RF_MAC_READ_REG(CFG_RF_MAC_DEBUG_BUS1_ADDR);
is_vld = REG_FIELD_GET(RF_MAC_NEXT_CMD_VLD_2CPU2, tmp);
if (is_vld) {
txq_bit_map = REG_FIELD_GET(RF_MAC_NEXT_TXQ_BITMAP_2CPU2, tmp);
if (txq_bit_map & (1 << MAC_RF_QUE_BCN) ||
txq_bit_map & (1 << MAC_RF_QUE_TDMA)) {
ret = 1;
}
}
return ret;
}
uint32_t bb_cpu_mac_get_rest_slot_time()
{
uint32_t remain_time = RF_MAC_READ_REG(CFG_RF_MAC_SLICE_TIME_LEFT_ADDR);
/* uint us */
return remain_time/25;
}
void bb_cpu_mac_inter_pkt_interval(uint32_t interval)
{
/* uint us */
RF_MAC_WRITE_REG(CFG_RF_MAC_PKT_INTERVAL_TIME_ADDR, (interval * 25));
}
/* NOTE: CFG_RF_MAC_TXRX_CTL_ADDR need atomic operations
*
* this function in isr, so it do not need stop bbcpu irq.
*/
void bb_cpu_mac_set_vcs_sts_from_isr(uint32_t is_busy)
{
uint32_t tmp = RF_MAC_READ_REG(CFG_RF_MAC_TXRX_CTL_ADDR);
REG_FIELD_SET(RF_MAC_VCS_STATUS, tmp, is_busy);
RF_MAC_WRITE_REG(CFG_RF_MAC_TXRX_CTL_ADDR, tmp);
}
uint32_t bb_cpu_mac_get_vcs_sts()
{
uint32_t tmp = RF_MAC_READ_REG(CFG_RF_MAC_TXRX_CTL_ADDR);
return REG_FIELD_GET(RF_MAC_VCS_STATUS, tmp);
}
void bb_cpu_mac_set_tx_done()
{
/* NOTE: make sure CFG_RF_MAC_TXRX_CTL_ADDR is atomic operations,
* we need stop bbcpu irq.
*/
/* disable irq */
bb_cpu_mac_isr_stop();
uint32_t tmp = RF_MAC_READ_REG(CFG_RF_MAC_TXRX_CTL_ADDR);
REG_FIELD_SET(RF_MAC_TX_DONE_CPU2, tmp, 1);
RF_MAC_WRITE_REG(CFG_RF_MAC_TXRX_CTL_ADDR, tmp);
/* enable irq */
bb_cpu_mac_isr_start();
}
void bb_cpu_mac_set_rx_done()
{
/* NOTE: make sure CFG_RF_MAC_TXRX_CTL_ADDR is atomic operations,
* we need stop bbcpu irq.
*/
/* disable irq */
bb_cpu_mac_isr_stop();
uint32_t tmp = RF_MAC_READ_REG(CFG_RF_MAC_TXRX_CTL_ADDR);
REG_FIELD_SET(RF_MAC_RX_DONE_CPU2, tmp, 1);
RF_MAC_WRITE_REG(CFG_RF_MAC_TXRX_CTL_ADDR, tmp);
/* enable irq */
bb_cpu_mac_isr_start();
}
void bb_cpu_mac_set_tx_abort_done()
{
/* NOTE: make sure CFG_RF_MAC_TXRX_CTL_ADDR is atomic operations,
* we need stop bbcpu irq.
*/
/* disable irq */
bb_cpu_mac_isr_stop();
uint32_t tmp = RF_MAC_READ_REG(CFG_RF_MAC_TXRX_CTL_ADDR);
REG_FIELD_SET(RF_MAC_TX_ABORT_DONE_CPU2, tmp, 1);
RF_MAC_WRITE_REG(CFG_RF_MAC_TXRX_CTL_ADDR, tmp);
/* enable irq */
bb_cpu_mac_isr_start();
}
void bb_cpu_mac_set_rx_abort_done()
{
/* NOTE: make sure CFG_RF_MAC_TXRX_CTL_ADDR is atomic operations,
* we need stop bbcpu irq.
*/
/* disable irq */
bb_cpu_mac_isr_stop();
uint32_t tmp = RF_MAC_READ_REG(CFG_RF_MAC_TXRX_CTL_ADDR);
REG_FIELD_SET(RF_MAC_RX_ABORT_DONE_CPU2, tmp, 1);
RF_MAC_WRITE_REG(CFG_RF_MAC_TXRX_CTL_ADDR, tmp);
/* enable irq */
bb_cpu_mac_isr_start();
}
static uint32_t bb_cpu_mac_check_fsm(uint32_t reason, uint32_t is_assert)
{
#define RESET_FSM_TIME_NTB 250 // 10US * 25
uint32_t start_ntb, cur_ntb, time_span;
uint32_t wmac_fsm;
/* wait reset fsm complete */
start_ntb = RGF_MAC_READ_REG(CFG_RD_LOCAL_TMR_ADDR);
do {
/* reset txrx fsm */
mac_rf_reset_txrxfsm();
cur_ntb = RGF_MAC_READ_REG(CFG_RD_LOCAL_TMR_ADDR);
time_span = cur_ntb - start_ntb;
wmac_fsm = mac_rf_wmac_get_fsm();
} while (wmac_fsm && time_span < RESET_FSM_TIME_NTB);
/* just check wmac fsm */
if (wmac_fsm) {
bb_cpu_printf("reason:%d, fsm:0x%x, lft:%lu\n", reason, wmac_fsm,
bb_cpu_mac_get_rest_slot_time());
if (is_assert) {
IOT_ASSERT(0);
}
}
return wmac_fsm;
}
uint32_t bb_cpu_mac_set_sched_stop_done(uint32_t times)
{
/* NOTE: make sure CFG_RF_MAC_TXRX_CTL_ADDR is atomic operations,
* we need stop bbcpu irq.
*/
/* disable irq */
bb_cpu_mac_isr_stop();
uint32_t tmp = RF_MAC_READ_REG(CFG_RF_MAC_TXRX_CTL_ADDR);
REG_FIELD_SET(RF_MAC_EARLY_STOP_DONE, tmp, 1);
RF_MAC_WRITE_REG(CFG_RF_MAC_TXRX_CTL_ADDR, tmp);
/* enable irq */
bb_cpu_mac_isr_start();
/* wmac fsm check */
return bb_cpu_mac_check_fsm(BB_CPU_CHECK_WMAC_FSM_DUE_TO_EARLY_STOP,
(times > 1));
}
void bb_cpu_mac_set_csma_is_ready()
{
uint32_t tmp = RF_MAC_READ_REG(CFG_RF_MAC_PKT_INTERVAL_TIME_CTL_ADDR);
REG_FIELD_SET(RF_MAC_CSMA_CPU2_READY, tmp, 1);
RF_MAC_WRITE_REG(CFG_RF_MAC_PKT_INTERVAL_TIME_CTL_ADDR, tmp);
}
void bb_cpu_mac_set_cmdlist_done()
{
/* rf mac cmdlist done */
uint32_t tmp = RF_MAC_READ_REG(CFG_RF_MAC_PKT_INTERVAL_TIME_CTL_ADDR);
REG_FIELD_SET(RF_MAC_CMDLIST_EARLY_STOP_DONE, tmp, 1);
RF_MAC_WRITE_REG(CFG_RF_MAC_PKT_INTERVAL_TIME_CTL_ADDR, tmp);
/* wmac cmdlist done */
tmp = WMAC_READ_REG(CFG_WMAC_CTRL_ADDR);
REG_FIELD_SET(SW_CMDLIST_DONE_CPU2_IDLE_PLS, tmp, 1);
WMAC_WRITE_REG(CFG_WMAC_CTRL_ADDR, tmp);
/* check wmac fsm */
bb_cpu_mac_check_fsm(BB_CPU_CHECK_WMAC_FSM_DUE_TO_CMDLIST_DONE, 1);
}
void bb_cpu_mac_tx_timer_en(uint32_t enable)
{
/* start rf mac tx timer */
uint32_t tmp = RF_MAC_READ_REG(CFG_RF_MAC_BB_EVT_CTL_ADDR);
REG_FIELD_SET(RF_MAC_BB_TX_TIMER_EN, tmp, enable);
RF_MAC_WRITE_REG(CFG_RF_MAC_BB_EVT_CTL_ADDR, tmp);
}
void bb_cpu_mac_stop_listen_timer_en(uint32_t enable)
{
/* start rf mac stop listen timer */
uint32_t tmp = RF_MAC_READ_REG(CFG_RF_MAC_BB_EVT_CTL_ADDR);
REG_FIELD_SET(RF_MAC_BB_EVT4_TIMER_EN, tmp, enable);
RF_MAC_WRITE_REG(CFG_RF_MAC_BB_EVT_CTL_ADDR, tmp);
}
uint32_t bb_cpu_mac_trigger_tx(uint32_t *phr)
{
uint32_t tmp, is_beacon = 0, recorc_ntb, tmp_ntb, tx_gap;
/* start bb tx timer every time */
bb_rf_tx_timer_en(1);
/* start rf mac tx timer */
bb_cpu_mac_tx_timer_en(1);
/* set tx rf timer, unit ntb */
RF_MAC_WRITE_REG(CFG_RF_MAC_BB_TX_RF_TIMER_VALUE_ADDR, BB_CPU_AOTX_TIME);
/* tx bb time - tx rf time > 50us */
/* set tx bb timer, unit ntb */
RF_MAC_WRITE_REG(CFG_RF_MAC_BB_TX_BB_TIMER_VALUE_ADDR, BB_CPU_SOTX_TIME);
/* start rf mac stop listen timer */
bb_cpu_mac_stop_listen_timer_en(1);
/* set evt bit4 timer, unit ntb */
RF_MAC_WRITE_REG(CFG_RF_MAC_BB_EVT4_TIMER_VALUE_ADDR,
BB_CPU_NOTX_TIME);
if (phr) {
bb_cpu_rf_fc_t fc_msg = {0};
bb_cpu_mac_get_msg_from_phr(bb_cpu_get_proto(), phr, &fc_msg);
is_beacon = (fc_msg.delimiter == FC_DELIM_BEACON);
if (is_beacon) {
/* disable irq */
bb_cpu_mac_isr_stop();
}
}
/* record rx stop ntb */
recorc_ntb = bb_cpu_mac_get_stop_rx_evt_ntb();
/* start tx */
tmp = RF_MAC_READ_REG(CFG_RF_MAC_BB_EVT_CTL_ADDR);
REG_FIELD_SET(RF_MAC_BB_EVT_BIT4, tmp, 1);
REG_FIELD_SET(RF_MAC_BB_EVT_BIT01, tmp, 1);
RF_MAC_WRITE_REG(CFG_RF_MAC_BB_EVT_CTL_ADDR, tmp);
/* make sure rx stop has triggered */
do {
tmp_ntb = bb_cpu_mac_get_stop_rx_evt_ntb();
} while (recorc_ntb == tmp_ntb);
/* config beacon timestamp */
tx_gap = bb_cpu_get_tx_golden_gap(mac_rf_get_option());
if (phr && is_beacon) {
/* update timestamp */
switch (bb_cpu_get_proto()) {
#if SUPPORT_SMART_GRID
case PLC_PROTO_TYPE_SG:
{
frame_control_t *phr_t = (frame_control_t *)phr;
phr_t->vf.rf_bcn.time_stamp = tx_gap + tmp_ntb;
break;
}
#endif
#if SUPPORT_SOUTHERN_POWER_GRID
case PLC_PROTO_TYPE_SPG:
{
spg_frame_control_t *phr_t = (spg_frame_control_t *)phr;
phr_t->vf.rf_bcn.time_stamp = tx_gap + tmp_ntb;
break;
}
#endif
default:
IOT_ASSERT(0);
break;
}
/* set phr */
bb_rf_set_tx_phr((uint32_t *)phr);
/* enable irq */
bb_cpu_mac_isr_start();
}
return tx_gap + tmp_ntb;
}
void bb_cpu_mac_rx_timer_en(uint32_t enable)
{
/* start rf mac rx timer */
uint32_t tmp = RF_MAC_READ_REG(CFG_RF_MAC_BB_EVT_CTL_ADDR);
REG_FIELD_SET(RF_MAC_BB_RX_TIMER_EN, tmp, enable);
RF_MAC_WRITE_REG(CFG_RF_MAC_BB_EVT_CTL_ADDR, tmp);
}
void bb_cpu_mac_trigger_rx()
{
uint32_t tmp;
/* start bb rx timer every time */
bb_rf_rx_timer_en(1);
/* start rf mac rx timer */
bb_cpu_mac_rx_timer_en(1);
/* set tx rf timer, unit ntb */
RF_MAC_WRITE_REG(CFG_RF_MAC_BB_RX_RF_TIMER_VALUE_ADDR, 2);
/* tx bb time - tx rf time > 50us */
/* set tx bb timer, unit ntb */
RF_MAC_WRITE_REG(CFG_RF_MAC_BB_RX_BB_TIMER_VALUE_ADDR, (51 * 25));
/* start rx */
tmp = RF_MAC_READ_REG(CFG_RF_MAC_BB_EVT_CTL_ADDR);
REG_FIELD_SET(RF_MAC_BB_EVT_BIT23, tmp, 1);
RF_MAC_WRITE_REG(CFG_RF_MAC_BB_EVT_CTL_ADDR, tmp);
}
void bb_cpu_mac_trigger_stop_listen()
{
uint32_t tmp;
/* start bb stop listen timer every time */
bb_rf_stop_listen_timer_en(1);
/* start rf mac stop listen timer */
bb_cpu_mac_stop_listen_timer_en(1);
/* set evt bit4 timer, unit ntb */
RF_MAC_WRITE_REG(CFG_RF_MAC_BB_EVT4_TIMER_VALUE_ADDR, 2);
/* stop listen */
tmp = RF_MAC_READ_REG(CFG_RF_MAC_BB_EVT_CTL_ADDR);
REG_FIELD_SET(RF_MAC_BB_EVT_BIT4, tmp, 1);
RF_MAC_WRITE_REG(CFG_RF_MAC_BB_EVT_CTL_ADDR, tmp);
}
uint32_t bb_cpu_mac_get_tx_complete_ntb()
{
return RF_MAC_READ_REG(CFG_RF_MAC_BB_DEBUG_NTB_TMR_0_REG_ADDR);
}
uint32_t bb_cpu_mac_get_tx_complete_local_ntb()
{
return RF_MAC_READ_REG(CFG_RF_MAC_BB_DEBUG_LOCAL_TMR_0_REG_ADDR);
}
uint32_t bb_cpu_mac_get_stop_listen_ntb()
{
return RF_MAC_READ_REG(CFG_RF_MAC_BB_DEBUG_NTB_TMR_1_REG_ADDR);
}
uint32_t bb_cpu_mac_get_stop_listen_local_ntb()
{
return RF_MAC_READ_REG(CFG_RF_MAC_BB_DEBUG_LOCAL_TMR_1_REG_ADDR);
}
uint32_t bb_cpu_mac_get_rx_stf_ntb()
{
return RF_MAC_READ_REG(CFG_RF_MAC_BB_DEBUG_NTB_TMR_2_REG_ADDR);
}
uint32_t bb_cpu_mac_get_rx_stf_local_ntb()
{
return RF_MAC_READ_REG(CFG_RF_MAC_BB_DEBUG_LOCAL_TMR_2_REG_ADDR);
}
uint32_t bb_cpu_mac_get_rx_sig_ntb()
{
return RF_MAC_READ_REG(CFG_RF_MAC_BB_DEBUG_NTB_TMR_3_REG_ADDR);
}
uint32_t bb_cpu_mac_get_rx_sig_local_ntb()
{
return RF_MAC_READ_REG(CFG_RF_MAC_BB_DEBUG_LOCAL_TMR_3_REG_ADDR);
}
uint32_t bb_cpu_mac_get_rx_phr_ntb()
{
return RF_MAC_READ_REG(CFG_RF_MAC_BB_DEBUG_NTB_TMR_4_REG_ADDR);
}
uint32_t bb_cpu_mac_get_rx_phr_local_ntb()
{
return RF_MAC_READ_REG(CFG_RF_MAC_BB_DEBUG_LOCAL_TMR_4_REG_ADDR);
}
uint32_t bb_cpu_mac_get_rx_pld_start_ntb()
{
return RF_MAC_READ_REG(CFG_RF_MAC_BB_DEBUG_NTB_TMR_5_REG_ADDR);
}
uint32_t bb_cpu_mac_get_rx_pld_start_local_ntb()
{
return RF_MAC_READ_REG(CFG_RF_MAC_BB_DEBUG_LOCAL_TMR_5_REG_ADDR);
}
uint32_t bb_cpu_mac_get_rf_tx_ntb()
{
return WMAC_READ_REG(CFG_WMAC_EVT_I_0_NTB_TMR_STS_ADDR);
}
uint32_t bb_cpu_mac_get_bb_tx_ntb()
{
return WMAC_READ_REG(CFG_WMAC_EVT_I_1_NTB_TMR_STS_ADDR);
}
uint32_t bb_cpu_mac_get_rf_rx_ntb()
{
return WMAC_READ_REG(CFG_WMAC_EVT_I_2_NTB_TMR_STS_ADDR);
}
uint32_t bb_cpu_mac_get_bb_rx_ntb()
{
return WMAC_READ_REG(CFG_WMAC_EVT_I_3_NTB_TMR_STS_ADDR);
}
uint32_t bb_cpu_mac_get_stop_rx_evt_ntb()
{
return WMAC_READ_REG(CFG_WMAC_EVT_I_4_NTB_TMR_STS_ADDR);
}
uint32_t bb_cpu_mac_get_rf_tx_local_ntb()
{
return WMAC_READ_REG(CFG_WMAC_EVT_I_0_LOCAL_TMR_STS_ADDR);
}
uint32_t bb_cpu_mac_get_bb_tx_local_ntb()
{
return WMAC_READ_REG(CFG_WMAC_EVT_I_1_LOCAL_TMR_STS_ADDR);
}
uint32_t bb_cpu_mac_get_rf_rx_local_ntb()
{
return WMAC_READ_REG(CFG_WMAC_EVT_I_2_LOCAL_TMR_STS_ADDR);
}
uint32_t bb_cpu_mac_get_bb_rx_local_ntb()
{
return WMAC_READ_REG(CFG_WMAC_EVT_I_3_LOCAL_TMR_STS_ADDR);
}
uint32_t bb_cpu_mac_get_stop_rx_evt_local_ntb()
{
return WMAC_READ_REG(CFG_WMAC_EVT_I_4_LOCAL_TMR_STS_ADDR);
}
uint32_t bb_cpu_mac_get_hwq_cur_ptr(uint32_t hwqid)
{
uint32_t cur_ptr_dlt = CFG_WMAC_WMAC_CURRENT_TX_PTR1_ADDR -
CFG_WMAC_WMAC_CURRENT_TX_PTR0_ADDR;
return WMAC_READ_REG(CFG_WMAC_WMAC_CURRENT_TX_PTR0_ADDR +
hwqid * cur_ptr_dlt);
}
uint32_t bb_cpu_mac_get_hwqfsm()
{
return WMAC_READ_REG(CFG_WMAC_TXQ_FSM_STS_ADDR);
}
void bb_cpu_dma_start(uint32_t bb_addr, uint32_t pb_addr, uint32_t byte_size)
{
(void)bb_addr;
(void)pb_addr;
(void)byte_size;
}
void bb_cpu_dma_stop()
{
}
void bb_cpu_mac_init(void)
{
bb_cpu_hw_ring_init();
bb_cpu_mac_isr_init();
bb_cpu_mac_isr_enable();
bb_cpu_timer_enable();
bb_cpu_mac_isr_start();
}
void bb_cpu_mac_get_msg_from_phr(uint32_t proto, void *phr, bb_cpu_rf_fc_t *msg)
{
switch (proto) {
#if SUPPORT_SMART_GRID
case PLC_PROTO_TYPE_SG:
{
/* nid share the same place for SG */
frame_control_t *sg_phr = (frame_control_t *)phr;
msg->nid = sg_phr->nid;
msg->delimiter = sg_phr->delimiter_type;
switch (sg_phr->delimiter_type) {
case FC_DELIM_BEACON:
{
msg->rf_mcs = (uint8_t)sg_phr->vf.rf_bcn.mcs;
msg->rf_pb_sz_idx = (uint8_t)sg_phr->vf.rf_bcn.pb_sz_idx;
msg->src_tei = sg_phr->vf.rf_bcn.src_tei;
break;
}
case FC_DELIM_SOF:
{
msg->dst_tei = sg_phr->vf.rf_sof.dst_tei;
msg->src_tei = sg_phr->vf.rf_sof.src_tei;
msg->rf_pb_sz_idx = (uint8_t)sg_phr->vf.rf_sof.pb_sz_idx;
msg->rf_mcs = (uint8_t)sg_phr->vf.rf_sof.mcs;
break;
}
case FC_DELIM_SACK:
{
msg->result_in_sack = sg_phr->vf.rf_sack.rx_result;
msg->dst_tei = sg_phr->vf.rf_sack.dtei;
msg->src_tei = sg_phr->vf.rf_sack.stei;
break;
}
default:
break;
}
break;
}
#endif
#if SUPPORT_SOUTHERN_POWER_GRID
case PLC_PROTO_TYPE_SPG:
{
spg_frame_control_t *spg_phr = (spg_frame_control_t *)phr;
msg->nid = spg_phr->snid;
msg->delimiter = spg_phr->delimiter_type;
switch (spg_phr->delimiter_type) {
case FC_DELIM_BEACON:
{
msg->rf_mcs = (uint8_t)spg_phr->vf.rf_bcn.mcs;
msg->rf_pb_sz_idx = (uint8_t)spg_phr->vf.rf_bcn.pb_sz_idx;
msg->src_tei = spg_phr->vf.rf_bcn.src_tei;
break;
}
case FC_DELIM_SOF:
{
msg->dst_tei = spg_phr->vf.rf_sof.dst_tei;
msg->src_tei = spg_phr->vf.rf_sof.src_tei;
msg->rf_pb_sz_idx = (uint8_t)spg_phr->vf.rf_sof.pb_sz_idx;
msg->rf_mcs = (uint8_t)spg_phr->vf.rf_sof.mcs;
break;
}
case FC_DELIM_SACK:
{
msg->result_in_sack = spg_phr->vf.rf_sack.rx_result;
msg->dst_tei = spg_phr->vf.rf_sack.dtei;
break;
}
default:
break;
}
break;
}
#endif
default:
(void)proto;
(void)phr;
(void)msg;
break;
}
return;
}

430
bb_cpu/mac/bb_cpu_mac_isr.c Normal file
View File

@@ -0,0 +1,430 @@
/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
****************************************************************************/
/* os shim includes */
#include "iot_config.h"
#include "os_types.h"
/* plc public api includes */
#include "plc_fr.h"
#include "plc_const.h"
/* driver includes */
#include "iot_irq.h"
#include "bb_cpu_mac_isr.h"
#include "bb_cpu_mac_init.h"
#include "bb_cpu_fsm.h"
#include "bb_cpu_timer.h"
#include "mac_rf_isr.h"
#include "iot_io.h"
#include "hw_reg_api.h"
#include "rfplc_reg_base.h"
#include "rf_mac_reg.h"
#include "mac_sys_reg.h"
#include "plc_mac_cfg.h"
#include "mac_rf_common_hw.h"
#include "mac_rf_timer.h"
/* define mac isr ctxt */
rf_mac_isr_ctx_t g_rf_mac_isr_1 = { 0 };
rf_mac_isr_ctx_t *p_rf_mac_isr_1 = &g_rf_mac_isr_1;
static uint8_t stf_occur = 0;
/* get hw intrrupt status, hw interrupt */
static uint32_t bb_cpu_mac_get_hw_interrupt_sts()
{
return RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_7_ADDR);
}
/* clear hw intrrupt status, hw interrupt */
static void bb_cpu_mac_clear_hw_interrupt(uint32_t irq_sts)
{
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_5_ADDR, irq_sts);
}
/* get sw intrrupt status, hw interrupt */
static uint32_t bb_cpu_mac_get_sw_interrupt_sts()
{
return RF_MAC_READ_REG(CFG_RF_MAC_COMMON_INT_REG_27_ADDR);
}
/* clear sw intrrupt status, hw interrupt */
static void bb_cpu_mac_clear_sw_interrupt(uint32_t irq_sts)
{
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_25_ADDR, irq_sts);
}
static void bb_cpu_mac_hw_isr_reset(void)
{
/* disable all mac interrupt */
p_rf_mac_isr_1->isr_hw_mask = 0;
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_9_ADDR,
p_rf_mac_isr_1->isr_hw_mask);
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_1_ADDR,
p_rf_mac_isr_1->isr_hw_mask);
/* clean up all pending interrupt */
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_5_ADDR,
RF_MAC_COMMON_IRQ_SW_CLR_CPU2_MASK);
}
static void bb_cpu_mac_sw_isr_reset(void)
{
/* disable all mac interrupt */
p_rf_mac_isr_1->isr_sw_mask = 0;
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_29_ADDR,
p_rf_mac_isr_1->isr_sw_mask);
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_21_ADDR,
p_rf_mac_isr_1->isr_sw_mask);
/* clean up all pending interrupt */
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_25_ADDR,
RF_MAC_COMMON_SHARE_IRQ_SW_CLR_CPU2_MASK);
}
static void bb_cpu_mac_share_isr_reset(void)
{
/* disable all mac interrupt */
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_19_ADDR, 0);
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_11_ADDR, 0);
/* clean up all pending interrupt */
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_15_ADDR,
RF_MAC_COMMON_SHARE_IRQ_SW_CLR_CPU2_MASK);
}
void bb_cpu_mac_hw_isr_enable(uint8_t id)
{
uint32_t int_mask;
int_mask = 1 << id;
if (!(p_rf_mac_isr_1->isr_hw_mask & int_mask)) {
p_rf_mac_isr_1->isr_hw_mask |= int_mask;
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_9_ADDR,
p_rf_mac_isr_1->isr_hw_mask);
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_1_ADDR,
p_rf_mac_isr_1->isr_hw_mask);
}
}
void bb_cpu_mac_sw_isr_enable(uint8_t id)
{
uint32_t int_mask;
int_mask = 1 << id;
if (!(p_rf_mac_isr_1->isr_sw_mask & int_mask)) {
p_rf_mac_isr_1->isr_sw_mask |= int_mask;
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_29_ADDR,
p_rf_mac_isr_1->isr_sw_mask);
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_21_ADDR,
p_rf_mac_isr_1->isr_sw_mask);
}
}
void bb_cpu_mac_hw_isr_disable(uint8_t id)
{
uint32_t int_mask;
int_mask = 1 << id;
if (p_rf_mac_isr_1->isr_hw_mask & int_mask) {
p_rf_mac_isr_1->isr_hw_mask &= ~int_mask;
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_9_ADDR,
p_rf_mac_isr_1->isr_hw_mask);
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_1_ADDR,
p_rf_mac_isr_1->isr_hw_mask);
}
}
void bb_cpu_mac_sw_isr_disable(uint8_t id)
{
uint32_t int_mask;
int_mask = 1 << id;
if (p_rf_mac_isr_1->isr_sw_mask & int_mask) {
p_rf_mac_isr_1->isr_sw_mask &= ~int_mask;
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_19_ADDR,
p_rf_mac_isr_1->isr_sw_mask);
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_11_ADDR,
p_rf_mac_isr_1->isr_sw_mask);
}
}
void bb_cpu_mac_set_sw_irq_to_maincpu(uint8_t id)
{
if (id < RF_MAC_SW_INT_MAX) {
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_22_ADDR, (1 << id));
} else {
IOT_ASSERT(id < RF_MAC_SW2_INT_MAX);
uint32_t timer_id = id - RF_MAC_SW_INT_MAX;
mac_rf_timer_stop(timer_id);
mac_rf_timer_set(timer_id, 1);
mac_rf_timer_start(timer_id);
}
}
void bb_cpu_mac_set_share_irq_to_maincpu(uint8_t id)
{
RF_MAC_WRITE_REG(CFG_RF_MAC_COMMON_INT_REG_12_ADDR, (1 << id));
}
void bb_cpu_mac_isr_start(void)
{
/* enable soc irq */
iot_interrupt_unmask(p_rf_mac_isr_1->isr_hw_h);
iot_interrupt_unmask(p_rf_mac_isr_1->isr_sw_h);
iot_interrupt_unmask(p_rf_mac_isr_1->isr_timer_h);
}
void bb_cpu_mac_isr_stop(void)
{
/* disable soc irq */
iot_interrupt_mask(p_rf_mac_isr_1->isr_hw_h);
iot_interrupt_mask(p_rf_mac_isr_1->isr_sw_h);
iot_interrupt_mask(p_rf_mac_isr_1->isr_timer_h);
}
void bb_cpu_mac_isr_enable()
{
/* enable hw interrupt */
for (uint32_t i = 0; i < RF_MAC_ISR_HW_MAX_ID; i++) {
bb_cpu_mac_hw_isr_enable(i);
}
/* enable bb init and set channel interrupt */
bb_cpu_mac_sw_isr_enable(RF_MAC_SW_ISR_BB_INIT);
bb_cpu_mac_sw_isr_enable(RF_MAC_SW_ISR_SET_CHANNEL);
/* enable trigger hwq interrupt */
bb_cpu_mac_sw_isr_enable(RF_MAC_SW_ISR_CSMA_TX_CHECK);
bb_cpu_mac_sw_isr_enable(RF_MAC_SW_ISR_SYNC_SPI_VALUE);
bb_cpu_mac_sw_isr_enable(RF_MAC_SW_ISR_TX_TONE);
bb_cpu_mac_sw_isr_enable(RF_MAC_SW_ISR_SET_PS_IDLE);
bb_cpu_mac_sw_isr_enable(RF_MAC_SW_ISR_TX_CAL_UPDATE);
}
static uint32_t bb_cpu_mac_isr_handler(uint32_t vector, uint32_t data)
{
(void)vector;
(void)data;
uint32_t hw_int_status, sw_int_status, timer_int_sts;
/* get interrupt status */
hw_int_status = bb_cpu_mac_get_hw_interrupt_sts();
/* clear interrupt status */
bb_cpu_mac_clear_hw_interrupt(hw_int_status);
/* get interrupt status */
sw_int_status = bb_cpu_mac_get_sw_interrupt_sts();
/* clear interrupt status */
bb_cpu_mac_clear_sw_interrupt(sw_int_status);
/* get timer interrupt status */
timer_int_sts = bb_cpu_timer_get_timeout_id();
bb_cpu_timer_clr_timeout_id(timer_int_sts);
/* cmdlist done */
if (hw_int_status & (0x1 << RF_MAC_ISR_CMDLIST_DONE_ID)) {
/* set event to cmdlist done and stop tx/rx */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_CMDLIST_DONE_ID);
}
/* stop schedule */
if (hw_int_status & (0x1 << RF_MAC_ISR_EARLY_STOP_START_ID)) {
/* set event to stop schduel(reset tx/rx) */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_RST_ID);
}
/* vcs timeout
* NOTE: the priority of BB_CPU_ISR_VCS_TIMEOUT_ID higher than
* RF_MAC_ISR_BB_RX_STF_ID.
*/
if (timer_int_sts & (0x1 << BB_CPU_ISR_VCS_TIMEOUT_ID)) {
/* stop vcs working */
bb_cpu_stop_vcs_working_from_isr();
}
/* rx stf */
if (hw_int_status & (0x1 << RF_MAC_ISR_BB_RX_STF_ID)) {
/* pull vcs up */
bb_cpu_mac_set_vcs_sts_from_isr(1);
/* set stf occour */
stf_occur = 1;
/* set eifs */
bb_cpu_set_vcs_timer_from_isr(RF_MAC_EIFS_US, 1);
/* increase rx stf cnt */
mac_rf_rx_stf_cnt_inc();
}
/* tx abort */
if (hw_int_status & (0x1 << RF_MAC_ISR_TX_ABORT_ID)) {
/* set event to tx abort */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_TX_ABORT_ID);
}
/* rx abort */
if (hw_int_status & (0x1 << RF_MAC_ISR_RX_ABORT_ID)) {
/* set event to rx abort */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_RX_ABORT_ID);
}
/* backoff timeout */
if (hw_int_status & (0x1 << RF_MAC_ISR_BACKOFF_TIMEOUT_ID)) {
/* set event to backoff timeout */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_BACKOFF_TIMEOUT_ID);
}
/* rx start */
if (hw_int_status & (0x1 << RF_MAC_ISR_RX_START_ID)) {
stf_occur = 0;
/* set event to rx start */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_MAC_RX_START_ID);
}
/* rx timeout */
if (timer_int_sts & (0x1 << BB_CPU_ISR_RX_TIMEOUT_ID)) {
/* set event to rx timeout */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_RX_TIMEOUT_ID);
}
/* tx start */
if (hw_int_status & (0x1 << RF_MAC_ISR_TX_START_ID)) {
/* set event to start tx */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_MAC_TX_START_ID);
}
/* tx timeout */
if (timer_int_sts & (0x1 << BB_CPU_ISR_TX_TIMEOUT_ID)) {
/* set event to tx timeout */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_TX_TIMEOUT_ID);
}
/* wait sack timeout */
if (timer_int_sts & (0x1 << BB_CPU_ISR_WAIT_SACK_TIMEOUT_ID)) {
/* in conflict scenarios, backoff eifs */
/* pull vcs up */
bb_cpu_mac_set_vcs_sts_from_isr(1);
/* set eifs */
bb_cpu_set_vcs_timer_from_isr(RF_MAC_EIFS_US, 0);
/* set event to wait sack timeout */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_WAIT_SACK_TIMEOUT_ID);
}
/* wait reset timeout */
if (timer_int_sts & (0x1 << BB_CPU_ISR_RST_TIMEOUT_ID)) {
/* set event to wait reset timeout */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_RST_TIMEOUT_ID);
}
/* bb tx done */
if (hw_int_status & (0x1 << RF_MAC_ISR_BB_TX_DONE_ID)) {
/* set event to tx complete */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_TX_COMP_ID);
}
/* bb rx sig done */
if (hw_int_status & (0x1 << RF_MAC_ISR_BB_RX_SIG_ID)) {
if (!stf_occur) {
/* pull vcs up */
bb_cpu_mac_set_vcs_sts_from_isr(1);
/* set eifs */
bb_cpu_set_vcs_timer_from_isr(RF_MAC_EIFS_US, 1);
mac_rf_lost_stf_cnt_inc();
}
/* set event to rx sig */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_RX_SIG_ID);
}
/* bb rx phr done */
if (hw_int_status & (0x1 << RF_MAC_ISR_BB_RX_PHR_ID)) {
/* set event to rx phy header */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_RX_PHR_ID);
}
/* bb rx pld start */
if (hw_int_status & (0x1 << RF_MAC_ISR_BB_RX_PLD_START_ID)) {
/* set event to rx pld start */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_RX_PLD_START_ID);
}
/* bb init */
if (sw_int_status & (0x1 << RF_MAC_SW_ISR_BB_INIT)) {
/* set event to bb init */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_BB_INIT_ID);
}
/* bb set channel */
if (sw_int_status & (0x1 << RF_MAC_SW_ISR_SET_CHANNEL)) {
/* set event to set channel */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_SET_CHANNEL_ID);
}
/* bb early stop done */
if (hw_int_status & (0x1 << RF_MAC_ISR_EARLY_STOP_DONE_ID)) {
/* set isr is vaild */
bb_cpu_set_isr_vaild_from_isr(1);
}
/* csma q tx check */
if (sw_int_status & (0x1 << RF_MAC_SW_ISR_CSMA_TX_CHECK)) {
/* csma q tx check */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_CSMA_TX_CHECK_ID);
}
/* hplc cpu sync rf spi */
if (sw_int_status & (0x1 << RF_MAC_SW_ISR_SYNC_SPI_VALUE)) {
/* csma q tx check */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_SYNC_SPI_ID);
}
/* hplc cpu tx tone */
if (sw_int_status & (0x1 << RF_MAC_SW_ISR_TX_TONE)) {
/* tx tone */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_TX_TONE_ID);
}
/* hplc cpu set power save idle */
if (sw_int_status & (0x1 << RF_MAC_SW_ISR_SET_PS_IDLE)) {
/* set power save idle */
bb_cpu_set_event_from_isr(BB_CPU_EVENT_PS_IDLE_ID);
}
/* hplc cpu request tx cal update */
if (sw_int_status & (0x1 << RF_MAC_SW_ISR_TX_CAL_UPDATE)) {
bb_cpu_set_event_from_isr(BB_CPU_EVENT_TX_CAL_UPDATE_ID);
}
return 0;
}
void bb_cpu_mac_isr_init(void)
{
bb_cpu_mac_hw_isr_reset();
bb_cpu_mac_sw_isr_reset();
bb_cpu_mac_share_isr_reset();
/* just need init hw interrupt(common isr) */
/* hw irq need isr handle */
p_rf_mac_isr_1->isr_hw_h = iot_interrupt_create(HAL_VECTOR_RFMAC_INT1,
HAL_INTR_PRI_7, (iot_addrword_t)NULL, bb_cpu_mac_isr_handler);
p_rf_mac_isr_1->isr_sw_h = iot_interrupt_create(HAL_VECTOR_RFMAC_INT1,
HAL_INTR_PRI_7, (iot_addrword_t)NULL, bb_cpu_mac_isr_handler);
iot_interrupt_attach(p_rf_mac_isr_1->isr_hw_h);
iot_interrupt_attach(p_rf_mac_isr_1->isr_sw_h);
/* timer irq need isr handle */
p_rf_mac_isr_1->isr_timer_h =
iot_interrupt_create(HAL_VECTOR_RFMAC_TIMEOUT_INT1, HAL_INTR_PRI_6,
(iot_addrword_t)NULL, bb_cpu_mac_isr_handler);
iot_interrupt_attach(p_rf_mac_isr_1->isr_timer_h);
}