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334
bb_cpu/startup/init_2.c
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334
bb_cpu/startup/init_2.c
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/****************************************************************************
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*
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* Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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*
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* This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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* be copied by any method or incorporated into another program without
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* the express written consent of Aerospace C.Power. This Information or any portion
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* thereof remains the property of Aerospace C.Power. The Information contained herein
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* is believed to be accurate and Aerospace C.Power assumes no responsibility or
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* liability for its use in any way and conveys no license or title under
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* any patent or copyright and makes no representation or warranty that this
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* Information is free from patent or copyright infringement.
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*
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* ****************************************************************************/
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/* os shim includes */
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#include "os_types.h"
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#include "iot_irq.h"
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#include "iot_wdg.h"
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#include "os_mem.h"
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#include "efuse.h"
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#include "iot_system.h"
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#include "iot_io.h"
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#include "cpu.h"
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#include "dbg_io.h"
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#include "platform.h"
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#include "encoding.h"
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#include "iot_string_api.h"
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#include "iot_dbglog.h"
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#include "iot_string.h"
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#include "iot_cli_type_definition.h"
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#include "iot_version.h"
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#include "iot_mtd.h"
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#include "cpu.h"
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#include "bb_cpu_utils.h"
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#define FILENAME(x) iot_strrchr(x, '/') ? iot_strrchr(x, '/') + 1 : x
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extern void def_trap_entry_2();
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extern void intc_handler(uint32_t cpu);
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cpu_state g_bbcpu_state;
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extern uint32_t _sp;
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extern unsigned int _heap_end;
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extern uint32_t _start_2;
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static char g_dbg_msg[80];
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#if (IOT_DTEST_ONLY_SUPPORT == 1)
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void print_error_msg(const char *err_msg)
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{
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while(*err_msg != '\0'){
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dbg_putchar(*err_msg);
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++err_msg;
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}
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}
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#else /*(IOT_DTEST_ONLY_SUPPORT == 1) */
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#define print_error_msg(err_msg) while(!bb_cpu_exception_printf("%s", err_msg))
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#endif /*(IOT_DTEST_ONLY_SUPPORT == 1) */
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#define DUMP_DEEP_LEN 10
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typedef struct {
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uint32_t ra[DUMP_DEEP_LEN];
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uint32_t s0[DUMP_DEEP_LEN];
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} exception_dump_t;
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exception_dump_t g_exception_dump = {0};
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static void iot_illegal_instruct(uintptr_t epc)
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{
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uint32_t *pc = (uint32_t *) (epc & 0xFFFFFFF0);
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uint32_t i = 0;
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for (i = 0; i < 8; i++) {
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iot_sprintf(g_dbg_msg, "0x%08x, value: 0x%08x\n", pc+i, *(pc+i));
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print_error_msg(g_dbg_msg);
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}
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}
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int iot_backtrace(uintptr_t epc, saved_registers *regs)
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{
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uint32_t s0 = 0;
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volatile uint32_t deep_len = 0;
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uint32_t ret_fun = 0;
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uint32_t frame_start = 0;
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uint8_t cnt = 0;
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s0 = regs->fp;
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g_exception_dump.ra[deep_len] = epc;
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g_exception_dump.s0[deep_len] = s0;
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frame_start = s0;
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deep_len++;
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while( s0 <= frame_start && deep_len < DUMP_DEEP_LEN) {
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s0 = frame_start;
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if ((s0 >= (uint32_t)&_sp)||(s0 <= (uint32_t)&_data)){
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break;
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}
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uint32_t *tmp = (uint32_t *) s0;
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uint32_t text_s = (uint32_t)&_start_2;
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uint32_t text_e = (uint32_t)&_etext;
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uint32_t iram_s = (uint32_t)&_iram_start;
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uint32_t iram_e = (uint32_t)&_iram_end;;
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ret_fun = *(tmp-1);
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if (((ret_fun > text_s) && (ret_fun < text_e)) ||
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((ret_fun > iram_s) && (ret_fun < iram_e)) ){
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frame_start = *(tmp-2);
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} else {
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frame_start = *(tmp-1);
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ret_fun = regs->ra;
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}
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g_exception_dump.ra[deep_len] = ret_fun;
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g_exception_dump.s0[deep_len] = s0;
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deep_len++;
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cnt++;
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iot_sprintf(g_dbg_msg, "func: 0x%08x, so: 0x%08x, stack: 0x%08x\n",
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ret_fun, s0, frame_start);
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print_error_msg(g_dbg_msg);
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}
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return 0;
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}
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void exception_reg_dump(saved_registers *regs)
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{
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int i = 0;
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iot_sprintf(g_dbg_msg, "exception registers dump\n");
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print_error_msg(g_dbg_msg);
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iot_sprintf(g_dbg_msg, "ra = 0x%08x\n", regs->ra);
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print_error_msg(g_dbg_msg);
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iot_sprintf(g_dbg_msg, "sp = 0x%08x\n", regs->sp);
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print_error_msg(g_dbg_msg);
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iot_sprintf(g_dbg_msg, "gp = 0x%08x\n", regs->gp);
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print_error_msg(g_dbg_msg);
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iot_sprintf(g_dbg_msg, "tp = 0x%08x\n", regs->tp);
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print_error_msg(g_dbg_msg);
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for(i=0; i<3; i++) {
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iot_sprintf(g_dbg_msg, "t%d = 0x%08x\n", i, regs->t0_2[i]);
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print_error_msg(g_dbg_msg);
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}
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iot_sprintf(g_dbg_msg, "fp = 0x%08x\n", regs->fp);
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print_error_msg(g_dbg_msg);
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iot_sprintf(g_dbg_msg, "s1 = 0x%08x\n", regs->s1);
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print_error_msg(g_dbg_msg);
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for(i=0; i<8; i++) {
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iot_sprintf(g_dbg_msg, "a%d = 0x%08x\n", i, regs->a0_7[i]);
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print_error_msg(g_dbg_msg);
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}
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for(i=2; i<12; i++) {
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iot_sprintf(g_dbg_msg, "s%d = 0x%08x\n", i, regs->s2_11[i-2]);
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print_error_msg(g_dbg_msg);
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}
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for(i=3; i<5; i++) {
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iot_sprintf(g_dbg_msg, "t%d = 0x%08x\n", i, regs->t3_4[i-3]);
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print_error_msg(g_dbg_msg);
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}
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iot_sprintf(g_dbg_msg, "t5 = 0x%08x\n", regs->t5);
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print_error_msg(g_dbg_msg);
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iot_sprintf(g_dbg_msg, "t6 = 0x%08x\n", regs->t6);
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print_error_msg(g_dbg_msg);
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}
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void exception_handler_2(uintptr_t mcause, uintptr_t epc, saved_registers *reg)
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{
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uint32_t mbadaddr = 0;
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/* save cpu1's crash state */
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g_bbcpu_state.crash = 1;
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g_bbcpu_state.mcause = mcause;
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g_bbcpu_state.mepc = epc;
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g_bbcpu_state.trap_frame = reg;
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// disable iot_printf
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iot_print_config(false);
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// dump exception registers
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exception_reg_dump(reg);
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//disble global interrupt;
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__asm volatile ( "csrc mstatus,8" );
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__asm volatile ( "csrr %0, mbadaddr" : "=r"(mbadaddr));
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switch(mcause) {
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case 0x0:
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iot_sprintf(g_dbg_msg, "mcause: 0x%02x[Instruction address misaligned]\n",
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mcause);
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print_error_msg(g_dbg_msg);
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break;
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case 0x1:
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iot_sprintf(g_dbg_msg, "mcause: 0x%02x[Instruction access fault]\n",
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mcause);
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print_error_msg(g_dbg_msg);
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break;
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case 0x2:
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iot_sprintf(g_dbg_msg, "mcause: 0x%02x[Illegal instruction]\n", mcause);
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print_error_msg(g_dbg_msg);
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iot_illegal_instruct(epc);
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break;
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case 0x3:
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iot_sprintf(g_dbg_msg, "mcause: 0x%02x[Breakpoint]\n", mcause);
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print_error_msg(g_dbg_msg);
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break;
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case 0x4:
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iot_sprintf(g_dbg_msg, "mcause: 0x%02x[Load address misaligned]\n",
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mcause);
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print_error_msg(g_dbg_msg);
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break;
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case 0x5:
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iot_sprintf(g_dbg_msg, "mcause: 0x%02x[Load access fault]\n", mcause);
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print_error_msg(g_dbg_msg);
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break;
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case 0x6:
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iot_sprintf(g_dbg_msg, "mcause: 0x%02x[Store address misaligned]\n",
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mcause);
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print_error_msg(g_dbg_msg);
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break;
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case 0x7:
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iot_sprintf(g_dbg_msg, "mcase: 0x%02x[Store access fault]\n", mcause);
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print_error_msg(g_dbg_msg);
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break;
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default:
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iot_sprintf(g_dbg_msg, "mcause: 0x%02x\n", mcause);
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print_error_msg(g_dbg_msg);
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break;
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}
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iot_sprintf(g_dbg_msg, "mepc: 0x%08x, mbadaddr: 0x%08x, core:%d\n", epc,
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mbadaddr, cpu_get_mhartid());
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print_error_msg(g_dbg_msg);
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iot_backtrace(epc, reg);
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while(1);
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}
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uintptr_t handle_trap_2(uintptr_t mcause, uintptr_t epc, saved_registers *reg)
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{
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if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT) {
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intc_handler(cpu_get_mhartid());
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}else {
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exception_handler_2(mcause, epc, reg);
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}
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return epc;
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}
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void _init_2()
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{
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write_csr(mtvec, &def_trap_entry_2);
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clear_csr(mie, MIP_MEIP);
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clear_csr(mie, MIP_MTIP);
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iot_interrupt_init(cpu_get_mhartid());
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set_csr(mie, MIP_MEIP);
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// Enable interrupts in general.
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set_csr(mstatus, MSTATUS_MIE);
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wdg_deinit(cpu_get_mhartid());
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g_bbcpu_state.flags = CPU_FLAG_RUNNING;
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}
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void _fini()
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{
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}
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void assert_failed( unsigned char *pucFile, unsigned long ulLine )
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{
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( void ) pucFile;
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( void ) ulLine;
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char *filename;
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//disble global interrupt;
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__asm volatile ( "csrc mstatus,8" );
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uint32_t ast_ra = 0;
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__asm volatile ("mv %0, ra" : "=r"(ast_ra));
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// disable iot_printf
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iot_print_config(false);
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g_bbcpu_state.assert_failed = 1;
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if (pucFile && (filename = FILENAME((char*)pucFile))) {
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os_mem_cpy(g_bbcpu_state.assert_info.file, filename, 32);
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iot_sprintf(g_dbg_msg, "%s:%d ra:0x%08x Asserted!\n",
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filename, ulLine, ast_ra);
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} else {
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os_mem_set(g_bbcpu_state.assert_info.file, 0, 32);
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iot_sprintf(g_dbg_msg, "NULL:%d ra:0x%08x Asserted!\n",
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ulLine, ast_ra);
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}
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print_error_msg(g_dbg_msg);
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g_bbcpu_state.assert_info.line = ulLine;
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iot_sprintf(g_dbg_msg, "bbcpu: mcause: 0x%08x, mepc: 0x%08x\n",
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g_bbcpu_state.mcause, g_bbcpu_state.mepc);
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print_error_msg(g_dbg_msg);
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/* do a breakpoint exception */
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asm volatile("ebreak");
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}
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void assert_failed_simple()
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{
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g_bbcpu_state.assert_failed = 1;
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os_mem_set(g_bbcpu_state.assert_info.file, 0, 32);
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g_bbcpu_state.assert_info.line = 0;
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//disble global interrupt;
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__asm volatile ( "csrc mstatus,8" );
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// disable iot_printf
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iot_print_config(false);
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iot_sprintf(g_dbg_msg, "NULL:0 Asserted!\n");
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print_error_msg(g_dbg_msg);
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/* do a breakpoint exception */
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asm volatile("ebreak");
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}
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